CN106992164A - 一种微电子封装用铜合金单晶键合丝及其制备方法 - Google Patents
一种微电子封装用铜合金单晶键合丝及其制备方法 Download PDFInfo
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Abstract
一种微电子封装用铜合金单晶键合丝及其制备方法,该键合丝是以高纯铜为主体材料,包括银、钪、铁、钛等微量金属材料。其组成键合丝的材料各成分重量百分比为:铜含量为:99.9%‑99.95%、银含量为0.01%‑0.02%、钪含量为0.01%‑0.02%、铁含量为:0.001%‑0.015%、钛含量为0.001%‑0.01%;其制造方法包括:提取纯度大于99.99%的高纯铜,制备成铜合金铸锭,再制成铸态铜合金单晶母线,将单晶母线拉制成1mm左右的单晶丝经热处理后,再经精密拉拔、热处理、清洗后制成不同规格的铜合金单晶键合丝。
Description
技术领域
本发明涉及微电子后道封装工序用金属键合丝及其制备方法,尤其涉及一种微电子封装用铜合金单晶键合丝及其制备方法。
背景技术
目前用于集成电路、半导体分立器件等领域的引线封装键合丝最为广泛采用的是黄金和白银类键合丝。由于黄金和白银属贵重金属,价格昂贵且日益上涨,给用量最大的中低端LED、IC封装用户带来沉重的成本压力。同时,随着集成电路及半导体器件封装技术向多引线化、高集成度和小型化发展,封装材料要求采用线径更细、电学性能更好的键合丝进行窄间距、长距离的键合。传统的金丝和银丝已经在导电和导热性能上逐步趋近于极限。因而业界急需成本相对低廉、性能稳定可靠的新型键合丝材料用以取代黄金和银键合丝。
铜丝作为内引线,具有比金丝高的导电和导热性能,可以用于制造对电流负载要求更高的功率器件,而且可以使高密度封装时的散热更为容易。铜丝较强的抗拉强度可以使丝线直径变得更细,焊盘尺寸和焊盘间距也能相应减小,价格比贵金属键合丝材便宜很多。但铜的易氧化、高硬度、成球差以及进行树脂封装时易引起线材表面腐蚀是人们最为关注的缺点。尤其在键合铜成球工艺的加热环境下,铜表面极易氧化,形成的氧化膜降低了铜线的键合性能。为了解决上述问题,研发铜键合丝的主要方法有两种:高纯铜丝表面涂层和合金化。
表面涂层主要采用铜线表面镀钯,铜丝芯材为99.9999%铜,镀钯工艺为真空镀膜,多出一道工序,成本过于高昂,而且镀钯的目的是隔绝铜丝与空气的接触,降低其氧化速率,但在烧球键合过程中,由于镀钯层与基材铜丝的再结晶温度不同,容易发生歪球等不良工艺。合金化则是通过添加合金元素形成均匀的铜合金来改善铜线的抗氧化性、耐腐蚀性和成球性,降低硬度等,但又不损失铜的导电导热性,这是目前研发高质量铜合金键合丝的主要方向。然而,目前报道的铜合金键合丝,没有一种能够改善铜键合丝的所有缺点,有的只是改善了其抗氧气性,但其导电性降低;有的改善其抗氧化性和耐腐蚀性,但其硬度较高,塑性较差,不能连续拉成细丝。究其原因,主要是这些铜合金键合丝只考虑添加合金元素来改善抗氧化性,细化晶粒,但这些增加的晶界会降低导电性和和耐腐蚀性,增加了硬度,没有从微观结构和合金成分综合考虑。
发明内容
本发明的目的是克服以上现有技术不足,提供一种微电子封装用铜合金单晶键合丝及其制备方法,它克服现有铜合金类键合丝表面易氧化、耐腐蚀性差、导电性降低、硬度高和拉拔断线等问题。
本发明为解决其技术问题所采用的技术方案是:一种微电子封装用铜合金单晶键合丝,组成键合丝的材料各成分重量百分比为:银(Ag)含量为0.01%-0.02%、钪(Sc)含量为0.01%-0.02%、铁(Fe)含量为:0.001%-0.015%、钛(Ti)含量为0.001%-0.01%,其余为铜和不可避免的杂质,之和等于100%。要求铜的纯度大于99.99%、银的纯度大于99.999%、钪的纯度大于99.999%、铁、钛的纯度大于99.999%。
本发明的技术方案通过以下制备方法或工艺予以解决:
① 提取高纯铜:将TU00铜(99.99%铜)作为阳极浸入电解液中,以高纯铜箔作为阴极浸入电解液中;在阳极、阴极之间输入(7-9)V、(2.5-3.5)A的直流电,以补充新鲜电解液方式维持电解液温度不超过60℃,待阴极积聚一定重量的纯度大于99.9999%的高纯铜时及时更换高纯铜箔,再经清洗、烘干备用。
② 制备成铜合金铸锭:提取纯度大于99.9999%的高纯铜,然后加入银、钪、铁、钛;其成分含量按照重量百分比分别为:银占0.01%-0.02%、钪占0.01%-0.02%、铁占0.001%-0.015%,钛占0.001%-0.01%,其余为铜和不可避免的杂质,之和等于100%。这些金属经机械混合后放入高纯石墨坩埚中,在氩气保护条件下使用感应电炉加热使其熔化,进而制备成铜合金铸锭。
③ 连铸成铸态铜合金单晶母线:将制备好的铜合金铸锭加入有氮气保护的水平连铸金属单晶连铸室,应用中频感应加热至(1100-1200)℃,待完全熔化、精炼和除气后,将熔液注入连铸室中间的储液池保温,在维持(2-5)L/min净化氮气流量的连铸室中,完成对铜合金熔液的水平单晶连铸,得到Φ3mm左右、纵向和横向晶粒数均为1个的铸态铜合金单晶母线。
④ 粗拔:将Φ3mm左右的铸态铜合金单晶母线拉拔成直径为1mm左右的铜合金单晶丝。
⑤ 热处理:将直径为1mm左右的铜合金单晶丝进行退火处理;退火温度为400-600oC,退火时间为2-6小时,保护气氛为95%N2+5%H2。
⑥ 精拔:将经退火处理的铜合金单晶丝精密拉拔成不同规格的(0.010mm-0.050mm)铜合金单晶键合丝。
⑦ 热处理:将精拔后的金银钯合金单晶键合丝进行退火处理;退火温度为400-600oC,退火时间为0.2-0.6秒,保护气氛为95%N2+5%H2。退火完成后,得到微电子封装用铜合金单晶键合丝。
⑧ 表面清洗:将退火处理后的微电子封装用铜合金单晶键合丝先经稀释后的酸液中进行清洗,然后经超声波清洗,再经高纯水清洗、烘干。
⑨ 分卷:将成品微电子封装用铜合金单晶键合丝进行复绕、分卷、包装。
本发明的原理:向铜中添加一定量银(Ag)元素的目的就是增加铜合金的抗氧化性,保证铜合金的导电和导热性;向铜中添加钪(Sc)能极大地影响铜合金的组织和性能,可大幅地提高铜合金的强度,还能保持合金的塑性,且其耐腐蚀性和成球性(焊接性能)优异。因为钪既是稀土金属又是过渡族金属,它在铜合金中既有稀土元素的净化和改善铸锭组织的作用,又有过渡族元素的再结晶抑制剂作用。向铜中添加微量的钛(Ti)的主要作用是降低Sc的添加量,降低合金的成本,同时产生很强的变质作用和抑制再结晶能力。向铜中添加微量的铁(Fe)可以进一步保证铜合金的导电性,降低硬度。所有添加的微量元素银、钪、钛和铁都可以与铜形成固溶体,而不会形成金属间化合物,保证铜合金良好的塑性。而且,将铜合金提拉成单晶组织,没有晶界存在,这样可以进一步降低硬度,保证良好的导电性和塑性。
本发明具有以下优点:本发明的微电子封装用铜合金单晶键合丝具有良好抗氧化性和成球性、高导电和导热性、低硬度、良好塑性和耐腐蚀性。能够适应电子封装高性能、多功能、微型化、低成本的需求。
具体实施方式
实施例1
本发明是这样实现的,一种以高纯铜为主体材料的铜合金单晶键合丝,组成该键合丝的材料由下列重量百分比的原材料组成:银(Ag)含量为0.016%、钪(Sc)含量为0.013%、铁(Fe)含量为:0.012%、钛(Ti)含量为0.006%,其余为铜和不可避免的杂质,之和等于100%;要求铜的纯度大于99.99%、银的纯度大于99.999%、钪的纯度大于99.999%、铁、钛的纯度大于99.999%。
微电子封装用铜合金单晶键合丝的制备工艺步骤和方法如下:
① 提取高纯铜:将TU00铜(99.99%铜)作为阳极浸入电解液中,以高纯铜箔作为阴极浸入电解液中;在阳极、阴极之间输入9V、2.5A的直流电,以补充新鲜电解液方式维持电解液温度不超过60℃,待阴极积聚一定重量的纯度大于99.9999%的高纯铜时及时更换高纯铜箔,再经清洗、烘干备用。
② 制备成铜合金铸锭:提取纯度大于99.9999%的高纯铜,然后加入银、钪、铁、钛;其成分含量按照重量百分比分别为:银占0.016%、钪占0.013%、铁占0.012%,钛占0.006%,其余为铜和不可避免的杂质,之和等于100%。这些金属经机械混合后放入高纯石墨坩埚中,在氩气保护条件下使用感应电炉加热使其熔化,进而制备成铜合金铸锭。
③ 连铸成铸态铜合金单晶母线:将制备好的铜合金铸锭加入有氮气保护的水平连铸金属单晶连铸室,应用中频感应加热至1200℃,待完全熔化、精炼和除气后,将熔液注入连铸室中间的储液池保温,在维持5L/min净化氮气流量的连铸室中,完成对铜合金熔液的水平单晶连铸,得到Φ3mm左右、纵向和横向晶粒数均为1个的铸态铜合金单晶母线。
④ 粗拔:将Φ3mm左右的铸态铜合金单晶母线拉拔成直径为1mm左右的铜合金单晶丝。
⑤ 热处理:将直径为1mm左右的铜合金单晶丝进行退火处理;退火温度为600oC,退火时间为3小时,保护气氛为95%N2+5%H2。
⑥ 精拔:将经退火处理的铜合金单晶丝精密拉拔成直径0.018mm铜合金单晶键合丝。
⑦ 热处理:将精拔后的铜合金单晶键合丝进行退火处理;退火温度为450oC,退火时间为0.2秒,保护气氛为95%N2+5%H2。退火完成后,得到微电子封装用铜合金单晶键合丝。
⑧ 表面清洗:将退火处理后的微电子封装用铜合金单晶键合丝先经稀释后的酸液中进行清洗,然后经超声波清洗,再经高纯水清洗、烘干。
⑨ 分卷:将成品微电子封装用铜合金单晶键合丝进行复绕、分卷、包装。
该铜合金单晶键合丝拉断力大于 0.055 N,延伸率大于13%,最小熔断电流为0.29A,表明其导电性好,且硬度适中,焊接成球性好,非常适用于高密度,多引脚集成电路封装。
实施例2
本发明是这样实现的,一种以高纯铜为主体材料的铜合金单晶键合丝,组成该键合丝的材料由下列重量百分比的原材料组成:银(Ag)含量为0.02%、钪(Sc)含量为0.018%、铁(Fe)含量为:0.008%、钛(Ti)含量为0.003%,其余为铜和不可避免的杂质,之和等于100%;要求铜的纯度大于99.99%、银的纯度大于99.999%、钪的纯度大于99.999%、铁、钛的纯度大于99.999%。
微电子封装用铜合金单晶键合丝的制备工艺步骤和方法如下:
① 提取高纯铜:将TU00铜(99.99%铜)作为阳极浸入电解液中,以高纯铜箔作为阴极浸入电解液中;在阳极、阴极之间输入8V、3A的直流电,以补充新鲜电解液方式维持电解液温度不超过60℃,待阴极积聚一定重量的纯度大于99.9999%的高纯铜时及时更换高纯铜箔,再经清洗、烘干备用。
② 制备成铜合金铸锭:提取纯度大于99.9999%的高纯铜,然后加入银、钪、铁、钛;其成分含量按照重量百分比分别为:银占0.02%、钪占0.018%、铁占0.008%,钛占0.003%,其余为铜和不可避免的杂质,之和等于100%。这些金属经机械混合后放入高纯石墨坩埚中,在氩气保护条件下使用感应电炉加热使其熔化,进而制备成铜合金铸锭。
③ 连铸成铸态铜合金单晶母线:将制备好的铜合金铸锭加入有氮气保护的水平连铸金属单晶连铸室,应用中频感应加热至1150℃,待完全熔化、精炼和除气后,将熔液注入连铸室中间的储液池保温,在维持4L/min净化氮气流量的连铸室中,完成对铜合金熔液的水平单晶连铸,得到Φ3mm左右、纵向和横向晶粒数均为1个的铸态铜合金单晶母线。
④ 粗拔:将Φ3mm左右的铸态铜合金单晶母线拉拔成直径为1mm左右的铜合金单晶丝。
⑤ 热处理:将直径为1mm左右的铜合金单晶丝进行退火处理;退火温度为500oC,退火时间为5小时,保护气氛为95%N2+5%H2。
⑥ 精拔:将经退火处理的铜合金单晶丝精密拉拔成直径0.023mm铜合金单晶键合丝。
⑦ 热处理:将精拔后的铜合金单晶键合丝进行退火处理;退火温度为500oC,退火时间为0.3秒,保护气氛为95%N2+5%H2。退火完成后,得到微电子封装用铜合金单晶键合丝。
⑧ 表面清洗:将退火处理后的微电子封装用铜合金单晶键合丝先经稀释后的酸液中进行清洗,然后经超声波清洗,再经高纯水清洗、烘干。
⑨ 分卷:将成品微电子封装用铜合金单晶键合丝进行复绕、分卷、包装。
该铜合金单晶键合丝拉断力大于 0.088 N,延伸率大于16%,最小熔断电流为0.31A,且硬度适中,焊接成球性好,非常适用于高密度,多引脚集成电路封装。
实施例3
本发明是这样实现的,一种以高纯铜为主体材料的铜合金单晶键合丝,组成该键合丝的材料由下列重量百分比的原材料组成:银(Ag)含量为0.01%、钪(Sc)含量为0.01%、铁(Fe)含量为:0.01%、钛(Ti)含量为0.01%,其余为铜和不可避免的杂质,之和等于100%;要求铜的纯度大于99.99%、银的纯度大于99.999%、钪的纯度大于99.999%、铁、钛的纯度大于99.999%。
微电子封装用铜合金单晶键合丝的制备工艺步骤和方法如下:
① 提取高纯铜:将TU00铜(99.99%铜)作为阳极浸入电解液中,以高纯铜箔作为阴极浸入电解液中;在阳极、阴极之间输入7V、3.5A的直流电,以补充新鲜电解液方式维持电解液温度不超过60℃,待阴极积聚一定重量的纯度大于99.9999%的高纯铜时及时更换高纯铜箔,再经清洗、烘干备用。
② 制备成铜合金铸锭:提取纯度大于99.9999%的高纯铜,然后加入银、钪、铁、钛;其成分含量按照重量百分比分别为:银占0.01%、钪占0.01%、铁占0.01%,钛占0.01%,其余为铜和不可避免的杂质,之和等于100%。这些金属经机械混合后放入高纯石墨坩埚中,在氩气保护条件下使用感应电炉加热使其熔化,进而制备成铜合金铸锭。
③ 连铸成铸态铜合金单晶母线:将制备好的铜合金铸锭加入有氮气保护的水平连铸金属单晶连铸室,应用中频感应加热至1100℃,待完全熔化、精炼和除气后,将熔液注入连铸室中间的储液池保温,在维持3L/min净化氮气流量的连铸室中,完成对铜合金熔液的水平单晶连铸,得到Φ3mm左右、纵向和横向晶粒数均为1个的铸态铜合金单晶母线。
④ 粗拔:将Φ3mm左右的铜合金单晶母线拉拔成直径为1mm左右的铜合金单晶丝。
⑤ 热处理:将直径为1mm左右的铜合金单晶丝进行退火处理;退火温度为400oC,退火时间为6小时,保护气氛为95%N2+5%H2。
⑥ 精拔:将经退火处理的铜合金单晶丝精密拉拔成直径0.010mm铜合金单晶键合丝。
⑦ 热处理:将精拔后的铜合金单晶键合丝进行退火处理;退火温度为600oC,退火时间为0.6秒,保护气氛为95%N2+5%H2。退火完成后,得到微电子封装用铜合金单晶键合丝。
⑧ 表面清洗:将退火处理后的微电子封装用铜合金单晶键合丝先经稀释后的酸液中进行清洗,然后经超声波清洗,再经高纯水清洗、烘干。
⑨ 分卷:将成品微电子封装用铜合金单晶键合丝进行复绕、分卷、包装。
该铜合金单晶键合丝拉断力大于 0.043 N,延伸率大于11%,最小熔断电流为0.25A,且硬度适中,焊接成球性好,非常适用于高密度,多引脚集成电路封装。
Claims (2)
1.一种微电子封装用铜合金单晶键合丝,包括银、钪、铁、钛等金属材料组成的一种微电子封装用铜合金单晶键合丝及其制备方法,其组成键合丝的材料各成分重量百分比为:银(Ag)含量为0.01%-0.02%、钪(Sc)含量为0.01%-0.02%、铁(Fe)含量为:0.001%-0.015%、钛(Ti)含量为0.001%-0.01%,其余为铜和不可避免的杂质,之和等于100%;要求铜的纯度大于99.99%、银的纯度大于99.999%、钪的纯度大于99.999%、铁、钛的纯度大于99.999%。
2.如权利要求1所述的一种微电子封装用铜合金单晶键合丝的制备方法,其制作的工艺步骤和方法如下:
① 提取高纯铜:以国家标准GB/T 5231-2012中TU00铜(99.99%铜)为基材,经电镀后提取纯度大于99.9999%的高纯铜,再经清洗、烘干备用;
② 制备成铜合金铸锭:提取纯度大于99.9999%的高纯铜,然后加入银、钪、铁、钛;其成分含量按照重量百分比分别为:银占0.01%-0.02%、钪占0.01%-0.02%、铁占0.001%-0.015%,钛占0.001%-0.01%,其余为铜和不可避免的杂质,之和等于100%;这些金属经机械混合后放入高纯石墨坩埚中,在氩气保护条件下使用感应电炉加热使其熔化,进而制备成铜合金铸锭;
③ 连铸成铸态铜合金单晶母线:将制备好的铜合金铸锭加入有氮气保护的水平连铸金属单晶连铸室,应用中频感应加热熔化、精炼和除气后,将熔液注入储液池保温,完成对铜合金熔液的水平单晶连铸,得到Φ3mm左右、纵向和横向晶粒数均为1个的铸态铜合金单晶母线;
④ 粗拔:将Φ3mm左右的铸态铜合金单晶母线拉拔成直径为1mm左右的铜合金单晶丝;
⑤ 热处理:将直径为1mm左右的铜合金单晶丝进行退火;退火温度为400-600oC,退火时间为2-6小时,保护气氛为95%N2+5%H2;
⑥ 精拔:对经热处理后的铜合金单晶丝精密拉拔成直径分别为10μm-50μm的成品铜合金单晶键合丝;
⑦ 热处理:将精拔后的铜合金单晶键合丝进行退火;退火温度为400-600oC,退火时间为0.2-0.6秒,保护气氛为95%N2+5%H2;
⑧ 表面清洗:先用稀释后的酸液对键合丝进行清洗,然后经超声波清洗,再经高纯水清洗、烘干;
⑨ 分卷:将成品铜合金单晶键合丝进行复绕、分卷、包装。
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107799496A (zh) * | 2017-09-01 | 2018-03-13 | 华南理工大学 | 一种电子封装用高可靠性铜合金键合丝及其制备方法 |
CN106992164B (zh) * | 2017-04-10 | 2019-03-01 | 江西蓝微电子科技有限公司 | 一种微电子封装用铜合金单晶键合丝及其制备方法 |
CN109473413A (zh) * | 2018-11-09 | 2019-03-15 | 上海理工大学 | 一种抗氧化的铜基键合丝及其制备方法 |
CN110592420A (zh) * | 2019-10-23 | 2019-12-20 | 常州恒丰特导股份有限公司 | 高分段玻璃保险管用镀锡银铜合金熔断丝及其制备方法 |
CN114369735A (zh) * | 2021-12-16 | 2022-04-19 | 虹华科技股份有限公司 | 一种电子芯片用高纯铜铜丝的加工工艺 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1985014A (zh) * | 2004-07-15 | 2007-06-20 | 普兰西欧洲股份公司 | 铜合金制造的导线材料 |
CN102268616A (zh) * | 2011-06-30 | 2011-12-07 | 蒙特集团(香港)有限公司 | 一种非晶态合金改性切割钢线 |
CN102517528A (zh) * | 2011-12-09 | 2012-06-27 | 徐云管 | 一种单晶合金材料制造超高张力线的方法 |
CN104911391A (zh) * | 2015-07-03 | 2015-09-16 | 苏州科茂电子材料科技有限公司 | 一种同轴电缆用铜基合金材料及其制备方法 |
CN105070346A (zh) * | 2015-09-02 | 2015-11-18 | 赣州西维尔金属材料科技有限公司 | 一种通信设备用半柔电缆镀银铜线内导体 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106992164B (zh) * | 2017-04-10 | 2019-03-01 | 江西蓝微电子科技有限公司 | 一种微电子封装用铜合金单晶键合丝及其制备方法 |
-
2017
- 2017-04-10 CN CN201710228970.0A patent/CN106992164B/zh active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1985014A (zh) * | 2004-07-15 | 2007-06-20 | 普兰西欧洲股份公司 | 铜合金制造的导线材料 |
CN102268616A (zh) * | 2011-06-30 | 2011-12-07 | 蒙特集团(香港)有限公司 | 一种非晶态合金改性切割钢线 |
CN102517528A (zh) * | 2011-12-09 | 2012-06-27 | 徐云管 | 一种单晶合金材料制造超高张力线的方法 |
CN104911391A (zh) * | 2015-07-03 | 2015-09-16 | 苏州科茂电子材料科技有限公司 | 一种同轴电缆用铜基合金材料及其制备方法 |
CN105070346A (zh) * | 2015-09-02 | 2015-11-18 | 赣州西维尔金属材料科技有限公司 | 一种通信设备用半柔电缆镀银铜线内导体 |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106992164B (zh) * | 2017-04-10 | 2019-03-01 | 江西蓝微电子科技有限公司 | 一种微电子封装用铜合金单晶键合丝及其制备方法 |
CN107799496A (zh) * | 2017-09-01 | 2018-03-13 | 华南理工大学 | 一种电子封装用高可靠性铜合金键合丝及其制备方法 |
WO2019041587A1 (zh) * | 2017-09-01 | 2019-03-07 | 华南理工大学 | 一种电子封装用高可靠性铜合金键合丝及其制备方法 |
CN107799496B (zh) * | 2017-09-01 | 2020-05-22 | 华南理工大学 | 一种电子封装用高可靠性铜合金键合丝及其制备方法 |
CN109473413A (zh) * | 2018-11-09 | 2019-03-15 | 上海理工大学 | 一种抗氧化的铜基键合丝及其制备方法 |
CN110592420A (zh) * | 2019-10-23 | 2019-12-20 | 常州恒丰特导股份有限公司 | 高分段玻璃保险管用镀锡银铜合金熔断丝及其制备方法 |
CN110592420B (zh) * | 2019-10-23 | 2021-08-13 | 常州恒丰特导股份有限公司 | 高分断玻璃保险管用镀锡银铜合金熔断丝及其制备方法 |
CN114369735A (zh) * | 2021-12-16 | 2022-04-19 | 虹华科技股份有限公司 | 一种电子芯片用高纯铜铜丝的加工工艺 |
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