CN103779309A - 镀金金银钯合金单晶键合丝及其制造方法 - Google Patents

镀金金银钯合金单晶键合丝及其制造方法 Download PDF

Info

Publication number
CN103779309A
CN103779309A CN201410024437.9A CN201410024437A CN103779309A CN 103779309 A CN103779309 A CN 103779309A CN 201410024437 A CN201410024437 A CN 201410024437A CN 103779309 A CN103779309 A CN 103779309A
Authority
CN
China
Prior art keywords
gold
silver
purity
alloy
plated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201410024437.9A
Other languages
English (en)
Inventor
徐云管
李湘平
彭庶瑶
梁建华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JIANGXI LAN WEI ELECTRONIC TECHNOLOGY Co Ltd
Original Assignee
JIANGXI LAN WEI ELECTRONIC TECHNOLOGY Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by JIANGXI LAN WEI ELECTRONIC TECHNOLOGY Co Ltd filed Critical JIANGXI LAN WEI ELECTRONIC TECHNOLOGY Co Ltd
Priority to CN201410024437.9A priority Critical patent/CN103779309A/zh
Publication of CN103779309A publication Critical patent/CN103779309A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/43—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/43—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/43—Manufacturing methods
    • H01L2224/431—Pre-treatment of the preform connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/43—Manufacturing methods
    • H01L2224/431—Pre-treatment of the preform connector
    • H01L2224/4312—Applying permanent coating, e.g. in-situ coating
    • H01L2224/43125—Plating, e.g. electroplating, electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/43—Manufacturing methods
    • H01L2224/438—Post-treatment of the connector
    • H01L2224/43848—Thermal treatments, e.g. annealing, controlled cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45139—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45565—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45599—Material
    • H01L2224/456—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45644—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electroplating Methods And Accessories (AREA)

Abstract

本发明提供了一种镀金金银钯合金单晶键合丝及其制造方法，该键合丝是以高纯银为主体材料，包括金、钯、铕、镧等微量金属材料。其组成键合丝的材料各成分重量百分比为：银含量为：97.713%-98.157%、金含量为1.8%-2.2%、钯含量为0.04%-0.08%、铕含量为：0.002%-0.004%、镧含量为0.001%-0.003%；其制造方法包括：提取纯度大于99.9999%的高纯银，制备成银合金铸锭，再制成铸态金银钯合金单晶母线，将单晶母线拉制成1mm左右的单晶丝，经热处理后在其表面电镀纯金保护层，再经精密拉拔、热处理、清洗后制成不同规格的镀金金银钯合金单晶键合丝。

Description

镀金金银钯合金单晶键合丝及其制造方法
技术领域
本发明属于微电子技术领域，涉及微电子后道封装工序用金属键合丝及其制造方法，尤其涉及一种镀金金银钯等合金材料制作的镀金金银钯合金单晶键合丝及其制造方法。
背景技术
目前用于集成电路、半导体分立器件等领域的引线封装键合丝最为广泛采用的是黄金类键合丝。由于黄金属贵重金属，价格昂贵且日益上涨，给用量最大的中低端LED、IC封装用户带来沉重的成本压力。因而业界急需成本相对低廉、性能稳定可靠的新型键合丝材料用以取代黄金键合丝。以高纯银为主体材料的镀金金银钯合金单晶键合丝既有银基类键合丝的优点又兼顾黄金类键合丝的优点，是一种价格相对低廉且性能又稳定可靠的一种新型键合丝。
发明内容
本发明的目的是提供一种以高纯银为主体材料的镀金金银钯合金单晶键合丝及其制造方法，它克服现有合金类键合铜丝、铝丝表面易氧化、高温稳定性差和拉拔断线问题，以及黄金类键合丝生产成本高等不足。
为达到上述目的，本发明所采用的技术方案是：一种镀金金银钯合金单晶键合丝，组成键合丝的材料各成分重量百分比为：金（Au）占1.8%-2.2%、钯（Pd）占0.04%-0.08%、铕（Eu）占0.002%-0.004%、镧（La）占0.001%-0.003%，银（Ag）占97.713%-98.157%。
要求金的纯度大于99.99%、银的纯度大于99.9999%、钯的纯度大于99.999%、铕的纯度大于99.9%、镧的纯度大于99.5%。
所述镀金金银钯合金单晶键合丝的制造方法步骤如下：
① 提取高纯银：将1号银（IC-Ag99.99）作为阳极浸入电解液中，以高纯银箔作为阴极浸入电解液中；在阳极、阴极之间输入（7-9）V、（2.5-3.5）A的直流电，以补充新鲜电解液方式维持电解液温度不超过60℃，待阴极积聚一定重量的纯度大于99.9999%的高纯银时及时更换高纯银箔，再经清洗、烘干备用。
② 制备成银合金铸锭：提取纯度大于99.9999%的高纯银，然后加入金、钯、铕、镧，成分含量按照重量百分比分别为：金占0.9%-1.1%、钯占0.04%-0.08%、铕占0.002%-0.004%、镧占0.001%-0.003%，银占97.713%-98.157%，因为留有后续工艺中电镀金的余量，所以这里各项材料质量百分比之和不等于100%。这些金属经机械混合后放入高纯石墨坩埚中，在惰性气体保护条件下使用感应电炉加热使其熔化，进而制备成银合金铸锭。
③ 连铸成铸态金银钯合金单晶母线：将制备好的银合金铸锭加入有氮气保护的水平连铸金属单晶连铸室，应用中频感应加热至（1100-1150）℃，待完全熔化、精炼和除气后，将熔液注入连铸室中间的储液池保温，在维持（2-5）L/min净化氮气流量的连铸室中，完成对金银钯合金熔液的水平单晶连铸，得到Φ3mm左右、纵向和横向晶粒数均为1个的铸态金银钯合金单晶母线。
④ 粗拔：将Φ3mm左右的金银钯合金单晶母线拉拔成直径为1mm左右的金银钯合金单晶丝。
⑤ 热处理：将直径为1mm左右的金银钯合金单晶丝进行退火处理。
⑥ 表面镀金：采用常规电镀设备和工艺，将退火后的1mm左右的金银钯合金单晶丝电镀纯金防氧化保护层，电镀用金的纯度大于99.99%；电流密度（4-4.5）A/dm2，镀层厚度控制在1μm-1.5μm，收线速度为（4-5）m/min；经镀金后的镀金金银钯合金单晶丝中金占总重量的百分比控制在1.8%-2.2%。
⑦ 精拔：将直径为1mm左右的镀金金银钯合金单晶丝精密拉拔成不同规格的（0.013mm-0.050mm）镀金金银钯合金单晶键合丝。
⑧ 热处理：将精拔后的镀金金银钯合金单晶键合丝进行退火处理。
⑨ 表面清洗：将退火处理后的镀金金银钯合金单晶键合丝先经稀释后的酸液中进行清洗，然后经超声波清洗，再经高纯水清洗、烘干。
⑩ 分卷：将成品镀金金银钯合金单晶键合丝进行复绕、分卷、包装。
本发明的技术效果是：以高纯银为主体材料的镀金金银钯合金单晶键合丝既有银基类键合丝的优点又兼顾黄金类键合丝的优点，是一种价格相对低廉且性能又稳定可靠的一种新型键合丝。它它克服现有合金类键合铜丝、铝丝表面易氧化、高温稳定性差和拉拔断线问题，以及黄金类键合丝生产成本高等不足。
具体实施方式
为了便于理解，下面结合具体实施例对本发明予以进一步说明。
实施例1
一种以高纯银为主体材料的镀金金银钯合金单晶键合丝，组成该键合丝的材料由下列重量百分比的原材料组成：金（Au)占1.8%、钯（Pd)占0.04%、铕（Eu）占0.002%、镧（La）占0.001%，银（Ag）占98.157%；要求金的纯度大于99.99%、银的纯度大于99.9999%、钯的纯度大于99.999%、铕的纯度大于99.9%、镧的纯度大于99.5%。
其制作工艺步骤和方法如下：
① 提取高纯银：以国家标准GB/T4135中1号银（IC-Ag99.99）为基材，提取纯度大于99.9999%的高纯银，经清洗、烘干备用。
② 制备成银合金铸锭：按前述的键合丝组成成分重量百分比准备原材料（这里的重量百分比是指各原材料占键合丝总质量的百分比而不是各原材料占制备银合金铸锭的原材料总质量的百分比），其中金（Au)所占重量百分比为0.9%而不是1.8%（金占1.8%指的是包括了后续工序中表面镀金的重量百分比），在高纯银内加入高纯金、钯、铕、镧，这些金属经机械混合后放入高纯石墨坩埚中，在惰性气体保护条件下使用感应电炉加热使其熔化，进而制备成银合金铸锭。
③ 连铸成铸态金银钯合金单晶母线：将制备好的银合金铸锭加入有氮气保护的水平连铸金属单晶连铸室，应用中频感应加热、熔化、精炼和除气后，将熔液注入储液池保温，完成对金银钯合金熔液的水平单晶连铸，得到Φ3mm左右、纵向和横向晶粒数均为1个的铸态金银钯合金单晶母线。
④ 粗拔：将Φ3mm左右的金银钯合金单晶母线拉拔成直径为1mm左右的金银钯合金单晶丝。
⑤ 热处理：将直径为1mm左右的金银钯合金单晶丝进行退火处理。
⑥ 表面镀金：采用常规电镀设备和工艺，对经过热处理的1mm左右的金银钯合金单晶丝电镀纯金防氧化保护层，要求金的纯度大于99.99%，电镀时电流密度4A/dm2，收线速度为4m/min，表面镀金层的厚度控制在1μm，经镀金后的镀金金银钯合金单晶丝中金占总重量的百分比为1.8%。
⑦ 精拔：将经退火处理的镀金金银钯合金单晶丝精密拉拔成不同规格的（0.013mm-0.050mm）镀金金银钯合金单晶键合丝。
⑧ 热处理：将精拔后的镀金金银钯合金单晶键合丝进行退火处理。
⑨ 表面清洗：将退火处理后的镀金金银钯合金单晶键合丝先经稀释后的酸液中进行清洗，然后经超声波清洗，再经高纯水清洗、烘干。
实施例2
本发明是这样实现的，一种以高纯银为主体材料的镀金金银钯合金单晶键合丝，组成该键合丝的材料由下列重量百分比的原材料组成：金（Au)占2.2%、钯（Pd)占0.08%、铕（Eu）占0.004%、镧（La）占0.003%，银（Ag）占97.713%；要求金的纯度大于99.99%、银的纯度大于99.9999%、钯的纯度大于99.999%、铕的纯度大于99.9%、镧的纯度大于99.5%。
其制作工艺步骤和方法如下：
① 提取高纯银：以国家标准GB/T4135中1号银（IC-Ag99.99）为基材，提取纯度大于99.9999%的高纯银，经清洗、烘干备用。
② 制备成银合金铸锭：按前述的键合丝组成成分重量百分比准备原材料，其中金（Au)所占重量百分比为1.1%，在高纯银内加入高纯金、钯、铕、镧，这些金属经机械混合后放入高纯石墨坩埚中，在惰性气体保护条件下使用感应电炉加热使其熔化，进而制备成银合金铸锭。
③ 连铸成铸态金银钯合金单晶母线：将制备好的银合金铸锭加入有氮气保护的水平连铸金属单晶连铸室，应用中频感应加热、熔化、精炼和除气后，将熔液注入储液池保温，完成对金银钯合金熔液的水平单晶连铸，得到Φ3mm左右、纵向和横向晶粒数均为1个的铸态金银钯合金单晶母线。
④ 粗拔：将Φ3mm左右的金银钯合金单晶母线拉拔成直径为1mm左右的金银钯合金单晶丝。
⑤ 热处理：将直径为1mm左右的金银钯合金单晶丝进行退火处理。
⑥ 表面镀金：采用常规电镀设备和工艺，对经过热处理的1mm左右的金银钯合金单晶丝电镀纯金防氧化保护层，要求金的纯度大于99.99%，电镀时电流密度4.5A/dm2，收线速度为5m/min，表面镀金层的厚度控制在1.5μm，经镀金后的镀金金银钯合金单晶丝中金占总重量的百分比为2.2%。
⑦ 精拔：将经退火处理的镀金金银钯合金单晶丝精密拉拔成不同规格的（0.013mm-0.050mm）金银钯合金单晶键合丝。
⑧ 热处理：将精拔后的镀金金银钯合金单晶键合丝进行退火处理。
⑨ 表面清洗：将退火处理后的镀金金银钯合金单晶键合丝先经稀释后的酸液中进行清洗，然后经超声波清洗，再经高纯水清洗、烘干。
实施例3
本发明是这样实现的，一种以高纯银为主体材料的镀金金银钯合金单晶键合丝，组成该键合丝的材料由下列重量百分比的原材料组成：金（Au)占2.0%、钯（Pd)占0.06%、铕（Eu）占0.003%、镧（La）占0.002%，银（Ag）占97.935%。要求金的纯度大于99.99%、银的纯度大于99.9999%、钯的纯度大于99.999%、铕的纯度大于99.9%、镧的纯度大于99.5%。
其制作工艺步骤和方法如下：                
① 提取高纯银：以国家标准GB/T4135中1号银（IC-Ag99.99）为基材，提取纯度大于99.9999%的高纯银，经清洗、烘干备用。
② 制备成银合金铸锭：按前述的键合丝组成成分重量百分比准备原材料，其中金（Au)所占重量百分比为1.0%，在高纯银内加入高纯金、钯、铕、镧，这些金属经机械混合后放入高纯石墨坩埚中，在惰性气体保护条件下使用感应电炉加热使其熔化，进而制备成银合金铸锭。
③ 连铸成铸态金银钯合金单晶母线：将制备好的银合金铸锭加入有氮气保护的水平连铸金属单晶连铸室，应用中频感应加热、熔化、精炼和除气后，将熔液注入储液池保温，完成对金银钯合金熔液的水平单晶连铸，得到Φ3mm左右、纵向和横向晶粒数均为1个的铸态金银钯合金单晶母线。
④ 粗拔：将Φ3mm左右的金银钯合金单晶母线拉拔成直径为1mm左右的金银钯合金单晶丝。
⑤ 热处理：将直径为1mm左右的金银钯合金单晶丝进行退火处理。
⑥ 表面镀金：采用常规电镀设备和工艺，对经过热处理的1mm左右的金银钯合金单晶丝电镀纯金防氧化保护层，要求金的纯度大于99.99%，电镀时电流密度4A/dm2，收线速度为5m/min，表面镀金层的厚度控制在1.3μm，经镀金后的镀金金银钯合金单晶丝中金占总重量的百分比为2.0%。
⑦ 精拔：将经退火处理的镀金金银钯合金单晶丝精密拉拔成不同规格的（0.013mm-0.050mm）镀金金银钯合金单晶键合丝。
⑧ 热处理：将精拔后的镀金金银钯合金单晶键合丝进行退火处理。
⑨ 表面清洗：将退火处理后的镀金金银钯合金单晶键合丝先经稀释后的酸液中进行清洗，然后经超声波清洗，再经高纯水清洗、烘干。

Claims (5)

1.一种镀金金银钯合金单晶键合丝，其特征是组成键合丝的材料各成分重量百分比为：金（Au）占1.8%-2.2%、钯（Pd）占0.04%-0.08%、铕（Eu）占0.002%-0.004%、镧（La）占0.001%-0.003%，银（Ag）占97.713%-98.157%。
2.如权利要求1所述的镀金金银钯合金单晶键合丝，其特征是所使用的材料中，金的纯度大于99.99%、银的纯度大于99.9999%、钯的纯度大于99.999%、铕的纯度大于99.9%、镧的纯度大于99.5%。
3.一种权利要求1或2所述的镀金金银钯合金单晶键合丝的制造方法，其特征是其制作的工艺步骤和方法如下：
① 提取高纯银：提取纯度大于99.9999%的高纯银，再经清洗、烘干备用；
② 制备成银合金铸锭：按下述成分含量按照重量百分比准备材料：金占0.9%-1.1%、钯占0.04%-0.08%、铕占0.002%-0.004%、镧占0.001%-0.003%，银占97.713-98.157%，这些金属经机械混合后放入高纯石墨坩埚中，在惰性气体保护条件下使用感应电炉加热使其熔化，进而制备成银合金铸锭；
③ 连铸成铸态金银钯合金单晶母线：将制备好的银合金铸锭加入有氮气保护的水平连铸金属单晶连铸室，应用中频感应加热熔化、精炼和除气后，将熔液注入储液池保温，完成对金银钯合金熔液的水平单晶连铸，得到Φ3mm左右，纵向和横向晶粒数均为1个的铸态金银钯合金单晶母线；
④ 粗拔：将Φ3mm左右的金银钯合金单晶母线拉拔成直径为1mm左右的金银钯合金单晶丝；
⑤ 热处理：将直径为1mm左右的金银钯合金单晶丝进行退火；
⑥ 表面镀金：对经热处理后的金银钯合金单晶丝电镀纯金保护层，电镀用金的纯度要求不低于99.99%，表面镀金层的厚度控制在1μm-1.5μm，经镀金后的镀金金银钯合金单晶丝中金占总重量的百分比为1.8%-2.2%；
⑦ 精拔：将直径为1 mm左右的经镀金后的镀金金银钯合金单晶丝精密拉拔成直径分别为13μm-50μm的镀金金银钯合金单晶键合丝；
⑧ 热处理：将精拔后的镀金金银钯合金单晶键合丝进行退火；
⑨ 表面清洗：先用稀释后的酸液对键合丝进行清洗，然后经超声波清洗，再经高纯水清洗、烘干；
 ⑩分卷：将成品镀金金银钯合金单晶键合丝进行复绕、分卷、包装。
4.如权利要3所述的一种镀金金银钯合金单晶键合丝的制造方法，其特征是：提取高纯银时以国家标准GB/T4135中1号银为基材，经电镀后提取纯度大于99.9999%的高纯银。
5.如权利要3所述的一种镀金金银钯合金单晶键合丝的制造方法，其特征是：表面镀金时电流密度（4-4.5）A/dm2，收线速度为（4-5）m/min。
CN201410024437.9A 2014-01-20 2014-01-20 镀金金银钯合金单晶键合丝及其制造方法 Pending CN103779309A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201410024437.9A CN103779309A (zh) 2014-01-20 2014-01-20 镀金金银钯合金单晶键合丝及其制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410024437.9A CN103779309A (zh) 2014-01-20 2014-01-20 镀金金银钯合金单晶键合丝及其制造方法

Publications (1)

Publication Number Publication Date
CN103779309A true CN103779309A (zh) 2014-05-07

Family

ID=50571404

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410024437.9A Pending CN103779309A (zh) 2014-01-20 2014-01-20 镀金金银钯合金单晶键合丝及其制造方法

Country Status (1)

Country Link
CN (1) CN103779309A (zh)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103996668A (zh) * 2014-05-30 2014-08-20 江西蓝微电子科技有限公司 银镧钙合金键合丝及其制造方法
CN104022094A (zh) * 2014-05-30 2014-09-03 江西蓝微电子科技有限公司 银铕合金键合丝及其制造方法
CN104593634A (zh) * 2014-12-31 2015-05-06 北京达博有色金属焊料有限责任公司 一种化学镀金钯键合银合金丝及其制备方法
CN105428335A (zh) * 2015-12-09 2016-03-23 北京达博有色金属焊料有限责任公司 一种键合丝
CN107946271A (zh) * 2017-11-14 2018-04-20 汕头市骏码凯撒有限公司 一种半导体封装用银合金线及其制造方法
CN110648989A (zh) * 2019-10-11 2020-01-03 重庆新启派电子科技有限公司 一种芯片植球用键合丝

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102154574A (zh) * 2010-10-18 2011-08-17 东莞市正奇电子有限公司 半导体组件连接用合金线
CN102437136A (zh) * 2011-11-16 2012-05-02 浙江佳博科技股份有限公司 一种键合合金丝及其生产工艺
JP2012169374A (ja) * 2011-02-10 2012-09-06 Tanaka Electronics Ind Co Ltd Ａｇ−Ａｕ−Ｐｄ三元合金系ボンディングワイヤ
CN103199073A (zh) * 2013-03-14 2013-07-10 江西蓝微电子科技有限公司 银钯合金单晶键合丝及其制造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102154574A (zh) * 2010-10-18 2011-08-17 东莞市正奇电子有限公司 半导体组件连接用合金线
JP2012169374A (ja) * 2011-02-10 2012-09-06 Tanaka Electronics Ind Co Ltd Ａｇ−Ａｕ−Ｐｄ三元合金系ボンディングワイヤ
CN103155130A (zh) * 2011-02-10 2013-06-12 田中电子工业株式会社 Ag-Au-Pd三元合金接合线
CN102437136A (zh) * 2011-11-16 2012-05-02 浙江佳博科技股份有限公司 一种键合合金丝及其生产工艺
CN103199073A (zh) * 2013-03-14 2013-07-10 江西蓝微电子科技有限公司 银钯合金单晶键合丝及其制造方法

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103996668A (zh) * 2014-05-30 2014-08-20 江西蓝微电子科技有限公司 银镧钙合金键合丝及其制造方法
CN104022094A (zh) * 2014-05-30 2014-09-03 江西蓝微电子科技有限公司 银铕合金键合丝及其制造方法
CN104593634A (zh) * 2014-12-31 2015-05-06 北京达博有色金属焊料有限责任公司 一种化学镀金钯键合银合金丝及其制备方法
CN105428335A (zh) * 2015-12-09 2016-03-23 北京达博有色金属焊料有限责任公司 一种键合丝
CN105428335B (zh) * 2015-12-09 2017-12-26 北京达博有色金属焊料有限责任公司 一种键合丝
CN107946271A (zh) * 2017-11-14 2018-04-20 汕头市骏码凯撒有限公司 一种半导体封装用银合金线及其制造方法
CN107946271B (zh) * 2017-11-14 2020-01-21 汕头市骏码凯撒有限公司 一种半导体封装用银合金线及其制造方法
CN110648989A (zh) * 2019-10-11 2020-01-03 重庆新启派电子科技有限公司 一种芯片植球用键合丝

Similar Documents

Publication Publication Date Title
CN103779308A (zh) 金银钯合金单晶键合丝及其制造方法
CN103779309A (zh) 镀金金银钯合金单晶键合丝及其制造方法
CN103199073B (zh) 银钯合金单晶键合丝及其制造方法
CN103194637B (zh) 一种键合合金银丝及制备方法
CN101707194B (zh) 一种镀钯键合铜丝的制造方法
CN106992164B (zh) 一种微电子封装用铜合金单晶键合丝及其制备方法
CN104388861B (zh) 一种多晶串联led用微细银金合金键合线的制造方法
CN100421246C (zh) 键合铜丝及其制备方法
CN103474408B (zh) 一种表面有镀金层的金银合金键合丝及其制备方法
CN104377185A (zh) 镀金银钯合金单晶键合丝及其制造方法
CN102776408A (zh) 一种银合金丝及其制备方法
CN102121077B (zh) 一种键合金丝的制备方法
CN106011516B (zh) 一种掺杂金合金键合丝及其深冷处理制备方法
CN101667566A (zh) 一种银基覆金的键合丝线及其制造方法
CN104835797B (zh) 一种铜钯银合金键合引线及其制备方法
CN102226991A (zh) 铜钯合金单晶键合丝及其制造方法
CN109767991B (zh) 一种高金合金键合丝的制备方法
CN107799496A (zh) 一种电子封装用高可靠性铜合金键合丝及其制备方法
CN104372197A (zh) 半导体封装用银合金线及其制备方法
CN109449133A (zh) 一种铜镀纯镍键合丝及其制备方法
CN102361026A (zh) 一种具有防氧化功能的铜基键合丝
CN103219246A (zh) 一种镀钯镀银的双镀层键合铜丝的制造方法
CN103996668A (zh) 银镧钙合金键合丝及其制造方法
CN104022095A (zh) 镀金银镧钙合金键合丝及其制造方法
CN103199072A (zh) 镀金铜钯合金单晶键合丝及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20140507

RJ01 Rejection of invention patent application after publication