CN106206557A - 硅中介层 - Google Patents

硅中介层 Download PDF

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CN106206557A
CN106206557A CN201510413740.2A CN201510413740A CN106206557A CN 106206557 A CN106206557 A CN 106206557A CN 201510413740 A CN201510413740 A CN 201510413740A CN 106206557 A CN106206557 A CN 106206557A
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chip
layer
silicon
intermediary layer
cutting road
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CN106206557B (zh
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管式凡
施能泰
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Micron Technology Inc
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Inotera Memories Inc
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Abstract

本发明公开了一种硅中介层，包含一硅基板，具有一正面及相对于正面的一背面；一第一集成电路芯片，设置在硅基板的正面；一第二集成电路芯片，设置在硅基板的正面且靠近第一集成电路芯片；一虚设切割道区域，设置在第一集成电路芯片与第二集成电路芯片之间；以及至少一电路器件，设置在硅基板正面的虚设切割道区域中。

Description

硅中介层
技术领域
本发明涉及一半导体器件，特别是涉及一种硅中介层，在其芯片之间的切割道内具有电路器件。
背景技术
在半导体技术领域中，集成电路通常通过封装工艺，变成一封装体后，再安装在印刷电路板或电脑***主机板上。集成电路可以被安装至一基板或一中介层上，然后再以塑胶材料或环氧树酯材料包覆封装。
上述封装过程可以采用本领域技术人员所熟知的覆晶技术，将集成电路的输入/输出(input/output,I/O)面(或有源面)朝下，安装至所述基板或中介层的安装面上。
目前，中介层的主要功用是将具相对较小垫距(pad pitch)的集成电路芯片的接触垫扇出(fan out)以匹配印刷电路板上具较大垫距的接触垫。如能更进一步利用中介层，使其不仅具扇出集成电路信号的功用，实为所述领域所期望。
发明内容
根据本发明提供的硅中介层，包含一硅基板，具有一正面及相对于正面的一背面；一第一集成电路芯片，设置在硅基板的正面；一第二集成电路芯片，设置在硅基板的正面且与第一集成电路芯片紧密靠近；一虚设切割道区域，设置在第一集成电路芯片与第二集成电路芯片之间；以及至少一电路器件，设置在硅基板正面的虚设切割道区域中。
根据本发明一实施例，一位于硅基板正面的重布线层，覆盖住第一集成电路芯片、第二集成电路芯片与虚设切割道区域。在硅基板内部形成的通过硅片通道，与重布线层电性连接。
毋庸置疑的，本领域的技术人员读完接下来本发明优选实施例的详细描述与附图后，均可了解本发明的目的。
附图说明
图1至图6为剖视示意图，说明根据本发明一实施例，制作一具有通过硅片通道(TSV)的硅中介层与半导体芯片的封装体的方法。
图7为晶圆俯视图，示意性说明本发明一实施例的2x2芯片阵列与第一和第二切割道区域。
其中，附图标记说明如下：
10 芯片
100 晶圆(中介层晶圆)
100a 正面
100b 背面
11 多芯片中介层
110 重布线层
112 介电层
114 金属绕线
116 凸块垫
12 电路器件
120 微凸块
130 模塑料
140 通过硅片通道
20 半导体晶粒
200 切割道
201 第一切割道区域
202 第二切割道区域
310 焊接凸块
具体实施方式
接下来的详细叙述须参附图所示内容，用来说明可依据本发明具体实行的实施例。这些实施例提供足够的细节，可使此领域中的技术人员充分了解并具体实行本发明。在不悖离本发明的范围内，可做结构、逻辑和电性上的修改应用在其他实施例上。
因此，接下来的详细叙述并非用来对本发明加以限制。本发明涵盖的范围由其权利要求所定义。与其权利要求具同等意义者也应属本发明涵盖的范围。
本发实施例所参照的附图为示意图，并未按比例绘制，且相同或类似的特征通常以相同的附图标记描述。
在本说明书中，“晶粒”、“半导体芯片”与“半导体晶粒”具相同含意，可交换使用。在本说明书中，“晶圆”与“基板”意指任何具一暴露面，可在其上沉积材料并制作例如本发明实施例所示的集成电路的结构物。需了解的是“基板”通常包含半导体晶圆。
工艺中所称的“晶圆”与“基板”，可为包含制作于其上的材料层的半导体结构物。“晶圆”与“基板”两者都包含已掺杂或未掺杂的半导体、具有衬底或绝缘体支撑的外延半导体层，以及其他本领域技术人员所熟知的半导体结构。
请参照图1至图6，为根据本发明一实施例，制作一具有通过硅片通道(TSV)的硅中介层与半导体芯片的封装体的方法。
首先，如图1所示，提供一晶圆(中介层晶圆)100，例如半导体晶圆或硅晶圆。晶圆100包含一正面100a与一相对于正面100a的背面100b。根据本发明实施例，在晶圆100的正面100a上具有多个芯片(或晶粒)10。
根据本发明实施例，每个芯片10内的集成电路，可包含存储器阵列、周边电路、逻辑电路，但并不限于此。根据本发明实施例，芯片10可为一存储器芯片，但并不限于此。
为了简化说明，在此不详述制作芯片10的集成电路的工艺步骤。一般而言，这些工艺步骤包含公知的技术，例如光刻工艺、蚀刻工艺、布植工艺、热处理、抛光工艺、薄膜沉积工艺，以及其他类似工艺。
根据本发明实施例，芯片10之间具有切割道200，将芯片10互相分隔开。根据本发明实施例，切割道200包含一第一切割道区域201与一第二切割道区域202。
根据本发明实施例，仅沿着第一切割道区域201切割晶圆100，可得到包含多个芯片10的多芯片中介层11。例如，如图7所示，沿着第一切割道区域201切割晶圆100，可得到一具有2x2芯片阵列的多芯片中介层11。须了解的是多芯片中介层11中的2x2芯片阵列仅为说明目的，其他芯片的矩阵排列，例如3x1芯片阵列、3x2芯片阵列或2x1芯片阵列也包含在本发明的范围。第二切割道区域202也可被称为“虚设切割道区域”。
同样参照图1，根据本发明实施例，第二切割道区域202内包含电路器件12。第二切割道区域202内的电路器件12是以上述公知的半导体工艺技术，与芯片10中的集成电路同时制作于晶圆100上。电路器件12包含有源电路器件，例如金氧半导体器件或晶体管、被动电路器件，例如电容、电阻、电感，或其他电路器件，例如熔丝电路或静电放电(ESD)保护器件。
根据本发明实施例，在晶圆100的正面100a上提供一重布线层(RDL)110。重布线层110包含至少一介电层112、金属绕线114，与提供后续连接使用的凸块垫116。须了解的是图1中，重布线层110的结构仅为说明目的，在其他实施例中，重布线层110可为多迭层结构，以符合不同电路设计的需求。
如图2所示，接着在重布线层110上形成微凸块120，选择性地将半导体晶粒20安装到重布线层110上方。根据本发明实施例，半导体晶粒20通过微凸块120与重布线层110电性连接。须了解的是图2中，半导体晶粒20的数量仅为说明目的。在一些实施例中，可不包含半导体晶粒20。
如图3所示，接着在晶圆100的正面100a上形成一模塑料130。模塑料130包覆住安装在重布线层110上方的晶粒20与重布线层110的上表面。最佳者，模塑料130完全填满晶粒20之间的空隙。接着，可继续进行一模塑料130的固化工艺。
根据本发明实施例，通过转移压模机，可将热固性模塑料成型到晶圆100上，或采用其他模塑料的形成方法。模塑料可为环氧化物、树脂，或者其他室温或高温下为液态的化合物。模塑料130是电绝缘体，但可为热导体，可在其中添加不同种类的填充剂，改善模塑料130的导热性、刚性或黏着性质。
如图4所示，模塑料130形成之后，接着对晶圆100进行一抛光工艺，自背面100b抛光移除掉部分晶圆100。例如，先将晶圆100载入至一晶圆抛光机，然后一抛光头与晶圆100的背面100b接触，并开始抛光。晶圆100在经过抛光工艺后，具有较薄的厚度。
如图5所示，接着在晶圆100中形成与重布线层110电性连接的通过硅片通道(TSV)140。例如，自晶圆100的背面100b，刻蚀选定的连接点的晶圆100，形成一TSV孔洞。接着，在TSV孔洞中沉积一扩散阻挡层与金属导电层。通过在背面100b施加一晶背抛光或化学机械抛光工艺，移除TSV孔洞外多余的金属导电层。
如图6所示，在晶圆100的背面100b上形成焊接凸块310或其他焊接物，与各个通过硅片通道140电性连接。接着，如图7所示，沿着第一切割道201切割晶圆100，得到多芯片中介层11。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (9)

1.一种硅中介层,其特征在于,包含有:
一硅基板，具有一正面及与所述正面相对的一背面；
一第一集成电路芯片，位于所述硅基板的所述正面；
一第二集成电路芯片，位于所述硅基板的所述正面且靠近所述第一集成电路芯片；
一虚设切割道区域，位于所述第一集成电路芯片与所述第二集成电路芯片之间；以及
至少一电路器件，位于所述硅基板的所述正面上且位于所述虚设切割道区域中。
2.根据权利要求1所述的硅中介层，其特征在于,所述虚设切割道区域将所述第一集成电路芯片与所述第二集成电路芯片分隔开。
3.根据权利要求1所述的硅中介层，其特征在于,所述电路器件包含金氧半导体、晶体管、电容、电阻、电感、熔丝电路，或静电放电保护器件。
4.根据权利要求1所述的硅中介层，其特征在于,包含一重布线层位于所述正面，其中所述重布线层覆盖住所述第一集成电路芯片、所述第二集成电路芯片与所述虚设切割道区域。
5.根据权利要求4所述的硅中介层，其特征在于,所述重布线层包含至少一介电层、金属绕线，与提供后续连接使用的凸块垫。
6.根据权利要求4所述的硅中介层，其特征在于,还包含位于所述硅基板中的直通硅穿孔，与所述重布线层电性连接。
7.根据权利要求4所述的硅中介层，其特征在于,还包含至少一半导体晶粒安装在所述重布线层上。
8.根据权利要求7所述的硅中介层，其特征在于,所述半导体晶粒通过微凸块与所述重布线层电性连接。
9.根据权利要求7所述的硅中介层，其特征在于,还包含一模塑料位于所述正面，其中所述模塑料包覆住所述半导体晶粒与所述重布线层的上表面。
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