CN106548948A - 集成多输出封装件及制造方法 - Google Patents

集成多输出封装件及制造方法 Download PDF

Info

Publication number
CN106548948A
CN106548948A CN201610784041.3A CN201610784041A CN106548948A CN 106548948 A CN106548948 A CN 106548948A CN 201610784041 A CN201610784041 A CN 201610784041A CN 106548948 A CN106548948 A CN 106548948A
Authority
CN
China
Prior art keywords
pipe core
component pipe
run
channel
core
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201610784041.3A
Other languages
English (en)
Other versions
CN106548948B (zh
Inventor
余振华
余国宠
蔡豪益
郭庭豪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN106548948A publication Critical patent/CN106548948A/zh
Application granted granted Critical
Publication of CN106548948B publication Critical patent/CN106548948B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16265—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/214—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/24147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the HDI interconnect not connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted, e.g. the upper semiconductor or solid-state body being mounted in a cavity or on a protrusion of the lower semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73217—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H01L23/295—Organic, e.g. plastic containing a filler
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

本发明的实施例提供了一种方法，包括从第一器件管芯的第一导电焊盘形成贯通道。第一导电焊盘位于第一器件管芯的顶面处。将第二器件管芯附着至第一器件管芯的顶面。第二器件管芯具有表面导电部件。将第二器件管芯和贯通道包封在包封材料中。平坦化包封材料以露出贯通道和表面导电部件。再分布线形成在贯通道和表面导电部件上方并且电耦合至贯通道和表面导电部件。本发明的实施例还提供了集成多输出封装件及制造方法。

Description

集成多输出封装件及制造方法
技术领域
本发明的实施例涉及半导体领域，更具体地涉及集成多输出封装件及制造方法。
背景技术
堆叠管芯通常用于三维(3D)集成电路中。通过管芯的堆叠，减小了封装件的占用空间(footprint)(形状因子)。另外，通过堆叠管芯的形成显著简化了管芯中的金属线布线。
在一些应用中，堆叠多个管芯以形成管芯堆叠件，其中，多个管芯包括衬底导电贯通道(TSV，有时称为硅贯通道)。有时，堆叠管芯的总数可以达到八个或更多。当形成这种管芯堆叠件时，通过倒装芯片接合将第一管芯首先接合至封装衬底上，其中，回流焊料区/球以将第一管芯结合至封装衬底。第一底部填充物分配在第一管芯与封装衬底之间的间隙中。然后固化第一底部填充物。然后执行测试以确保第一管芯适当地连接至封装衬底，并且第一管芯和封装衬底按照期望的方式运行。
接下来，通过倒装芯片接合将第二管芯接合至第一管芯上，其中，回流焊料区/球以将第二管芯结合至第一管芯。第二底部填充物分配在第二管芯与第一管芯之间的间隙中。然后固化第二底部填充物。然后执行测试以确保第二管芯正确地连接至第一管芯，并且第一管芯、第二管芯和封装衬底按照期望的方式运行。接下来，通过与用于结合第一管芯和第二管芯相同的工艺步骤将第三管芯接合至第二管芯上。重复该工艺直到接合所有的管芯。
发明内容
本发明的实施例提供了一种制造集成多输出封装件的方法，包括：从第一器件管芯的第一导电焊盘形成贯通道，其中，所述第一导电焊盘位于所述第一器件管芯的顶面处；将第二器件管芯附着至所述第一器件管芯的顶面，其中，所述第二器件管芯包括表面导电部件；将所述第二器件管芯和所述贯通道包封在包封材料中；平坦化所述包封材料以露出所述贯通道和所述表面导电部件；以及形成位于所述贯通道和所述表面导电部件上方并且电耦合至所述贯通道和所述表面导电部件的再分布线。
本发明的实施例还提供了一种制造集成多输出封装件的方法，包括：在第一器件管芯的第一导电焊盘上形成第一贯通道；在第二器件管芯的第二导电焊盘上形成第二贯通道；将所述第一器件管芯和所述第二器件管芯放置在载体上方；将第三器件管芯附着至所述第一器件管芯的顶面和所述第二器件管芯的顶面；将所述第三器件管芯、所述第一贯通道和所述第二贯通道包封在包封材料中；平坦化所述包封材料以露出所述第一贯通道、所述第二贯通道、以及所述第三器件管芯的表面部件；以及形成位于所述第一贯通道、所述第二贯通道和所述第三器件管芯上方并且电耦合至所述第一贯通道、所述第二贯通道和所述第三器件管芯的再分布线。
本发明的实施例还提供了一种制造集成多输出封装件的方法，包括：在第一器件管芯的顶面上形成第一贯通道；在第二器件管芯的顶面上形成第二贯通道；将所述第一器件管芯和所述第二器件管芯放置在载体上方；将第三器件管芯附着至所述第一器件管芯的顶面和所述第二器件管芯的顶面，其中，所述第三器件管芯位于所述第一贯通道和所述第二贯通道之间，并且所述第一器件管芯的正面和所述第二器件管芯的正面面向所述第三器件管芯的背面；在相同的包封工艺中，将所述第一器件管芯、所述第二器件管芯、所述第三器件管芯、所述第一贯通道和所述第二贯通道包封在包封材料中；平坦化所述包封材料以露出所述第一贯通道、所述第二贯通道、以及所述第三器件管芯的表面导电部件；以及形成位于所述第一贯通道、所述第二贯通道和所述第三器件管芯的表面导电部件上方并且电耦合至所述第一贯通道、所述第二贯通道和所述第三器件管芯的表面导电部件的再分布线。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以最佳地理解本发明的各个实施例。应该注意，根据工业中的标准实践，各种部件没有被按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增加或减少。
图1A至图1I示出了根据一些实施例的在多输出(fan-out)封装件的形成中的中间阶段的截面图。
图2A至图2I示出了根据一些实施例的在多输出封装件的形成中的中间阶段的截面图。
图3A至图3J示出了根据一些实施例的在多输出封装件的形成中的中间阶段的截面图。
图4A至图4J示出了根据一些实施例的在多输出封装件的形成中的中间阶段的截面图。
图5至图10示出了根据一些实施例的多输出封装件的截面图。
图11示出了根据一些实施例的多输出封装件的顶视图。
图12示出了根据一些实施例的用于形成多输出封装件的工艺流程图。
具体实施方式
以下公开内容提供了多种不同实施例或实例，以实现本发明的不同特征。以下将描述组件和布置的具体实例以简化本发明。当然，这些仅是实例并且不意欲限制本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例，也可以包括形成在第一部件和第二部件之间的附加部件使得第一部件和第二部件不直接接触的实施例。而且，本发明在各个实例中可以重复参考数字和/或字母。这种重复仅是为了简明和清楚，其自身并不表示所论述的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在...下面”、“在...下方”、“下部”、“在...上面”、“上部”等的空间相对术语，以便于描述如图所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外，空间关系术语旨在包括器件在使用或操作过程中的不同方位。装置可以以其他方式定位(旋转90度或在其他方位)，并且在本文中使用的空间关系描述符可以同样地作相应地解释。
根据各个示例性实施例，提供了集成多输出封装件及其形成方法。示出了形成多输出封装件的中间阶段。讨论了一些实施例的一些变化。贯穿各个视图和示例性实施例，类似的参考标号用于指定类似的元件。
图1A至图1I示出了根据一些实施例的在多输出(fan-out)封装件的形成中的中间阶段的截面图。图1A至图1I中所示的步骤还示例性地示出了图12所示的工艺流程200。在随后的讨论过程中，参照图12的工艺步骤讨论了图1A至图1I所示的工艺步骤。
参考图1A，提供器件10(其为具有多个器件管芯的相应的晶圆2的一部分)。根据本发明的一些实施例，器件管芯10为逻辑管芯，该管芯可以是中央处理单元(CPU)管芯、微控制单元(MCU)管芯、输入-输出(IO)管芯、基带(BB)管芯或应用处理器(AP)管芯。尽管未示出，但是器件管芯10可以包括半导体衬底，其中，诸如晶体管和/或二极管的有源器件形成在半导体衬底的顶面处。此外，金属线和通道(未示出)形成在器件管芯10的互连结构(未示出)中以互连器件管芯10中的集成电路器件，该互连结构位于半导体衬底上方。
金属焊盘12形成在器件管芯10的顶面10A处。器件管芯10的顶面10A还称为正面。器件管芯10具有背面10B，该背面还可以是器件管芯10中的相应的半导体衬底的背面。金属焊盘12可以是铝焊盘、铜焊盘、铝铜焊盘等。金属焊盘12可以形成在器件管芯10的第一表面区中，并且器件管芯10的第二表面区不具有形成在其中的金属焊盘。例如，根据图1A中示出的一些示例性实施例，右侧表面区中具有金属焊盘12，而左侧表面区不具有金属焊盘。
图1B和图1C示出了贯通道(through-via)14的形成。在图12中所示的工艺步骤中将相应的步骤示出为步骤202。根据一些实施例，如图1B所示，光刻胶16形成在晶圆2上方，然后图案化该光刻胶以形成开口15，通过该开口暴露每一个金属焊盘12的一部分。然后在开口15中镀敷贯通道14。然后去除光刻胶16，从而获得图1C中的结构。根据本发明的一些实施例，在镀敷之前未在晶圆2上形成晶种层。根据可选的实施例，在形成光刻胶16之前形成晶种层(未示出)，并且贯通道14镀敷在晶种层上。在去除光刻胶16之后，在蚀刻工艺中去除晶种层的未直接位于贯通道14下面的部分。因此，晶种层的剩余部分成为贯通道14的底部部分。
接下来，参考图1D，通过管芯附接膜(DAF)22将器件管芯20附着至器件管芯10。在图12中所示的工艺步骤中将相应的步骤示出为步骤204。器件管芯20的背面附着至器件10的正面10A，并且因此，对应的管芯堆叠为正反(face-to-back)堆叠。根据本发明的一些实施例，器件管芯20为存储器管芯，该管芯可以是与非(NAND)管芯、静态随机存取存储器(SRAM)管芯、低IO双倍数据率(DDR)管芯等。尽管未示出，但是器件管芯20可以是单个存储器管芯或堆叠的存储器管芯。并且器件管芯20还可以包括半导体衬底，其中，诸如晶体管和/或二极管的有源器件形成在半导体衬底的顶面处。此外，金属线和通道(未示出)形成在器件管芯20的互连结构中以互连器件管芯20中的集成电路器件。器件管芯20的背面还可以是器件管芯20中的半导体衬底的背面。
图11示出了器件管芯10的示例性顶视图以及对应的上面的器件管芯20和贯通道14。根据一些示例性实施例，器件管芯20与器件管芯10的角部区重叠，贯通道14邻近器件管芯20的两个侧壁。根据可选的实施例，器件管芯20与器件管芯10的中心区重叠，贯通道14环绕器件管芯20。还可以使用其他的布局方案来布局器件管芯20和贯通道14。
DAF 22是粘合膜，并且可以由聚合物形成。根据本发明的一些实施例，DAF 22具有低热导率，其可以低于约0.5W/m*K。
再次参考图1D，器件管芯20包括导电柱28，其可以是金属柱并且形成在表面介电层26中。金属柱28可以由铜、镍、钯、金、它们的多层和/或它们的合金形成。表面介电层26可以由聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等形成。金属焊盘24可以位于金属柱28下面，该金属焊盘可以由铜、铝或其他金属形成。
参考图1E，包封(encapsulating)材料30包封在器件管芯20和贯通道14上。在图12中所示的工艺步骤中将相应的步骤示出为步骤206。作为流体分配包封材料30，然后例如，在热固化工艺中压缩并且固化该包封材料。包封材料30填充器件管芯12与贯通道14之间的间隙。包封材料30可以包括模塑料、模制底部填充物、环氧树脂或树脂。在包封工艺之后，包封材料30的顶面高于金属柱28和贯通道14的顶端。
接下来，执行诸如机械研磨、化学机械抛光(CMP)和/或两者的组合的平坦化步骤，以平坦化包封材料30、贯通道14、表面介电层26和金属柱28。在图12中所示的工艺步骤中也将相应的步骤示出为步骤206。图1E中还示出了所得到的结构。由于平坦化，贯通道14的顶面与金属柱28的顶面齐平(共面)，并且与包封材料30的顶面齐平(共面)。
参考图1F，在包封材料30、贯通道14和金属柱28上方形成一个或多个介电层32和相应的再分布线(RDL)34。在图12中所示的工艺步骤中将相应的步骤示出为步骤208。根据本发明的一些实施例，介电层32由诸如PBO、聚酰亚胺、BCB等的聚合物形成。
RDL 34形成为电耦合至金属柱28和贯通道14。应该注意，所有附图中的RDL 34都是示意性的。例如，RDL 34实际上被图案化为通过相应的介电层彼此分离的多个分立部分。RDL 34的每一个分立部分都连接至相应的下面的金属柱28和/或贯通道14。RDL 34也可以将一些金属柱28互连至相应的贯通道14。RDL 34可以包括金属迹线(金属线)和通道，该通道位于金属迹线下面并且连接至金属迹线。根据本发明的一些实施例，通过镀敷工艺形成RDL 34，其中，每个RDL 34均包括晶种层(未示出)和位于晶种层上方的镀敷的金属材料。晶种层和镀敷的金属材料可以由相同材料或不同材料形成。
图1G示出了器件管芯10的背侧研磨，从该器件管芯的背侧(示出的底侧)研磨。在图12中所示的工艺步骤中将相应的步骤示出为步骤210。因此，器件管芯10的厚度从厚度T1(图1F)减小至图1G所示的厚度T2。
图1H示出了根据本发明的一些示例性实施例的电连接件36的形成。在图12中所示的工艺步骤中将相应的步骤示出为步骤212。电连接件36电耦合至RDL 34、金属柱28和/或贯通道14。电连接件36的形成可以包括将焊料球放置在RDL 34上方，并且然后回流焊料球。根据本发明的可选的实施例，电连接件36的形成包括执行镀敷步骤以在RDL 34上方形成焊料区然后回流焊料区。电连接件36还可以包括金属柱或者金属柱和焊料帽，其也可以通过镀敷来形成。
另外，集成无源器件(IPD)39可以接合至RDL 34。例如，IPD 39可以用于调整所得到的封装件的性能并且可以包括电容器。根据可选的实施例，未接合IPD 39。在整个说明书中，结合的结构包括器件管芯10和20、贯通道14、包封材料30、RDL 34、以及介电层32，该结合的结构被称为复合晶圆38，该复合晶圆是包括多个器件管芯10和20的复合晶圆。
在随后的步骤中，将复合晶圆38锯切成多个封装件40，每个封装件都包括一个器件管芯10、一个器件管芯20和对应的贯通道14。因此，根据一些实施例，利用单包封(模制)工艺形成封装件40，但是封装件40包括堆叠在一起的两层级器件管芯。这与传统的管芯堆叠工艺不同，其中，使用两个包封工艺来包封两层级器件管芯。另外，封装件40中未使用封装衬底。这导致封装件40的厚度的有利的减小，并且因此，封装件40适用于需要非常薄的封装件的移动应用。
根据一些实施例，鉴于器件管芯10的顶视图面积足以设置所有电连接件36，虽然由于RDL 34延伸越过器件管芯20的边缘而使得封装件40是多输出封装件，但是封装件40的占用空间(顶视图面积)与器件管芯10的顶视图面积相同。因此，封装件40的顶视图面积较小。另外，金属焊盘12与电连接件36之间的距离较小，从而改善所得到的封装件40的电性能。
此外，可以为逻辑管芯的器件管芯10通常比诸如器件管芯20的存储器件管芯生成更多的热量。存储器管芯遭受由热量导致的若干性能退化。根据本发明的实施例，具有低热导率的DAF 22用于减少器件管芯10中生成的热量传导至器件管芯20中。并且，器件管芯10中的热量可以通过贯通道14传导至电连接件36。贯通道14中的一些也可以设计为伪通道，该伪通道不用于器件管芯10与电连接件36之间的电连接。伪贯通道14可以是电浮置的并且用于将器件管芯10中的热量传导至电连接件36。
图2A至图4J示出了根据本发明的一些实施例的在多输出封装件的形成中的中间阶段的截面图。除非另有说明，否则这些实施例中的组件的材料和形成方法与图1A至图1I中示出的实施例中的由类似的参考标号表示的类似的组件基本上相同。因此，可以在图1A至图1H中所示的实施例的讨论中发现或实现关于图2A至图4J(以及图5至图10中的实施例)所示组件的形成工艺和材料的具体细节。
图2A和图2B中示出了一些实施例的初始步骤，该步骤与图1A至图1C中示出的工艺步骤本质上相同。贯通道14形成在器件管芯10的金属焊盘12上。接下来，将晶圆2锯切为单独的器件管芯10。
参考图2C，通过粘合膜44将器件管芯10附着至载体46。根据本发明的一些实施例，载体46是玻璃载体。尽管示出了一个器件管芯10，但是有多个器件管芯10放置在载体46上，并且器件管芯10可以布局为阵列。然后，如图2D所示，通过DAF 22将器件管芯20附着至器件管芯10的正面。在随后的步骤中，如图2E所示，分配包封材料30以包封器件管芯10和20。与图1E中示出的实施例不同，器件管芯10也被包封。由于在单个包封工艺中实现器件管芯10和20的包封，所以包封材料30的上部(用于包封器件管芯20)和底部(用于包封器件管芯10)之间没有可区分的界面。
在随后的步骤中，如图2F所示，介电层32和RDL 34形成在包封材料30上方，RDL 34电耦合至金属柱28和贯通道14。根据一些示例性实施例，RDL 34扩张越过器件管芯10和20两者的边缘。因此，图2F(与图1F相比)中示出的实施例可以用于其中器件管芯10的顶视图面积不足够大以容纳所有电连接件36(图2I)的实施例中，并且因此，RDL 34需要从器件管芯10进行多输出。
接下来，载体46从上面的结构脱离，从而得到图2G中示出的结构。然后可以执行背侧研磨以去除粘合膜44并且减薄器件管芯10，并且图2H中示出了所得到的结构。在图2I中，IPD 39可以(或可以不)接合至RDL34。将包括器件管芯10、器件管芯20、包封材料30、贯通道14、RDL 34和介电层32的所得到的复合晶圆38锯切为单独的封装件40。
图3A至图3J示出了根据一些实施例的多输出封装件40的形成。参考图3A，形成晶圆4，该晶圆中包括器件管芯20。导电焊盘(诸如金属焊盘)24形成在器件管芯20的正面20A处。器件管芯20具有背面20B，该背面还可以是其中的相应的半导体衬底(未示出)的背面。接下来，参考图3B，形成贯通道14，其中，形成工艺可以与图1B和图1C中示出的工艺类似。然后将晶圆4锯切为单独的器件管芯20。
参考图3C，选择器件管芯(包括20-1和20-2)并且放置在载体46和以及该载体上面的粘合膜44上。粘合层44可以由光热转换(LTHC)材料形成。另外，DAF 50可以用于将器件管芯20附着至粘合膜44。选择器件管芯20-1与20-2之间的距离，从而使得器件管芯20-1上方的贯通道14与器件管芯20-2上方的贯通道14之间的间隔足以容纳器件管芯10(图3D)。根据本发明的一些实施例，器件管芯20-1和20-2彼此相同，并且器件管芯20-1相对于器件管芯20-2旋转180°(在顶视图中)。根据可选的实施例，器件管芯20-1和20-2彼此部分相同，其中，诸如有源器件和互连结构(未示出)的下部(器件管芯20-1的)20-1-L与器件管芯20-2的下部20-2-L相同。然而，包括顶部再分布层(未示出)的上部20-1-U和20-2-U彼此不同，从而使得器件管芯20-1中的导电焊盘24集中在器件管芯20-1的左侧上，并且器件管芯20-2中的导电焊盘24集中在器件管芯20-2的右侧上。根据本发明的可选的实施例，器件管芯20-1和20-2是不同类型的管芯，并且具有不同的结构。根据本发明的可选的实施例，取决于设计需要，器件管芯20可以包括两个以上的管芯，诸如四个管芯，并且器件管芯10可以包括一个以上的管芯，诸如两个管芯，以用于多逻辑芯片和多存储器芯片的集成。
接下来，参考图3D，器件管芯10放置在器件管芯20上方，并且通过DAF 22附着至器件管芯20的正面上。器件管芯10的一部分还与器件管芯20之间的间隙重叠。根据一些实施例，器件管芯10包括金属焊盘12上方的金属柱52，并且没有介电层环绕金属柱52。根据可选的实施例，存在位于与金属柱52相同的平面处并且环绕该金属柱的介电层(未示出)。根据又一可选的实施例，没有金属柱形成在金属焊盘12上方，并且金属焊盘12是器件管芯10的顶部导电部件。
图3E示出了包封材料30中的器件管芯10和20以及贯通道14的包封，随后通过机械研磨、化学机械抛光(CMP)和/或两者的组合来暴露金属柱52和贯通道14。在随后的步骤中，如图3F所示，形成介电层32和RDL 34，并且RDL 34电耦合至金属柱52和贯通道14。接下来，器件管芯41可以接合至RDL 34(图3G)，并且形成电连接件36以连接至RDL 34(图3H)。器件管芯41可以包括穿过器件管芯41中的半导体衬底的贯通道(有时称为硅贯通道或衬底贯通道)。根据一些实施例，IPD也可以接合至RDL 34。
然后载体46从上面的结构脱离，并且图3I中示出所得到的结构。在随后的步骤中，从背侧研磨器件管芯20-1和20-2，并且通过研磨去除DAF50。图3J中示出所得到的结构。例如，图3J还示出了通过热界面材料(TIM)56使盖54附接至器件管芯20。TIM 56具有比DAF 22(图1I、图2I和图3J)的热导率高的热导率。例如，TIM 56的热导率可以高于约1W/m*K或甚至更高。盖54可以由具有良好热导率的材料形成。根据一些示例性实施例，盖54包括诸如铝、铜、铝/铜合金、不锈钢等的金属。
图4A至图4J示出了根据一些实施例的封装件40(图4J)的形成。这些实施例与图3A至图3J中示出的实施例本质上相同，除了器件管芯10不具有形成在金属焊盘12上方的金属柱52(图3J)。下文提供形成工艺的简要讨论。可以在图3A至图3J中的实施例中发现这些实施例的细节，并且本文不再重复。
图4A至图4C中示出的步骤与图3A至图3C中示出的步骤本质上相同。接下来，如图4D所示，器件管芯10附着至器件管芯20(包括20-1和20-2)。器件管芯10包括作为顶面导电部件的金属焊盘12，并且没有金属柱形成在金属焊盘12上方。器件10也放置在直接位于器件管芯20-1上方的贯通道14与直接位于器件管芯20-2上方的贯通道14之间。
图4E示出了包封材料30的直接形成，同时暴露金属焊盘12和贯通道14而没有平坦化。图4F至图4J中示出的工艺步骤与图3F至图3J中示出的工艺步骤本质上相同，并且本文不再重复该细节。
图5至图10示出了根据本发明的一些实施例形成的封装件。可以从图1A至图4J中的实施例来理解该形成工艺。图5中示出的封装件40与图1I中示出的封装件类似，除了在图5中未形成金属柱，并且金属焊盘24为管芯20的顶部导电部件。RDL 34包括与金属焊盘24物理接触的通道。
图6中示出的封装件40与图2I中示出的封装件类似，除了在图6中未形成金属柱，并且金属焊盘24为管芯20的顶部导电部件。RDL 34包括与金属焊盘24物理接触的通道。
图7示出了封装件40，该封装件与图2I中的封装件40类似，除了器件管芯20从器件管芯10部分地偏移。利用该部分的偏移，器件管芯20的第一部分与包封材料30的一部分重叠，而不与器件管芯10的任何部分重叠。器件管芯20的第二部分与器件管芯10的一部分重叠。因此，器件管芯20的第一部分悬浮，并且没有下面的器件管芯10的支撑。器件管芯20的相对于器件管芯10的部分的偏移有利地减少了器件管芯10和20的重叠面积。因此，器件管芯10的顶面面积的增加的百分比可以用于形成金属焊盘12和贯通道14，而不是与器件管芯20重叠。然而，根据一些实施例，器件管芯20从器件管芯10偏移未导致封装件40的形状因子(顶视图面积)的不期望的增加。例如，当通过满足所有的电连接件36所需要的面积来确定封装件40的顶视图面积时，只要器件管芯10和20的总占用面积未超出满足所有的电连接件36所需要的面积，器件管芯20从器件管芯10的部分的偏移就不会导致形状因子(顶视图面积)的增加。图8示出了与图7中示出的封装件类似的封装件40，除了未在金属焊盘24上方形成金属柱。
根据一些实施例，图9示出了封装件40，其中，有两个器件管芯10和从相应的器件管芯10部分地偏移的两个器件管芯20。每一个器件管芯10都具有与相应的下面的器件管芯20的一部分重叠的第一部分、以及从相应的下面的器件管芯20偏移的第二部分。贯通道14直接形成在每一个器件管芯20的金属焊盘24上。
根据一些实施例，图10示出了封装件40，其中，有四个器件管芯20(包括20-3和20-4)、以及一个器件管芯10。四个器件管芯20包括两个高层级器件管芯20-4、和位于该高层级器件管芯20-4下面的两个低层级器件管芯20-3。每一个高层级器件管芯20-4都具有与相应的下面的低层级器件管芯20-3的一部分重叠的第一部分、以及从相应的下面的低层级器件管芯20-3偏移的第二部分。在第一包封工艺中将四个器件管芯20包封在第一包封材料30A中。
器件管芯10位于高层级器件管芯20-4上方，并且在第二包封工艺中将该器件管芯包封在第二包封材料30B中。器件管芯10从两个高层级器件管芯20-4部分地偏移。例如，器件管芯10具有与高层级器件管芯20-4的一部分重叠的第一部分、以及与高层级器件管芯20-4之间的间隙重叠的第二部分。
包封材料30A和30B可以彼此相同或彼此不同。贯通道14A直接形成在低层级器件管芯20-3的金属焊盘24A上。贯通道14B中的一些直接形成在高层级器件管芯20-4的金属焊盘24B上。由于在包封材料30A的顶面上执行CMP，所以可以彼此区分包封材料30A和30B的界面，这使得包封材料30A中的球形填充物58中的一些被研磨为具有平坦的(而不是球形的)顶面。另一方面，位于包封材料30B中并且与包封材料30A接触的球形填充物60仍具有圆形形状。此外，由于贯通道14A和14B的形成工艺的性质，所以贯通道14A和14B中的每一个都可以具有比各自的底部宽度大的顶部宽度。从贯通道14B至相应的下面的贯通道14A的过渡也将显示为不连续的，并且贯通道14A的顶部宽度可以大于相应的上面的贯通道14B的底部宽度。
在图9和图10中，高层级管芯从低层级管芯的部分的偏移导致低层级管芯20-3的表面面积的有利的增加，并且该增加的面积可以用于形成金属焊盘和贯通道。另一方面，由于低层级管芯20-3占据封装件40的大部分顶视图面积，所以封装件40的翘曲不严重。
本发明的实施例具有一些有利部件。通过在低层级管芯的金属焊盘上直接形成贯通道，不使用封装衬底，并且所得到的封装件较薄。通过使用DAF的逻辑管芯和存储器管芯的热去耦防止由逻辑管芯中生成的热量导致的存储器管芯的性能退化。最小化封装件的顶视图面积。可以通过相同的包封工艺来包封高层级管芯和低层级管芯，并且因此，降低了封装件的成本并且减少了封装件的翘曲。
根据本发明的一些实施例，一种方法包括从第一器件管芯的第一导电焊盘形成贯通道。第一导电焊盘位于第一器件管芯的顶面处。将第二器件管芯附着至第一器件管芯的顶面。第二器件管芯具有表面导电部件。将第二器件管芯和贯通道包封在包封材料中。平坦化包封材料以露出贯通道和表面导电部件。再分布线形成在贯通道和表面导电部件上方并且电耦合至贯通道和表面导电部件。
根据本发明的一些实施例，一种方法包括在第一器件管芯的第一导电焊盘上形成第一贯通道、在第二器件管芯的第二导电焊盘上形成第二贯通道、将第一器件管芯和第二器件管芯放置在载体上方、以及将第三器件管芯附着至第一器件管芯的顶面和第二器件管芯的顶面。方法还包括：将第三器件管芯、第一贯通和第二贯通包封在包封材料中；平坦化包封材料以露出第一贯通道、第二贯通道和第三器件管芯的表面导电部件；以及形成位于第一贯通道、第二贯通道和第三器件管芯上方并且电耦合至第一贯通道、第二贯通道和第三器件管芯的再分布层。
根据本发明的一些实施例，一种方法包括在第一器件管芯的顶面上形成第一贯通道、在第二器件管芯的顶面上形成第二贯通道、将第一器件管芯和第二器件管芯放置在载体上方、以及将第三器件管芯附着至第一器件管芯的顶面和第二器件管芯的顶面。第三器件管芯位于第一贯通道和第二贯通道之间。第一器件管芯的正面和第二器件管芯的正面面向第三器件管芯的背面。方法还包括：在相同的包封工艺中，将第一器件管芯、第二器件管芯、第三器件管芯、第一贯通道、以及第二贯通道包封在包封材料中。平坦化包封材料以露出第一贯通道、第二贯通道、以及第三器件管芯的表面导电部件。再分布线形成在第一贯通道、第二贯通道和第三器件管芯的表面导电部件上方并且电耦合至第一贯通道、第二贯通道和第三器件管芯的表面导电部件。
本发明的实施例提供了一种制造集成多输出封装件的方法，包括：从第一器件管芯的第一导电焊盘形成贯通道，其中，所述第一导电焊盘位于所述第一器件管芯的顶面处；将第二器件管芯附着至所述第一器件管芯的顶面，其中，所述第二器件管芯包括表面导电部件；将所述第二器件管芯和所述贯通道包封在包封材料中；平坦化所述包封材料以露出所述贯通道和所述表面导电部件；以及形成位于所述贯通道和所述表面导电部件上方并且电耦合至所述贯通道和所述表面导电部件的再分布线。
根据本发明的一个实施例，其中，所述包封材料具有与所述第一器件管芯的相应的边缘对准的边缘。
根据本发明的一个实施例，其中，所述包封材料扩张越过所述第一器件管芯的相应的边缘，所述包封材料的底面与所述第一器件管芯的底面共面。
根据本发明的一个实施例，其中，所述第二器件管芯包括与所述第一器件管芯的一部分重叠的第一部分、以及与所述包封材料的一部分重叠的第二部分。
根据本发明的一个实施例，方法还包括与所述第一器件管芯共面的第三器件管芯，其中，所述第二器件管芯还包括与所述第三器件管芯的一部分重叠的第三部分。
根据本发明的一个实施例，其中，所述第一器件管芯包括第一下部和位于所述第一下部上方的第一上部，所述第一下部包括第一有源器件，并且所述第一上部包括第一布线层，其中，所述第二器件管芯包括第二下部和位于所述第二下部上方的第二上部，所述第二下部包括有源器件，并且所述第二上部包括第二布线层，其中，所述第一下部与所述第二下部相同，并且所述第一上部与所述第二上部不同。
根据本发明的一个实施例，其中，所述第一器件管芯包封在所述包封材料中，并且在相同的包封工艺中包封所述第一器件管芯和所述第二器件管芯。
根据本发明的一个实施例，其中，所述第二器件管芯的表面导电部件是金属柱。
根据本发明的一个实施例，其中，所述第二器件管芯的表面导电部件是金属焊盘。
本发明的实施例还提供了一种制造集成多输出封装件的方法，包括：在第一器件管芯的第一导电焊盘上形成第一贯通道；在第二器件管芯的第二导电焊盘上形成第二贯通道；将所述第一器件管芯和所述第二器件管芯放置在载体上方；将第三器件管芯附着至所述第一器件管芯的顶面和所述第二器件管芯的顶面；将所述第三器件管芯、所述第一贯通道和所述第二贯通道包封在包封材料中；平坦化所述包封材料以露出所述第一贯通道、所述第二贯通道、以及所述第三器件管芯的表面部件；以及形成位于所述第一贯通道、所述第二贯通道和所述第三器件管芯上方并且电耦合至所述第一贯通道、所述第二贯通道和所述第三器件管芯的再分布线。
根据本发明的一个实施例，其中，所述第一器件管芯和所述第二器件管芯通过间隙彼此分离，并且所述包封材料填充在所述间隙中。
根据本发明的一个实施例，其中，通过粘合膜将所述第三器件管芯附着至所述第一器件管芯的顶面和所述第二器件管芯的顶面。
根据本发明的一个实施例，其中，通过所述第一贯通道将所述第一器件管芯电耦合至所述第三器件管芯。
根据本发明的一个实施例，其中，在相同的包封工艺中包封所述第一器件管芯、所述第二器件管芯、所述第一贯通道和所述第二贯通道。
根据本发明的一个实施例，方法还包括位于所述第一器件管芯下面的第四器件管芯，并且其中，所述方法包括：在所述第四器件管芯的金属焊盘上形成第三贯通道；以及形成位于所述第三贯通道上方并且接触所述第三贯通道的第四贯通道，其中，所述第四贯通道具有与所述第一贯通道共面的顶面。
本发明的实施例还提供了一种制造集成多输出封装件的方法，包括：在第一器件管芯的顶面上形成第一贯通道；在第二器件管芯的顶面上形成第二贯通道；将所述第一器件管芯和所述第二器件管芯放置在载体上方；将第三器件管芯附着至所述第一器件管芯的顶面和所述第二器件管芯的顶面，其中，所述第三器件管芯位于所述第一贯通道和所述第二贯通道之间，并且所述第一器件管芯的正面和所述第二器件管芯的正面面向所述第三器件管芯的背面；在相同的包封工艺中，将所述第一器件管芯、所述第二器件管芯、所述第三器件管芯、所述第一贯通道和所述第二贯通道包封在包封材料中；平坦化所述包封材料以露出所述第一贯通道、所述第二贯通道、以及所述第三器件管芯的表面导电部件；以及形成位于所述第一贯通道、所述第二贯通道和所述第三器件管芯的表面导电部件上方并且电耦合至所述第一贯通道、所述第二贯通道和所述第三器件管芯的表面导电部件的再分布线。
根据本发明的一个实施例，其中，形成所述第一贯通道包括：在所述第一器件管芯上方形成光刻胶；图案化所述第一器件管芯以形成与所述第一器件管芯的导电焊盘的一部分对准的开口；在所述开口中镀敷导电材料；以及去除所述光刻胶。
根据本发明的一个实施例，方法还包括：将集成无源器件接合至所述再分布线。
根据本发明的一个实施例，其中，所述第三器件管芯包括：与所述第一器件管芯的一部分重叠的第一部分；与所述第二器件管芯的一部分重叠的第二部分；以及位于所述第一部分和所述第二部分之间的第三部分，其中，所述第三部分与所述包封材料的一部分重叠。
根据本发明的一个实施例，其中，所述第一贯通道直接形成在所述第一器件管芯中的金属焊盘的顶面上。
以上论述了若干实施例的部件，使得本领域的技术人员可以更好地理解本发明的各个实施例。本领域技术人员应该理解，可以很容易地使用本发明作为基础来设计或更改其他的处理和结构以用于达到与本发明所介绍实施例相同的目的和/或实现相同优点。本领域技术人员也应该意识到，这些等效结构并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (10)

1.一种制造集成多输出封装件的方法，包括：
从第一器件管芯的第一导电焊盘形成贯通道，其中，所述第一导电焊盘位于所述第一器件管芯的顶面处；
将第二器件管芯附着至所述第一器件管芯的顶面，其中，所述第二器件管芯包括表面导电部件；
将所述第二器件管芯和所述贯通道包封在包封材料中；
平坦化所述包封材料以露出所述贯通道和所述表面导电部件；以及
形成位于所述贯通道和所述表面导电部件上方并且电耦合至所述贯通道和所述表面导电部件的再分布线。
2.根据权利要求1所述的方法，其中，所述包封材料具有与所述第一器件管芯的相应的边缘对准的边缘。
3.根据权利要求1所述的方法，其中，所述包封材料扩张越过所述第一器件管芯的相应的边缘，所述包封材料的底面与所述第一器件管芯的底面共面。
4.根据权利要求1所述的方法，其中，所述第二器件管芯包括与所述第一器件管芯的一部分重叠的第一部分、以及与所述包封材料的一部分重叠的第二部分。
5.根据权利要求4所述的方法，还包括与所述第一器件管芯共面的第三器件管芯，其中，所述第二器件管芯还包括与所述第三器件管芯的一部分重叠的第三部分。
6.根据权利要求5所述的方法，其中，所述第一器件管芯包括第一下部和位于所述第一下部上方的第一上部，所述第一下部包括第一有源器件，并且所述第一上部包括第一布线层，其中，所述第二器件管芯包括第二下部和位于所述第二下部上方的第二上部，所述第二下部包括有源器件，并且所述第二上部包括第二布线层，其中，所述第一下部与所述第二下部相同，并且所述第一上部与所述第二上部不同。
7.根据权利要求4所述的方法，其中，所述第一器件管芯包封在所述包封材料中，并且在相同的包封工艺中包封所述第一器件管芯和所述第二器件管芯。
8.根据权利要求1所述的方法，其中，所述第二器件管芯的表面导电部件是金属柱。
9.一种制造集成多输出封装件的方法，包括：
在第一器件管芯的第一导电焊盘上形成第一贯通道；
在第二器件管芯的第二导电焊盘上形成第二贯通道；
将所述第一器件管芯和所述第二器件管芯放置在载体上方；
将第三器件管芯附着至所述第一器件管芯的顶面和所述第二器件管芯的顶面；
将所述第三器件管芯、所述第一贯通道和所述第二贯通道包封在包封材料中；
平坦化所述包封材料以露出所述第一贯通道、所述第二贯通道、以及所述第三器件管芯的表面部件；以及
形成位于所述第一贯通道、所述第二贯通道和所述第三器件管芯上方并且电耦合至所述第一贯通道、所述第二贯通道和所述第三器件管芯的再分布线。
10.一种制造集成多输出封装件的方法，包括：
在第一器件管芯的顶面上形成第一贯通道；
在第二器件管芯的顶面上形成第二贯通道；
将所述第一器件管芯和所述第二器件管芯放置在载体上方；
将第三器件管芯附着至所述第一器件管芯的顶面和所述第二器件管芯的顶面，其中，所述第三器件管芯位于所述第一贯通道和所述第二贯通道之间，并且所述第一器件管芯的正面和所述第二器件管芯的正面面向所述第三器件管芯的背面；
在相同的包封工艺中，将所述第一器件管芯、所述第二器件管芯、所述第三器件管芯、所述第一贯通道和所述第二贯通道包封在包封材料中；
平坦化所述包封材料以露出所述第一贯通道、所述第二贯通道、以及所述第三器件管芯的表面导电部件；以及
形成位于所述第一贯通道、所述第二贯通道和所述第三器件管芯的表面导电部件上方并且电耦合至所述第一贯通道、所述第二贯通道和所述第三器件管芯的表面导电部件的再分布线。
CN201610784041.3A 2015-09-21 2016-08-31 集成多输出封装件及制造方法 Active CN106548948B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201562221443P 2015-09-21 2015-09-21
US62/221,443 2015-09-21
US15/004,240 US10049953B2 (en) 2015-09-21 2016-01-22 Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors
US15/004,240 2016-01-22

Publications (2)

Publication Number Publication Date
CN106548948A true CN106548948A (zh) 2017-03-29
CN106548948B CN106548948B (zh) 2020-01-14

Family

ID=58224745

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610784041.3A Active CN106548948B (zh) 2015-09-21 2016-08-31 集成多输出封装件及制造方法

Country Status (5)

Country Link
US (4) US10049953B2 (zh)
KR (1) KR101892801B1 (zh)
CN (1) CN106548948B (zh)
DE (1) DE102016101685B4 (zh)
TW (1) TWI616956B (zh)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107301981A (zh) * 2016-04-15 2017-10-27 台湾积体电路制造股份有限公司 集成的扇出型封装件以及制造方法
CN110692127A (zh) * 2017-06-09 2020-01-14 苹果公司 使用扇出内插器小芯片的高密度互连
CN112687670A (zh) * 2019-10-18 2021-04-20 台湾积体电路制造股份有限公司 集成电路结构及其形成方法
WO2021189942A1 (zh) * 2020-03-27 2021-09-30 矽磐微电子(重庆)有限公司 半导体封装方法及半导体封装结构
US11532594B2 (en) 2015-09-21 2022-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package and the methods of manufacturing
US11532529B2 (en) 2015-09-21 2022-12-20 Taiwan Semiconductor Manufacturing Company Ltd. Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104835808A (zh) * 2015-03-16 2015-08-12 苏州晶方半导体科技股份有限公司 芯片封装方法及芯片封装结构
WO2017049510A1 (en) * 2015-09-23 2017-03-30 Intel Corporation Substrates, assemblies, and techniques to enable multi-chip flip chip packages
US11469215B2 (en) * 2016-07-13 2022-10-11 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with molding layer and method for forming the same
US9825007B1 (en) 2016-07-13 2017-11-21 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with molding layer and method for forming the same
DE112016007295T5 (de) * 2016-10-01 2019-06-19 Intel Corporation Elektronisches bauelementgehäuse
US20180233484A1 (en) * 2017-02-14 2018-08-16 Nanya Technology Corporation Semiconductor structure and manufacturing method thereof
US10217720B2 (en) * 2017-06-15 2019-02-26 Invensas Corporation Multi-chip modules formed using wafer-level processing of a reconstitute wafer
US10872864B2 (en) * 2017-06-30 2020-12-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
DE102018108924A1 (de) 2017-06-30 2019-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Halbleiter-Package und Verfahren
US11430724B2 (en) 2017-12-30 2022-08-30 Intel Corporation Ultra-thin, hyper-density semiconductor packages
US10742217B2 (en) 2018-04-12 2020-08-11 Apple Inc. Systems and methods for implementing a scalable system
KR102173811B1 (ko) * 2018-05-16 2020-11-04 주식회사 네패스 패키지 유닛 및 멀티 스택 패키지
US11462419B2 (en) 2018-07-06 2022-10-04 Invensas Bonding Technologies, Inc. Microelectronic assemblies
US20200020634A1 (en) * 2018-07-16 2020-01-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package and method of manufacturing the same
KR102160035B1 (ko) * 2018-11-06 2020-09-25 삼성전자주식회사 반도체 패키지
US10867929B2 (en) 2018-12-05 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structures and methods of forming the same
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US11088079B2 (en) 2019-06-27 2021-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure having line connected via portions
US11205607B2 (en) * 2020-01-09 2021-12-21 Nanya Technology Corporation Semiconductor structure and method of manufacturing thereof
US11227814B2 (en) * 2020-03-16 2022-01-18 Nanya Technology Corporation Three-dimensional semiconductor package with partially overlapping chips and manufacturing method thereof
US11410932B2 (en) * 2020-03-30 2022-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacturing the same
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11424235B2 (en) 2020-07-09 2022-08-23 International Business Machines Corporation Interposer-less multi-chip module
EP4189741A1 (en) * 2020-08-17 2023-06-07 Huawei Technologies Co., Ltd. A method for manufacturing a die assembly
US11521907B2 (en) * 2020-10-14 2022-12-06 Infineon Technologies Ag Hybrid embedded package
US11908838B2 (en) * 2021-08-26 2024-02-20 Taiwan Semiconductor Manufacturing Company Limited Three-dimensional device structure including embedded integrated passive device and methods of making the same
US11973058B2 (en) 2021-11-25 2024-04-30 International Business Machines Corporation Multiple die assembly

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101452860A (zh) * 2007-12-07 2009-06-10 矽品精密工业股份有限公司 多芯片堆叠结构及其制法
TW201230266A (en) * 2010-11-26 2012-07-16 Cambridge Silicon Radio Ltd Multi-chip package
CN103296009A (zh) * 2012-02-22 2013-09-11 中国科学院微电子研究所 带有ebg的屏蔽结构、3d封装结构及其制备方法

Family Cites Families (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6610560B2 (en) 2001-05-11 2003-08-26 Siliconware Precision Industries Co., Ltd. Chip-on-chip based multi-chip module with molded underfill and method of fabricating the same
DE102004049356B4 (de) 2004-10-08 2006-06-29 Infineon Technologies Ag Halbleitermodul mit einem internen Halbleiterchipstapel und Verfahren zur Herstellung desselben
US20080164605A1 (en) * 2007-01-08 2008-07-10 United Microelectronics Corp. Multi-chip package
TWI327365B (en) 2007-01-19 2010-07-11 Chipmos Technologies Inc Zigzag-stacked chip package structure
US8759964B2 (en) 2007-07-17 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level package structure and fabrication methods
KR100910233B1 (ko) 2008-01-02 2009-07-31 주식회사 하이닉스반도체 적층 웨이퍼 레벨 패키지
US20100193930A1 (en) 2009-02-02 2010-08-05 Samsung Electronics Co., Ltd. Multi-chip semiconductor devices having conductive vias and methods of forming the same
KR20100134354A (ko) 2009-06-15 2010-12-23 삼성전자주식회사 반도체 패키지, 스택 모듈, 카드 및 전자 시스템
US8446017B2 (en) 2009-09-18 2013-05-21 Amkor Technology Korea, Inc. Stackable wafer level package and fabricating method thereof
US8138014B2 (en) * 2010-01-29 2012-03-20 Stats Chippac, Ltd. Method of forming thin profile WLCSP with vertical interconnect over package footprint
CN102859691B (zh) 2010-04-07 2015-06-10 株式会社岛津制作所 放射线检测器及其制造方法
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8361842B2 (en) 2010-07-30 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded wafer-level bonding approaches
US8354297B2 (en) 2010-09-03 2013-01-15 Stats Chippac, Ltd. Semiconductor device and method of forming different height conductive pillars to electrically interconnect stacked laterally offset semiconductor die
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8884431B2 (en) 2011-09-09 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures for semiconductor devices
US8273604B2 (en) * 2011-02-22 2012-09-25 STAT ChipPAC, Ltd. Semiconductor device and method of forming WLCSP structure using protruded MLP
US8829676B2 (en) 2011-06-28 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for wafer level package
US20130040423A1 (en) 2011-08-10 2013-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of Multi-Chip Wafer Level Packaging
TWI481001B (zh) * 2011-09-09 2015-04-11 Dawning Leading Technology Inc 晶片封裝結構及其製造方法
US9190391B2 (en) 2011-10-26 2015-11-17 Maxim Integrated Products, Inc. Three-dimensional chip-to-wafer integration
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US8680647B2 (en) 2011-12-29 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with passive devices and methods of forming the same
KR101346420B1 (ko) 2011-12-29 2014-01-10 주식회사 네패스 반도체 패키지 및 그 제조 방법
US8703542B2 (en) 2012-05-18 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level packaging mechanisms
US9991190B2 (en) 2012-05-18 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging with interposer frame
US9281292B2 (en) 2012-06-25 2016-03-08 Intel Corporation Single layer low cost wafer level packaging for SFF SiP
US8809996B2 (en) 2012-06-29 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package with passive devices and method of forming the same
US8872326B2 (en) * 2012-08-29 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. Three dimensional (3D) fan-out packaging mechanisms
US8975726B2 (en) * 2012-10-11 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. POP structures and methods of forming the same
US8785299B2 (en) 2012-11-30 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package with a fan-out structure and method of forming the same
US8803306B1 (en) 2013-01-18 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package structure and methods for forming the same
US8778738B1 (en) 2013-02-19 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging devices and methods
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US8877554B2 (en) 2013-03-15 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US9478485B2 (en) * 2013-06-28 2016-10-25 STATS ChipPAC Pte. Ltd. Semiconductor device and method of stacking semiconductor die on a fan-out WLCSP
CN103579171B (zh) 2013-10-11 2016-03-09 三星半导体(中国)研究开发有限公司 半导体封装件及其制造方法
US9373527B2 (en) * 2013-10-30 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US9379074B2 (en) * 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
KR102143653B1 (ko) 2013-12-31 2020-08-11 에스케이하이닉스 주식회사 전자기 간섭 차폐부를 갖는 반도체 패키지 및 제조방법
KR102247916B1 (ko) 2014-01-16 2021-05-04 삼성전자주식회사 계단식 적층 구조를 갖는 반도체 패키지
US9396300B2 (en) 2014-01-16 2016-07-19 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods for semiconductor devices, packaged semiconductor devices, and design methods thereof
US9196586B2 (en) 2014-02-13 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package including an embedded surface mount device and method of forming the same
US9601463B2 (en) * 2014-04-17 2017-03-21 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out stacked system in package (SIP) and the methods of making the same
US9666520B2 (en) 2014-04-30 2017-05-30 Taiwan Semiconductor Manufactuing Company, Ltd. 3D stacked-chip package
JP2015216263A (ja) * 2014-05-12 2015-12-03 マイクロン テクノロジー， インク． 半導体装置
US9496196B2 (en) * 2014-08-15 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packages and methods of manufacture thereof
KR101640076B1 (ko) * 2014-11-05 2016-07-15 앰코 테크놀로지 코리아 주식회사 웨이퍼 레벨의 칩 적층형 패키지 및 이의 제조 방법
US9799628B2 (en) 2015-03-31 2017-10-24 Qualcomm Incorporated Stacked package configurations and methods of making the same
US10049953B2 (en) * 2015-09-21 2018-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors
US9917072B2 (en) 2015-09-21 2018-03-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing an integrated stacked package with a fan-out redistribution layer (RDL) and a same encapsulating process

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101452860A (zh) * 2007-12-07 2009-06-10 矽品精密工业股份有限公司 多芯片堆叠结构及其制法
TW201230266A (en) * 2010-11-26 2012-07-16 Cambridge Silicon Radio Ltd Multi-chip package
CN103296009A (zh) * 2012-02-22 2013-09-11 中国科学院微电子研究所 带有ebg的屏蔽结构、3d封装结构及其制备方法

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11532594B2 (en) 2015-09-21 2022-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package and the methods of manufacturing
US11532529B2 (en) 2015-09-21 2022-12-20 Taiwan Semiconductor Manufacturing Company Ltd. Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors
US11538788B2 (en) 2015-09-21 2022-12-27 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out stacked package with fan-out redistribution layer (RDL)
CN107301981A (zh) * 2016-04-15 2017-10-27 台湾积体电路制造股份有限公司 集成的扇出型封装件以及制造方法
CN107301981B (zh) * 2016-04-15 2020-07-10 台湾积体电路制造股份有限公司 集成的扇出型封装件以及制造方法
CN110692127A (zh) * 2017-06-09 2020-01-14 苹果公司 使用扇出内插器小芯片的高密度互连
CN110692127B (zh) * 2017-06-09 2023-09-26 苹果公司 使用扇出内插器小芯片的高密度互连
CN112687670A (zh) * 2019-10-18 2021-04-20 台湾积体电路制造股份有限公司 集成电路结构及其形成方法
CN112687670B (zh) * 2019-10-18 2023-11-03 台湾积体电路制造股份有限公司 集成电路结构及其形成方法
WO2021189942A1 (zh) * 2020-03-27 2021-09-30 矽磐微电子(重庆)有限公司 半导体封装方法及半导体封装结构
CN113725095A (zh) * 2020-03-27 2021-11-30 矽磐微电子(重庆)有限公司 半导体封装方法及半导体封装结构
CN113725095B (zh) * 2020-03-27 2024-05-24 矽磐微电子(重庆)有限公司 半导体封装方法及半导体封装结构

Also Published As

Publication number Publication date
US20190244871A1 (en) 2019-08-08
DE102016101685A1 (de) 2017-03-23
US20230123427A1 (en) 2023-04-20
DE102016101685B4 (de) 2021-10-14
TWI616956B (zh) 2018-03-01
US20170084555A1 (en) 2017-03-23
CN106548948B (zh) 2020-01-14
US20180342435A1 (en) 2018-11-29
US10049953B2 (en) 2018-08-14
US11532529B2 (en) 2022-12-20
US10269674B2 (en) 2019-04-23
KR20170034758A (ko) 2017-03-29
TW201721771A (zh) 2017-06-16
KR101892801B1 (ko) 2018-08-28

Similar Documents

Publication Publication Date Title
CN106548948A (zh) 集成多输出封装件及制造方法
US11469218B2 (en) Devices employing thermal and mechanical enhanced layers and methods of forming same
TWI578460B (zh) 半導體封裝組件及其形成方法
CN102931173B (zh) 多芯片晶圆级封装
CN108766940B (zh) 用于3d封装的应力补偿层
CN106558573A (zh) 半导体封装结构及形成该半导体封装结构的方法
CN109786268A (zh) 半导体封装件中的金属化图案及其形成方法
TWI567906B (zh) 封裝的半導體元件及與其形成方法
CN106486383A (zh) 封装结构及其制造方法
TW201530729A (zh) 層疊封裝元件及其製造方法
CN103119711A (zh) 形成完全嵌入式非凹凸内建层封装件的方法和由此形成的结构
TW201535596A (zh) 堆疊式封裝裝置與其形成方法
CN107301981A (zh) 集成的扇出型封装件以及制造方法
US11257785B2 (en) Multi-module integrated interposer and semiconductor device formed therefrom
CN202394961U (zh) 具有散热柱的半导体晶圆及封装构造
US20220384393A1 (en) Wafer-level stacked die structures and associated systems and methods
CN202394957U (zh) 半导体晶圆及封装构造
US11961824B2 (en) Semiconductor package including stacked chip structure
US20220173075A1 (en) Chip Package and Method of Forming the Same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant