CN103579183A - 中介层***及方法 - Google Patents

中介层***及方法 Download PDF

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Publication number
CN103579183A
CN103579183A CN201210592167.2A CN201210592167A CN103579183A CN 103579183 A CN103579183 A CN 103579183A CN 201210592167 A CN201210592167 A CN 201210592167A CN 103579183 A CN103579183 A CN 103579183A
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area
intermediary layer
region
semiconductor element
circuit
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CN201210592167.2A
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CN103579183B (zh
Inventor
余振华
郑心圃
侯上勇
叶德强
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明提供了一种用于设置中介层的***和方法。实施例包括在中介层晶圆上形成第一区域和第二区域，其中，该中介层在第一区域和第二区域之间具有划线区域。然而，第一区域和第二区域通过位于划线区域上方的电路相互连接。在另一个实施例中，第一区域和第二区域可以相互分离，然后在第一区域连接至第二区域之前，将第一区域和第二区域密封在一起。

Description

中介层***及方法
技术领域
本发明一般地涉及半导体技术领域，更具体地来说，涉及半导体器件及其制造方法。
背景技术
半导体器件用于各种电子应用(诸如个人计算机、手机、数码相机及其他电子设备等)中。半导体产业通过不断减少最小部件的尺寸来连续提高各种电子部件(例如，晶体管、二极管、电阻器、电容器等)的集成密度，从而允许更多的部件集成在指定区域中。由于集成部件所占用的体积基本上是位于半导体晶圆的表面上，因此，实际上这些集成度改善基本都是二维(2D)的。尽管在光刻方面的显著提高已经引起了2D集成电路结构大幅提高，但是还存在可以以二维实现的密度方面的物理局限性。这些局限性中的一个是制造这些部件需要的最小尺寸。而且，当更多的器件置于一个芯片中时，需要更复杂的设计。另一个局限性来自于随着器件数量的增加器件之间的互连件的数量和长度也显著增加。当互连件的数量和长度增加时，电路RC延迟和功耗都会增加。
因此，在一些应用中，已经将注意力转移到比以前的封装件使用更小面积的较小封装件上。已经开发的一种更小的封装件是三维(3D)IC，其中，两个管芯或IC接合在一起，并且，电连接件使用位于中介层上的接触焊盘形成在各个管芯之间。
在这些情况下，电源线和信号线可以穿过中介层。这些线可以是从中介层的一侧到中介层相对侧上的管芯或其他电连接件的连接件。
发明内容
为了解决现有技术中所存在的缺陷，根据本发明的一方面，提供了一种半导体器件，包括：中介层，具有第一侧和第二侧，所述中介层包括：第一区域，包括第一电路；第二区域，包括第二电路；和第三区域，位于所述第一区域和所述第二区域之间，所述第三区域没有电路并且从所述第一侧延伸到所述第二侧；以及导电路径，位于所述第一区域和所述第二区域之间，所述导电路径在所述第三区域上方延伸。
在该半导体器件中，所述第三区域为位于所述第一区域和所述第二区域之间的划线区域。
在该半导体器件中，所述第三区域包括密封剂。
在该半导体器件中，所述导电路径为第一半导体管芯的一部分。
该半导体器件进一步包括附接至所述第一区域的第二半导体管芯。
在该半导体器件中，所述第一电路和所述第二电路具有不同的图案。
在该半导体器件中，所述第一电路与所述第二电路相同。
根据本发明的另一方面，提供了一种半导体器件，包括：中介层，具有位于第二区域和第三区域之间且没有功能电路的第一区域；第一接触件，位于所述第二区域中；第二接触件，位于所述第三区域中；以及导电路径，在所述第一区域上方延伸，所述导电路径电连接所述第一接触件和所述第二接触件。
在该半导体器件中，所述导电路径是位于所述第一区域上方的第一半导体管芯的一部分。
该半导体器件进一步包括位于所述第二区域上方的第二半导体管芯。
在该半导体器件中，所述导电路径包括位于所述第一区域上方的钝化后互连件。
该半导体器件进一步包括与所述钝化后互连件接触的第一半导体管芯。
该半导体器件进一步包括位于所述第二区域和所述第一区域之间的密封环。
该半导体器件进一步包括延伸穿过所述第二区域的衬底通孔。
根据本发明的又一方面，提供了一种制造半导体器件的方法，所述方法包括：使用光刻工艺在晶圆的第一区域中形成第一电路、在所述晶圆的第二区域中形成第二电路以及在所述第一区域和所述第二区域之间形成划线区域，其中，所述光刻工艺使用具有第一尺寸的图案化曝光能量并且所述晶圆的所述第一区域具有所述第一尺寸；在不分离所述第一区域和所述第二区域的情况下，将所述第一区域和所述第二区域与所述晶圆分离；并且在所述划线区域的上方将所述第一电路连接至所述第二电路。
在该方法中，所述使用光刻工艺通过使所述划线区域不暴露于所述图案化曝光能量来形成所述划线区域。
在该方法中，将所述第一电路连接至所述第二电路进一步包括将所述第一电路和所述第二电路连接至位于所述划线区域上方的半导体管芯。
在该方法中，将所述第一电路连接至所述第二电路进一步包括在所述划线区域上方形成钝化后互连件。
在该方法中，所述第一电路包括衬底通孔。
该方法进一步包括在所述划线区域和所述第一区域之间形成密封环。
附图说明
为了更完整的理解本实施例及其优点，现在将结合附图所进行的以下描述作为参考，其中，
图1示出根据实施例的第一中介层(interposer)区域和第二中介层区域；
图2示出根据实施例的第一中介层区域和第二中介层区域的分离；
图3A至图3D示出根据实施例的第一半导体管芯、第二半导体管芯和第三半导体管芯至第一中介层区域和第二中介层区域的连接；
图4示出根据实施例的连接第一中介层区域和第二中介层区域的钝化后互连件的形成；
图5示出根据实施例的第一半导体管芯、第二半导体管芯和第三半导体管芯至钝化后互连件的连接；
图6示出根据实施例的第一中介层区域从第二中介层区域上的分离；
图7示出根据实施例的第一中介层区域和第二中介层区域之间的区域的封装；以及
图8示出根据实施例的第一半导体管芯、第二半导体管芯和第三半导体管芯至第一中介层区域和第二中介层区域的连接。
除非另有说明，否则不同附图中的相应标号和符号通常指的是相应部件。绘制附图以清楚地示出实施例的相关方面而不必按比例绘制。
具体实施方式
下面，详细讨论本发明实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的创造性概念。所讨论的具体实施例仅仅示出了制造和使用所公开主题的具体方式，而不用于限制不同实施例的范围。
将参考具体上下文(即，用于半导体芯片的中介层)来描述实施例。然而，也可以将其他实施例应用于其他类型的连接器件上。
现在参考图1，示出了中介层晶圆100，该晶圆具有衬底101、第一中介层区域103、第二中介层区域105、第一划线区域107、第二划线区域109、以及第三划线区域111。例如，用于中介层晶圆100的衬底101可以是硅衬底、掺杂或不掺杂的或者绝缘体上硅(SOI)衬底的有源层，以用于为中介层晶圆100提供支撑。然而，可选地，衬底101可以是玻璃衬底、陶瓷衬底、聚合物衬底或可以提供合适的保护和/或互连功能的任何其他衬底。可选地，这些以及任何其他合适的材料均可以用于衬底101。
衬底101可以划分为第一中介层区域103和第二中介层区域105。第一中介层区域103和第二中介层区域105被设计成连接至半导体管芯，诸如，处理器和内存管芯(在图1中未示出，但是下面结合图3A进行了示出和描述)，并且被设计成，一旦第一中介层区域103和第二中介层区域105从中介层晶圆100上分离，提供半导体管芯的支撑和连接。
第一划线区域107、第二划线区域109和第三划线区域111位于中介层晶圆100上的各个中介层区域(诸如，如图1所示的第一中介层区域103和第二中介层区域105)之间并且将各个中介层区域间隔开。在一个实施例中，第一划线区域107、第二划线区域109和第三划线区域111是在其中没有形成有源电路的中介层晶圆100的区域，或者是在中介层晶圆100形成之后没有被使用的电路的区域。同样地，当期望从中介层晶圆100上去除第一中介层区域103和第二中介层区域105时，为了不损害第一中介层区域103和第二中介层区域105中的电路，可以将第一划线区域107和第三划线区域111用作要去除的区域。
在一个实施例中，第一划线区域107、第二划线区域109和第三划线区域111可以在制造中介层晶圆100上的其他部件期间形成，并且可以具有介于大约60μm和大约160μm之间(诸如大约80μm)的第一宽度w1。例如，在本文所述的一个实施例中，第一划线区域107、第二划线区域109和第三划线区域111可以与衬底通孔(TSV)113、第一金属化层115、第一接触焊盘117的形成一起形成。第一划线区域107、第二划线区域109和第三划线区域111可以与下面描述的这些结构和其他结构同时形成。
使用特定实例，第一划线区域107、第二划线区域109和第三划线区域111的部分可以在制造第一金属化层115期间形成，例如，第一金属化层115可以使用一系列的光刻掩模和蚀刻工艺，其中，可以施加许多光刻胶(例如第一光刻胶(在图1中没有单独示出))，并且这些光刻胶被显影来用作用于图案化下面的层的掩模。第一光刻胶可以是诸如深紫外(DUV)光刻胶，并且可以通过使用旋涂工艺以在制造工艺中将第一光刻胶置于在合适位置来在中介层晶圆100上沉积第一光刻胶。
一旦放置了第一光刻胶，第一光刻胶就可以被曝露给穿过图案化中间掩模(图1中没有单独示出)的例如光的能量(在图1中通过标记为106的箭头表示)，以形成将会影响第一光刻胶的标线区域(reticule field)108，从而在第一光刻胶曝露给能量的那些部分中引起反应。由于标线区域108(其第二宽度w2介于大约13mm和大约64mm之间(例如大约32mm)，并且其长度(图1中未示出)介于大约13mm和大约52mm之间(例如大约26mm))没有大到足以在单次曝光中覆盖中介层晶圆100，因此，通过对中介层晶圆100的一部分(例如，第一中介层区域103)进行曝光并接着移动至中介层晶圆100的另一部分(例如，第二中介层区域105)以逐步的方式来曝光中介层晶圆100的各个部分。以这种方式，可以通过逐步移动并曝光中介层晶圆100的每一部分来图案化中介层晶圆100。
使用逐步曝光***，可以通过对第一区域(例如，第一中介层区域103)进行曝光并接着以从第一区域横向移动一距离对紧邻的第二区域(例如，第二中介层区域105)进行曝光，从而在第一中介层区域103和第二中介层区域105之间留下未曝光区域来形成第一划线区域107、第二划线区域109和第三划线区域111。由于对第一中介层区域103和第二中介层区域105之间的未曝光区域没有进行任何处理，所以该未曝光区域将成为第二划线区域109，从而使得第二划线区域109没有任何功能电路。可以使用相似的步进模式来形成第一划线区域107和第三划线区域111。
然而，中介层晶圆100的逐步非曝光并不是可以形成第一划线区域107、第二划线区域109和第三划线区域111的唯一方法。例如，第一划线区域107、第二划线区域109和第三划线区域111可以与它们相应的紧邻中介层区域(例如，第一中介层区域103或第二中介层区域105)一起被曝光，但是这种曝光可以使第一划线区域107、第二划线区域109和第三划线区域111没有功能电路。可选地，在期望将测试电路或其他结构置于第一划线区域107、第二划线区域109和第三划线区域111中的实施例中(但是，一旦第一中介层区域103和第二中介层区域105从中介层晶圆100上分离，就不采用该实施例)，可以通过这些结构来图案化第一划线区域107、第二划线区域109和第三划线区域111。
此外，处于相同定向的相同图案化标线可用于曝光的每一步骤中，从而形成相似的标线区域108并在中介层晶圆100的每部分(例如，第一中介层区域103和第二中介层区域105)上以相同布局形成对称结构。在另一实施例中，如果需要，则可以以不同定向(例如旋转180°)将相同图案化标线用于不同部分。通过使用被相同图案化的标线，使得整个工艺更便宜并且更有效。然而，在其他实施例中，可以将被不同图案化的标线用于每次曝光中。通过形成用于中介层晶圆100的组合曝光，可以在中介层晶圆100内形成更详细更具体的图案。
作为可以用于在中介层晶圆100上方和内部形成结构并且也用于形成第一划线区域107、第二划线区域109和第三划线区域111的制造工艺的实例，可以形成穿过衬底101的衬底通孔(TSV)113，可以在衬底101的第一侧上方形成第一金属化层115和第一接触焊盘117，可以在衬底101的第二侧上方形成第二金属化层119和第二接触焊盘121。可以以与第二接触焊盘121接触的方式形成第一外部连接件123，以帮助提供电连接。将以下段落中更详细地讨论这些结构中的每一个。
可以通过应用合适的光刻胶(例如，以上描述的第一光刻胶，未示出)并进行显影，然后蚀刻衬底101以生成TSV开口(如下所述，稍后填充的)，来形成TSV 113。处于该阶段的用于TSV的开口可以形成为以延伸进入衬底101到至少大于成品中介层晶圆100的最终期望高度的深度。因此，虽然该深度取决于中介层晶圆100的整体设计，但是该深度可以在衬底101的表面下方大约1μm和大约700μm之间，其中，优选深度为大约50μm。用于TSV 113的开口的直径可以形成为介于大约1μm和大约100μm之间，诸如大约6μm。
一旦形成了TSV 113的开口，例如就可以用势垒层和导电材料来填充TSV 113的开口。势垒层可以包括诸如氮化钛的导电材料，但是也可以可选地使用其他材料，诸如氮化钽、钛、电介质等。可以使用诸如，PECVD的CVD工艺形成该势垒层。然而，可选地，可以使用其他可选的工艺，诸如，溅射或金属有机化学汽相沉积(MOVCD)。可以形成该势垒层以勾画TSV 113的开口的下面的形状的轮廓。
导电材料可以包括铜，但是可以可选地使用其他合适的材料，诸如铝、合金、掺杂多晶硅、它们的组合等。可以通过沉积晶种层，然后在该晶种层上电镀铜、填充且过填充TSV 113的开口来形成导电材料。一旦填充TSV113的开口，就可以通过研磨工艺(诸如，化学机械抛光(CMP))去除位于TSV 113开口外部的多余的势垒层和多余的导电材料，但是可以使用任何合适的去除工艺。
一旦导电材料位于TSV 113开口内，就可以实施减薄衬底101的第二侧，以暴露TSV 113开口并且通过延伸穿过衬底101的导电材料制形成TSV113。在一个实施例中，减薄衬底101的第二侧可以留下TSV 113。可以通过诸如CMP或蚀刻的平坦化工艺来实施衬底101的第二侧的减薄。
然而，如本领域技术人员所公知的，上述用于形成TSV 113的工艺仅仅是形成TSV 113的一种方法，并且其他方法也完全旨在包含在本实施例的范围内。例如，也可以使用形成TSV 113的开口、用介电材料填充TSV113的开口、减薄衬底101的第二侧暴露介电材料、去除介电材料以及用导体填充TSV 113的开口。用于在衬底101内形成TSV 113的该方法和所有其他合适的方法完全旨在包括在本实施例的范围内。
可选地，TSV 113可以形成为延伸穿过位于衬底101上方的中介层晶圆100的多层，诸如第一金属化层115(下面进一步描述)。例如，可以在形成第一金属化层115之后或者甚至部分与金属化层115同时形成TSV113。例如，可以在单个工艺步骤中形成穿过第一金属化层115和衬底101的TSV 113的开口。可选地，可以在形成第一金属化层115之前，在衬底101中形成TSV 113的开口的一部分并且进行填充，并且，与每个第一金属化层115单独形成一样，可以形成并填充随后层的TSV 113开口。可以形成TSV 113的这些工艺中的任何一种以及任何其他合适的工艺均完全旨在包括在本实施例的范围内。
第一金属化层115形成在衬底101的第一侧上方，并被设计成将衬底101的第一侧互连至衬底101第二侧上的外部器件(例如，第一半导体管芯301、第二半导体管芯303以及第三半导体管芯305，其未在图1中示出而是下文结合图3A示出并进行描述)。虽然图1示出电介质和互连件的单层，但是第一金属化层115由电介质和导电材料的交替层形成，并且可以通过任何合适的工艺(诸如，沉积、镶嵌、双镶嵌等)形成第一金属化层115。在一个实施例中，可以具有一个或多个的金属化层，但是第一金属化层115中层的准确数量至少部分取决于中介层晶圆100的设计。
第一接触焊盘117可以形成在第一金属化层115上方并与第一金属化层115电接触。第一接触焊盘117可以包括铝，但是也可以可选地使用其他材料，诸如铜。可以使用诸如溅射的沉积工艺形成材料层(未示出)然后可以通过合适的工艺(诸如，光刻掩模和蚀刻)去除材料层的一部分形成第一接触焊盘117来形成第一接触焊盘117。然而，也可以任何其他合适的工艺来形成第一接触焊盘117，诸如在电介质中形成开口，沉积用于第一接触焊盘117的材料，然后平坦化该材料和电介质。第一接触焊盘117的厚度可以形成为介于约0.5μm和约4μm之间，诸如约1.45μm。
第二金属化层119形成在衬底101的第二侧上方并被设计成将衬底101的第二侧互连至至外部接触件上。尽管图1示出为电介质和互连件的单层，但是第二金属化层119可由电介质和导电材料的交替层形成，并且可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)形成第二金属化层119。在一个实施例中，可以具有一个或多个的金属化层，但是第二金属化层119中层的准确数量至少部分取决于中介层晶圆100的设计。
第二接触焊盘121可以形成在衬底101的第二侧上的第二金属化层119上方并与第二金属化层119电接触。第二接触焊盘121可以包括铝，但是也可以可选地使用其他材料，诸如铜。可以使用诸如溅射的沉积工艺以形成材料层(未示出)，然后可以通过合适的工艺(诸如，光刻掩模和蚀刻)去除材料层的一部分以形成第二接触焊盘121来形成第二接触焊盘121。然而，也可以任何其他合适的工艺来形成第二接触焊盘121，诸如在电介质中形成开口，沉积用于第二接触焊盘121的材料，然后平坦化该材料和电介质。第二接触焊盘121的厚度可以形成为介于约0.5μm和约4μm之间，诸如约1.45μm。
可以形成第一外部连接件123以提供位于第二接触焊盘121和外部器件(图1中没有单独示出)之间的外部连接。第一外部连接件123可以是接触凸块，诸如微凸块或可控塌陷芯片连接(C4)凸块，并且可以包括诸如锡的材料或诸如银或铜的其它合适的材料。在第一外部连接件123为锡焊料凸块的实施例中，可以通过首先通过任何合适的方法(诸如蒸发、电镀、打印、焊料转移、植球等)使锡层形成为大约100μm的优选厚度来形成第一外部连接件123。一旦在结构上形成锡层，优选地实施回流来使材料成型为期望的凸块形状。
可选地，可以在第一中介层区域103和第二中介层区域105周围形成密封环125以将第一中介层区域103和第二中介层区域105与第一划线区域107、第二划线区域109和第三划线区域111分隔开。密封环125可以用于帮助保护第一中介层区域103和第二中介层区域105的功能件。此外，如果需要，密封环125可以与第一中介层区域103和第二中介层区域105中的功能电路元件电连接以提供与这些元件的电连接。密封环125可以包括诸如铜、铝、钨、它们的合金等的导电材料。然而，可选地，可以使用其他材料，诸如，多层导电材料和绝缘材料。该密封环125的厚度可以形成为介于大约5μm和大约300μm之间，诸如大约10μm。
图2示出了可将中介层晶圆100分成多个单独的中介层的划线。在一个实施例中，例如使用金刚石涂层锯(diamond coated saw)201将这些单独的中介层与中介层晶圆100分离，锯201用于沿着诸如第一划线区域107和第三划线区域111的划线切割中介层晶圆100。然而，在可选实施例中，也可以使用其他划线方法，诸如使用激光划线器或使用一系列的蚀刻或其他分离工艺以将中介层晶圆100划分成多个单独的中介层。
此外，在一个实施例中，虽然金刚石涂层锯201用于沿着第一划线区域107和第三划线区域111切割中介层晶圆100，但是金刚石层面锯201不用于切割第二划线区域109。通过没有穿过第二划线区域109进行切割，虽然第一中介层区域103和第二中介层区域105与中介层晶圆100的其余部分分开，但是第一中介层区域和第二中介层区域保持彼此固定。通过保持第一中介层区域103和第二中介层区域105彼此固定，可以获得大于光刻工艺的曝光区域的单个中介层200。例如，单个中介层200的第一宽度可以介于大约32mm和大约52mm之间，诸如大约42mm。
然而，如本领域技术人员所公知的，处于该阶段的第一中介层区域103与第二中介层区域105的分离仅是示例性的，而并不用于进行限定。相反地，第一中介层区域103与第二中介层区域105可以在制造工艺期间的任何期望阶段被分离，包括在半导体管芯(例如，下面参照图3A和3B描述的第一半导体管芯301、第二半导体管芯303和第三半导体管芯305)的附接之后。可以利用将第一中介层区域103与第二中介层区域105分离的任何合适的时间，并且所有的这样的时间完全旨在包括在本实施例中。
图3A示出了单个中介层200与第一半导体管芯301、第二半导体管芯303和第三半导体管芯305的连接。在一个实施例中，例如，第一半导体管芯301可以是诸如图形处理单元的逻辑管芯，而第二半导体管芯303和第三半导体管芯305可以是存储器管芯。然而，可选地，可以使用任何合适的组合半导体管芯以及任何数量的半导体管芯，并且所有这种数量、组合和功能性均完全旨在包含在本实施例的范围内。
图3B示出了用于第一半导体管芯301、第二半导体管芯303和第三半导体管芯305的可重复的Logic×1+DRAM×4布局的一个实施例的平面图。在一个实施例中，第二半导体管芯303和第三半导体管芯305中的多个可以设置在位于中心的第一半导体管芯301周围。在一个实施例中，第一半导体管芯301(例如，逻辑管芯)的第三宽度w3可以介于约11mm和约33mm之间，诸如约22mm，第二长度l2介于约16mm和约36mm之间，诸如约26mm。第二半导体管芯303(例如，DRAM)的第四宽度w4可以介于约7mm和约14mm之间，诸如约7mm，第三长度l3可以介于约7mm和约17mm之间，诸如约12mm。可以在整个中介层晶圆100上重复这种连接布局。
图3C示出了可以利用Logic×1+DRAM×8图案的可选布局。在该实施例中，6个第二半导体管芯303和第三半导体管芯305位于第一半导体管芯301的周围。例如，2个第二半导体管芯303可以位于第一半导体管芯301的每一侧。
图3D示出了可以使用第一半导体管芯301、第二半导体管芯303和第三半导体管芯305的多种布局。在第一区域310中，第一半导体管芯301位于两个第二半导体管芯303的相对侧。在第二区域312中，第一半导体管芯301的单个内核被设置为紧邻第二半导体管芯303和第三半导体管芯305。在第三区域314中，第一半导体管芯301的两个内核被布置为紧邻两个第二半导体管芯303。在第四区域316中，转换了第三区域314的布局。这些和所有其他合适的布局均完全旨在包括在本实施例的范围内。
现在，再次参考图3A，在一个实施例中，第一半导体管芯301、第二半导体管芯303和第三半导体管芯305中的每一个均分别包括第二衬底307、有源器件(在图3A中未单独示出)、第三金属化层309、第三接触焊盘311和第二外部连接件313。第二衬底307可以是具有(110)的晶体定向的半导体材料，诸如硅、锗、金刚石等。可选地，也可以使用具有其他晶体定向的复合材料，诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、硅锗碳化物、磷砷化镓、磷化铟镓、它们的组合等。此外，第二衬底307可以包括绝缘体上硅(SOI)衬底。通常，SOI衬底包括半导体材料层，诸如外延硅、锗、硅锗、SOI、绝缘体上硅锗(SGOI)或它们的组合。第二衬底307可以掺杂有p型掺杂剂，诸如，硼、铝、锗等，但是本领域公知的是，该衬底可以可选地掺杂有n型掺杂剂。
第一半导体管芯301、第二半导体管芯303和第三半导体管芯305中的每一个均可以具有形成在它们相应的第二衬底307上的有源器件。如本领域技术人员所公知的，可以使用多种有源器件和无源器件，诸如电容器、电阻器、电感器等以生成设计的期望结构和功能要求。例如，与晶体管耦合的电容器可以用于形成第二半导体管芯303和第三半导体管芯305中的存储单元。可以使用任何合适的方法在相应的第二衬底307的表面内或者上形成有源器件。
第三金属化层309可以形成在相应的第二衬底307和有源器件上方，并且被设计成连接它们相应的管芯上的多个第一有源器件以形成功能电路。第三金属化层309可以由介电材料和导电材料的交替层形成，并且可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)形成。在一个实施例中，存在通过至少一个层间介电层(ILD)与第二衬底307分离的四个金属化层，但是第三金属化层309的准确数量是分别取决于第一半导体管芯301、第二半导体管芯303和第三半导体管芯305的设计。
此外，可以对第一半导体管芯301内的第三金属化层309进行图案化以提供单个中介层200内的第一中介层区域103和第二中介层区域105之间的连接通路317。可以利用第一半导体管芯301内的连接通路317以在第一中介层区域103和第二中介层区域105之间传递信号和/或功率并且使用第一中介层区域103和第二中介层区域105作为单个单元来代替作为两个分离的不同单元。在一个实施例中，可以形成连接通路317，使得当第一半导体管芯301连接至单个中介层200时，连接通路317将越过第二划线区域109和密封环125以在第一中介层区域103和第二中介层区域105之间建立电连接。
第三接触焊盘311可以形成在位于相应管芯上的第三金属化层309上方并且与该第三金属化层电接触。第三接触焊盘311可以包括铝，但是也可以可选地使用诸如铜的其他材料。可以使用诸如溅射的沉积工艺以形成材料层(未示出)，然后可以通过合适的工艺(诸如光刻掩模和蚀刻)去除材料层的一部分以形成第三接触焊盘311来形成第三接触焊盘311。然而，可以使用任何其他合适的工艺来形成第三接触焊盘311，诸如，在电介质中形成开口、沉积用于第三接触焊盘311材料、然后平坦化该材料和电介质。第三接触焊盘311的厚度可以形成为介于约0.5μm和约4μm之间，诸如约1.45μm。
可以形成第二外部连接件313以提供第三接触焊盘311和单个中介层200之间的外部连接。第二外部连接件313可以是接触凸块，诸如微凸块或可控塌陷芯片连接(C4)凸块，并且可以包括诸如锡的材料或诸如银或铜的其它合适的材料。在第二外部连接件313为锡焊接凸块的实施例中，可以通过首先通过任何合适的方法(诸如蒸发、电镀、打印、焊料转移、植球等)使锡层形成至大约100μm的优选厚度来形成第二外部连接件313。一旦在结构上形成锡层，优选地，就实施回流来使材料成型为期望的凸块形状。
此外，可以在单个中介层200和任何器件之间使用伪凸块(在图3A中没有单独示出)，诸如单个中介层200可以连接至第一半导体管芯301、第二半导体管芯303和第三半导体管芯305。这些伪凸块可以用于为结构提供支撑并减少可能产生的应力。通过提供这种支撑，可以防止存储和使用过程中可能出现的重复的热循环和环境循环期间的损害。
可以将第一半导体管芯301、第二半导体管芯303、第三半导体管芯305置于在单个中介层200上。在一个实施例中，可以以第一接触焊盘117面对第二外部连接件313并与该第二外部连接件313对准的方式将第一半导体管芯301、第二半导体管芯303、第三半导体管芯305置于单个中介层200上。一旦对准，就可以通过第二外部连接件313与第一接触焊盘117接触并实施回流以将第二外部连接件313的材料回流并接合至第一接触焊盘117来将第二外部连接件313和第一接触焊盘117接合在一起。然而，可以可选地使用任何合适的接合方法，诸如铜-铜接合，以将第一半导体管芯301、第二半导体管芯303和第三半导体管芯305接合至单个中介层200。
可以在第一半导体管芯301、第二半导体管芯303和第三半导体管芯305与单个中介层200之间的空间内注射或者以不同的方法形成底部填充材料315。例如，该底部填充材料315可以包括液态环氧树脂，液态环氧树脂被散布在第一半导体管芯301、第二半导体管芯303和第三半导体管芯305与单个中介层200之间，然后进行固化以被硬化。该底部填充材料315可以用于防止在第二外部连接件313中形成裂缝，其中，该裂缝通常由热应力引起。
可选地，为了防止在第二外部连接件313中产生裂缝，可以在第一半导体管芯301、第二半导体管芯303和第三半导体管芯305与单个中介层200之间形成可变形的凝胶或硅橡胶。可以通过在第一半导体管芯301、第二半导体管芯303和第三半导体管芯305与单个中介层200之间注射或以其它方式放置该凝胶或橡胶来形成该凝胶或硅橡胶。该可变形的凝胶或硅橡胶也可以在随后的工艺期间提供应力消除。
通过保持第一中介层区域103和第二中介层区域105之间的连接并且通过在第二划线区域109上方形成连接通路317以互连第一中介层区域103和第二中介层区域105，可以克服通过光刻工艺设定的单个中介层上的尺寸限制。这使得在中介层的设计和使用上以及连接件的数量和类型上更加灵活，其中，该连接件可以将中介层连接至半导体管芯和其它器件。
图4示出了另一实施例，其中，代替第一中介层区域103通过第一半导体管芯301连接至第二中介层区域105，第一中介层区域103通过形成在第一中介层区域103、第二中介层区域105和第二划线区域109上方的钝化后互连件(PPI)407连接至第二中介层区域105。然而，由于用于PPI407的光刻曝光区域并不像用于第一中介层区域103和第二中介层区域105的光刻曝光区域那样有限，所以用于形成PPI 407的光刻掩模和蚀刻工艺可以用于同时图案化第一中介层区域103和第二中介层区域105。
在一个实施例中，可以通过首先在衬底101上形成第一钝化层401来在第一金属化层115和第一接触焊盘117上方形成PPI 407。第一钝化层401可以由一个或多个合适的介电材料制成，诸如二氧化硅、氮化硅、诸如掺碳氧化物的低k电介质、诸如掺多孔碳的二氧化硅的超低k电介质、它们的组合等。第一钝化层401可以通过诸如化学汽相沉积(CVD)的工艺形成，但是可以使用其他合适的工艺，并且第一钝化层401的厚度可以介于0.5μm和约5μm之间，诸如约
Figure BDA00002674494700151
形成第一钝化层401之后，可以通过去除第一钝化层401一部分以暴露下面的第一接触焊盘117的至少一部分来制作穿过第一钝化层401的开口。该开口允许第一接触焊盘117和PPI 407(在下面进一步描述)之间的接触。可以使用合适的光刻掩模和蚀刻工艺形成该开口，但是可以使用任何合适的工艺以暴露第一接触焊盘117的一部分。
在暴露第一接触焊盘117之后，可以形成沿着第一钝化层401延伸的PPI 407。PPI 407可以用作再分布层以允许第一中介层区域103和第二中介层区域105通过PPI 407相互电连接，并且用于提供在第一半导体管芯301、第二半导体管芯303、第三半导体管芯305与单个中介层200之间的信号和功率布线的额外灵活性。在一个实施例中，可以通过合适的形成工艺(诸如CVD或溅射)最初形成钛铜合金的晶种层(未示出)来形成PPI 407。然后形成光刻胶(未示出)以覆盖晶种层，然后图案化光刻胶以暴露晶种层的位于期望PPI 407定位的位置处的那些部分。
一旦形成并图案化光刻胶，就可以通过诸如电镀的沉积工艺在晶种层上形成诸如铜的导电材料。该导电材料的厚度可以形成为介于约1μm和约10μm之间，诸如约5μm，其沿着衬底101的宽度介于约5μm和约300μm之间，诸如15μm。然而，虽然所描述的材料和方法适于形成导电材料，但是这些材料仅仅是示例性的。可选地，可以使用诸如AlCu或Au的任何其他合适的材料和诸如CVD或PVD的任何其他合适的形成工艺以形成PPI407。
一旦形成导电材料，就可以通过诸如灰化的合适的去除工艺来去除光刻胶。而且，在去除光刻胶之后，例如，可以通过使用导电材料作为掩模的合适的蚀刻工艺来去除晶种层被光刻胶覆盖的那些部分。
一旦形成PPI 407，就可以形成第二钝化层405以保护PPI 407和其他下面的结构。第二钝化层405可以由诸如聚酰亚胺的聚合物形成，或者可选地，可以由与第一钝化层401类似的材料(例如，二氧化硅、氮化硅、低k电介质、超低k电介质、它们的组合等)形成。第二钝化层405的厚度可以形成为介于约2μm和约15μm之间，诸如约5μm，并且第二钝化层405可以通过诸如CMP的工艺与PPI 407一起被平坦化。
图5示出了第一中介层区域103和第二中介层区域105与中介层晶圆100分离之后通过PPI 407与单个中介层200连接的第一半导体管芯301、第二半导体管芯303和第三半导体管芯305的布置。在一个实施例中，第一半导体管芯301、第二半导体管芯303和第三半导体管芯305可以以第一接触焊盘117面对PPI 407并与PPI 407对准的方式置于单个中介层上。一旦对准，然后第二外部连接件313和PPI 407就可以通过将第二外部连接件313与PPI 407接触并且实施回流以回流第二外部连接件313的材料并接合至PPI 407来接合在一起。然而，可选地，可以使用任何合适的接合方法，诸如，铜-铜接合以将第一半导体管芯301、第二半导体管芯303和第三半导体管芯305接合至PPI 407。
通过在第二划线区域109上方形成PPI 407，PPI 407有助于电互连第一中介层区域103和第二中介层区域105。第一中介层区域103和第二中介层区域105的互连有助于将第一中介层区域103和第二中介层区域105用作单个中介层以代替仅仅是物理上相互附接的多个中介层。该集成使得单个中介层200更有效并且集成度更高。
图6示出了用于另一实施例的起始点，其中，例如利用金刚石层面锯201经由第一划线区域107、第二划线区域109和第三划线区域111进行分割第一中介层区域103和第二中介层区域105与中介层晶圆100分离并且相互分离。然而，在第一中介层区域103和第二中介层区域105相互分离之后，第一中介层区域103和第二中介层区域105可以再接合在一起。
在一个实施例中，例如，第一中介层区域103和第二中介层区域105可以使用成型装置(未示出)接合在一起。例如，第一中介层区域103和第二中介层区域105可以置于成型装置的腔体中，并且该腔体可以被气密性地密封。可以在气密性地密封腔体之前将密封剂701置于腔体内，或者通过注射口将密封剂注射到腔体内。在一个实施例中，密封剂701可以是模塑料树脂，例如，聚酰亚胺、PPS、PEEK、PES、耐热水晶树脂、它们的组合等。
一旦将密封剂701置于腔体中使得密封剂701密封第一中介层区域103和第二中介层区域105之间的区域，可以固化密封剂701以硬化用于提供最佳保护的密封剂701。虽然严格的固化工艺至少部分取决于选择用于密封剂701的特定材料，但是在将模塑料选为密封剂701的实施例中，可以通过诸如将密封剂701加热到介于约100℃与约130℃之间(诸如加热到约125℃并加热约60秒到约3000秒，诸如600秒)的工艺来进行固化。此外，密封剂701中可以包括引发剂和/或催化剂以更好地控制固化工艺。
然而，如本领域技术人员所公知的，上述的固化工艺仅仅是示例性的工艺，并不意味着限定本实施例。可选地，也可以使用其它固化工艺，诸如，照射甚至允许在环境温度下硬化该密封剂701。可以使用任何合适的固化工艺，并且所有这样的工艺均完全旨在包含在本文所论述的实施例的范围内。
通过密封第一中介层区域103和第二中介层区域105之间的区域，密封剂701用作将第一中介层区域103和第二中介层区域105物理连接到单个中介层200的桥。该桥用于代替上述实施例所论述的未被划线的第二划线区域109，并且由于第一中介层区域103和第二中介层区域105被分离且(如果需要)被重新接合以用于更有效的工艺集成，所以该桥提供了更多的灵活性。
图8示出了第一半导体管芯301、第二半导体管芯303和第三半导体管芯305放置并接合至单个中介层200上。在一个实施例中，第一半导体管芯301、第二半导体管芯303和第三半导体管芯305可以以第一接触焊盘117面对第二外部连接件313并与第二外部连接件313对准的方式放置在单个中介层上。一旦对准，第二外部连接件313和第一接触焊盘117就可以通过将第二外部连接件313与第一接触焊盘117接触并且实施回流以回流第二外部连接件313的材料且接合至第一接触焊盘117来接合在一起。然而，可选地，可以使用任何合适的接合方法，诸如，铜-铜接合，以将第一半导体管芯301、第二半导体管芯303和第三半导体管芯305接合至单个中介层200。
根据一个实施例，提供了一种包括具有第一侧和第二侧的中介层的半导体器件。该中介层包括具有第一电路的第一区域、具有第二电路的第二区域和位于第一区域和第二区域之间的第三区域，该第三区域没有电路并且从第一侧延伸到第二侧。导电通路位于第一区域和第二区域之间，该导电通路在第三区域上方延伸。
根据另一个实施例，提供了一种包括中介层的半导体器件，其中，划线区域位于第一区域和第二区域之间。第一接触件位于第一区域中，第二接触件位于第二区域中。导电通路在划线区域上方延伸，该导电通路电连接第一接触件和第二接触件。
根据又一个实施例，提供一种制造半导体器件的方法，该方法包括：使用光刻工艺以在晶圆的第一区域中形成第一电路、在晶圆的第二区域中形成第二电路以及在第一区域和第二区域之间形成划线区域，其中，光刻工艺使用通过第一尺寸的被图案化的曝光能量，并且提供了具有第一尺寸晶圆的第一区域。在第一区域与第二区域不分离的情况下，将第一区域和第二区域与晶圆分离，并且第一电路与第二电路在划线区域上方相连接。
尽管已经详细地描述了本实施例及其优势，但应该理解，可以在不背离所附权利要求限定的本发明的精神和范围的情况下，做各种不同的改变、替换和更改。例如，可以改变或变更制造确切材料和方法，也可以重新设置工艺步骤的顺序，但是这仍然保持在本实施例的范围内。
而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明，现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造、材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。

Claims (10)

1.一种半导体器件，包括：
中介层，具有第一侧和第二侧，所述中介层包括：
第一区域，包括第一电路；
第二区域，包括第二电路；和
第三区域，位于所述第一区域和所述第二区域之间，所述第三区域没有电路并且从所述第一侧延伸到所述第二侧；以及
导电路径，位于所述第一区域和所述第二区域之间，所述导电路径在所述第三区域上方延伸。
2.根据权利要求1所述的半导体器件，其中，所述第三区域为位于所述第一区域和所述第二区域之间的划线区域。
3.根据权利要求1所述的半导体器件，其中，所述第三区域包括密封剂。
4.根据权利要求1所述的半导体器件，其中，所述导电路径为第一半导体管芯的一部分。
5.根据权利要求4所述的半导体器件，进一步包括附接至所述第一区域的第二半导体管芯。
6.根据权利要求1所述的半导体器件，其中，所述第一电路和所述第二电路具有不同的图案。
7.根据权利要求1所述的半导体器件，其中，所述第一电路与所述第二电路相同。
8.一种半导体器件，包括：
中介层，具有位于第二区域和第三区域之间且没有功能电路的第一区域；
第一接触件，位于所述第二区域中；
第二接触件，位于所述第三区域中；以及
导电路径，在所述第一区域上方延伸，所述导电路径电连接所述第一接触件和所述第二接触件。
9.根据权利要求8所述的半导体器件，其中，所述导电路径是位于所述第一区域上方的第一半导体管芯的一部分。
10.一种制造半导体器件的方法，所述方法包括：
使用光刻工艺在晶圆的第一区域中形成第一电路、在所述晶圆的第二区域中形成第二电路以及在所述第一区域和所述第二区域之间形成划线区域，其中，所述光刻工艺使用具有第一尺寸的图案化曝光能量并且所述晶圆的所述第一区域具有所述第一尺寸；
在不分离所述第一区域和所述第二区域的情况下，将所述第一区域和所述第二区域与所述晶圆分离；并且
在所述划线区域的上方将所述第一电路连接至所述第二电路。
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