TW201642428A - 矽中介層與其製作方法 - Google Patents

矽中介層與其製作方法 Download PDF

Info

Publication number
TW201642428A
TW201642428A TW104120221A TW104120221A TW201642428A TW 201642428 A TW201642428 A TW 201642428A TW 104120221 A TW104120221 A TW 104120221A TW 104120221 A TW104120221 A TW 104120221A TW 201642428 A TW201642428 A TW 201642428A
Authority
TW
Taiwan
Prior art keywords
integrated circuit
wafer
interposer
redistribution layer
circuit wafer
Prior art date
Application number
TW104120221A
Other languages
English (en)
Inventor
管式凡
施能泰
Original Assignee
華亞科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 華亞科技股份有限公司 filed Critical 華亞科技股份有限公司
Publication of TW201642428A publication Critical patent/TW201642428A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H01L23/295—Organic, e.g. plastic containing a filler
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

本發明披露一矽中介層，包含一矽基板，具有一正面及相對於正面的一背面；一第一積體電路晶片，設置於矽基板的正面；一第二積體電路晶片，設置於矽基板的正面且靠近第一積體電路晶片；一虛設切割道區域，設置於第一積體電路晶片與第二積體電路晶片間；以及至少一電路元件，設置於矽基板正面的虛設切割道區域中。

Description

矽中介層與其製作方法
本發明概括而言係關於一半導體元件，特別是關於一種矽中介層，在其晶片之間的切割道內設有電路元件。
在半導體技術領域中，積體電路通常經過封裝製程，變成一封裝體後，再安裝於印刷電路板或電腦系統主機板上。積體電路可以被安裝至一基板或一中介層上，然後再以塑膠材料或環氧樹酯材料包覆封裝。
上述封裝過程可以採用該領域技術人員所熟知的覆晶技術，將積體電路的輸入/輸出(input/output, I/O)面(或主動面)朝下，安裝至所述基板或中介層的安裝面上。
已知，中介層的主要功用是將具相對較小墊距(pad pitch)的積體電路晶片的接觸墊扇出(fan out)以匹配印刷電路板上具較大墊距的接觸墊。如能更進一步利用中介層，使其不僅具扇出積體電路訊號的功用，實為該領域所期望。
根據本發明提供的矽中介層，包含一矽基板，具有一正面及相對於正面的一背面；一第一積體電路晶片，設置於矽基板的正面；一第二積體電路晶片，設置於矽基板的正面且與第一積體電路晶片緊密靠近；一虛設切割道區域，設置於第一積體電路晶片與第二積體電路晶片間；以及至少一電路元件，設置於矽基板正面的虛設切割道區域中。
根據本發明一實施例，一位於矽基板正面的重佈線層，覆蓋住第一積體電路晶片、第二積體電路晶片與虛設切割道區域。在矽基板內部形成的直通矽穿孔，與重佈線層電性連接。
無庸置疑的，該領域的技術人士讀完接下來本發明較佳實施例的詳細描述與圖式後，均可了解本發明的目的。
接下來的詳細敘述須參附圖所示內容，用來說明可依據本發明具體實行的實施例。這些實施例提供足夠的細節，可使此領域中的技術人員充分了解並具體實行本發明。在不悖離本發明的範圍內，可做結構、邏輯和電性上的修改應用在其他實施例上。
因此，接下來的詳細敘述並非用來對本發明加以限制。本發明涵蓋的範圍由其權利要求所定義。與其權利要求具同等意義者也應屬本發明涵蓋的範圍。
本發實施例所參照的附圖為示意圖，並未按比例繪製，且相同或類似的特徵通常以相同的附圖標記描述。
在本說明書中，“晶粒”、“半導體晶片”與“半導體晶粒”具相同含意，可交換使用。在本說明書中，“晶圓”與“基板”意指任何具一暴露面，可在其上沉積材料並製作例如本發明實施例所示的積體電路的結構物。需了解的是“基板”通常包含半導體晶圓。
製程中所稱的“晶圓”與“基板”，可為包含製作於其上的材料層的半導體結構物。“晶圓”與“基板”兩者都包含已摻雜或未摻雜的半導體、具有基底或絕緣體支撐的磊晶半導體層，以及其他該領域技術人員所熟知的半導體結構。
請參照第1圖至第6圖，為根據本發明一實施例，製作一具有直通矽穿孔(TSV)的矽中介層與半導體晶片的封裝體的方法。
首先，如第1圖所示，提供一晶圓(中介層晶圓)100，例如半導體晶圓或矽晶圓。晶圓100包含一正面100a與一相對於正面100a的背面100b。根據本發明實施例，在晶圓100的正面100a上具有複數個晶片(或晶粒)10。
根據本發明實施例，每個晶片10內的積體電路，可包含記憶體陣列、周邊電路、邏輯電路，但並不限於此。根據本發明實施例，晶片10可為一記憶體晶片，但並不限於此。
為了簡化說明，在此不詳述製作晶片10的積體電路的製程步驟。一般而言，這些製程步驟包含習知的技術，例如圖案化製程、蝕刻製程、佈植製程、熱處理、研磨製程、薄膜沉積製程，以及其他類似製程。
根據本發明實施例，晶片10之間具有切割道200，將晶片10互相分隔開。根據本發明實施例，切割道200包含一第一切割道區域201與一第二切割道區域202。
根據本發明實施例，僅沿著第一切割道區域201切割晶圓100，可得到包含複數個晶片10的多晶片中介層11。例如，如第7圖所示，沿著第一切割道區域201切割晶圓100，可得到一具有2x2晶片陣列的多晶片中介層11。須了解的是多晶片中介層11中的2x2晶片陣列僅為說明目的，其他晶片的矩陣排列，例如3x1晶片陣列、3x2晶片陣列或2x1晶片陣列也包含在本發明的範圍。第二切割道區域202也可被稱為“虛設切割道區域”。
同樣參照第1圖，根據本發明實施例，第二切割道區域202內包含電路元件12。第二切割道區域202內的電路元件12是以上述習知的半導體製程技術，與晶片10中的積體電路同時製作於晶圓100上。電路元件12包含主動電路元件，例如金氧半導體元件或電晶體、被動電路元件，例如電容、電阻、電感，或其他電路元件，例如熔絲電路或靜電放電(ESD)保護元件。
根據本發明實施例，在晶圓100的正面100a上提供一重佈線層(RDL)110。重佈線層110包含至少一介電層112、金屬繞線114，與提供後續連接使用的凸塊墊116。須了解的是第1圖中，重佈線層110的結構僅為說明目的，在其他實施例中，重佈線層110可為多疊層結構，以符合不同電路設計的需求。
如第2圖所示，接著在重佈線層110上形成微凸塊120，選擇性地將半導體晶粒20安裝至重佈線層110上方。根據本發明實施例，半導體晶粒20藉由微凸塊120與重佈線層110電性連接。須了解的是第2圖中，半導體晶粒20的數量僅為說明目的。在一些實施例中，可不包含半導體晶粒20。
如第3圖所示，接著在晶圓100的正面100a上形成一成型模料130。成型模料130包覆住安裝在重佈線層110上方的晶粒20與重佈線層110的頂面。最佳者，成型模料130完全填滿晶粒20之間的空隙。接著，可繼續進行一成型模料130的固化製程。
根據本發明實施例，藉由轉移壓模機，可將熱固性成型模料成型到晶圓100上，或採用其他成型模料的形成方法。成型模料可為環氧化物、樹脂，或者其他室溫或高溫下為液態的化合物。成型模料130是電絕緣體，但可為熱導體，可在其中添加不同種類的填充劑，改善成型模料130的導熱性、剛性或黏著性質。
如第4圖所示，成型模料130形成之後，接著對晶圓100進行一研磨製程，自背面100b研磨移除掉部分晶圓100。例如，先將晶圓100載入至一晶圓研磨機，然後一研磨頭與晶圓100的背面100b接觸，並開始研磨。晶圓100在經過研磨製程後，具有較薄的厚度。
如第5圖所示，接著在晶圓100中形成與重佈線層110電性連接的直通矽穿孔(TSV)140。例如，自晶圓100的背面100b，蝕刻選定的連接點的晶圓100，形成一TSV孔洞。接著，在TSV孔洞中沉積一擴散阻擋層與金屬導電層。藉由在背面100b施加一晶背研磨或化學機械研磨製程，移除TSV孔洞外多餘的金屬導電層。
如第6圖所示，在晶圓100的背面100b上形成焊接凸塊310或其他焊接物，與各個直通矽穿孔140電性連接。接著，如第7圖所示，沿著第一切割道201切割晶圓100，得到多晶片中介層11。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
10‧‧‧晶片
100‧‧‧晶圓(中介層晶圓)
100a‧‧‧正面
100b‧‧‧背面
11‧‧‧多晶片中介層
110‧‧‧重佈線層
112‧‧‧介電層
114‧‧‧金屬繞線
116‧‧‧凸塊墊
12‧‧‧電路元件
120‧‧‧微凸塊
130‧‧‧成型模料
140‧‧‧直通矽穿孔
20‧‧‧半導體晶粒
200‧‧‧切割道
201‧‧‧第一切割道區域
202‧‧‧第二切割道區域
310‧‧‧焊接凸塊
310‧‧‧焊接凸塊
所附圖式提供對於此實施例更深入的了解，並納入此說明書成為其中一部分。這些圖式與描述，用來說明一些實施例的原理。圖式中:       第1圖至第6圖為示意性剖面圖，說明根據本發明一實施例，製作一具有直通矽穿孔(TSV)的矽中介層與半導體晶片的封裝體的方法。       第7圖為晶圓俯視圖，示意性說明本發明一實施例的2x2晶片陣列與第一和第二切割道區域。
10‧‧‧晶片
100‧‧‧晶圓(中介層晶圓)
11‧‧‧多晶片中介層
200‧‧‧切割道
201‧‧‧第一切割道區域
202‧‧‧第二切割道區域

Claims (9)

  1. 一種矽中介層，包含有: 一矽基板，具有一正面及與該正面相對的一背面； 一第一積體電路晶片，位於該矽基板的該正面； 一第二積體電路晶片，位於該矽基板的該正面且與靠近該第一積體電路晶片； 一虛設切割道區域，位於該第一積體電路晶片與該第二積體電路晶片間；以及 至少一電路元件，位於該矽基板的該正面上且位於該虛設切割道區域中。
  2. 如申請專利範圍第1項所述的矽中介層，其中該虛設切割道區域將該第一積體電路晶片與該第二積體電路晶片分隔開。
  3. 如申請專利範圍第1項所述的矽中介層，其中該電路元件包含金氧半導體、電晶體、電容、電阻、電感、熔絲電路，或靜電放電保護元件。
  4. 如申請專利範圍第1項所述的矽中介層，其中另包含一重佈線層位於該正面，其中該重佈線層覆蓋住該第一積體電路晶片、該第二積體電路晶片與該虛設切割道區域。
  5. 如申請專利範圍第4項所述的矽中介層，其中該重佈線層包含至少一介電層、金屬繞線，與提供後續連接使用的凸塊墊。
  6. 如申請專利範圍第4項所述的矽中介層，其中另包含位於該矽基板中的直通矽穿孔，與該重佈線層電性連接。
  7. 如申請專利範圍第4項所述的矽中介層，其中另包含至少一半導體晶粒安裝在該重佈線層上。
  8. 如申請專利範圍第7項所述的矽中介層，其中該半導體晶粒藉由微凸塊與該重佈線層電性連接。
  9. 如申請專利範圍第7項所述的矽中介層，其中另包含一成型模料位於該正面，其中該成型模料包覆住該半導體晶粒與該重佈線層的頂面。
TW104120221A 2015-05-25 2015-06-24 矽中介層與其製作方法 TW201642428A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/720,840 US9455243B1 (en) 2015-05-25 2015-05-25 Silicon interposer and fabrication method thereof

Publications (1)

Publication Number Publication Date
TW201642428A true TW201642428A (zh) 2016-12-01

Family

ID=56939537

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104120221A TW201642428A (zh) 2015-05-25 2015-06-24 矽中介層與其製作方法

Country Status (3)

Country Link
US (1) US9455243B1 (zh)
CN (1) CN106206557B (zh)
TW (1) TW201642428A (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017073472A (ja) * 2015-10-07 2017-04-13 株式会社ディスコ 半導体装置の製造方法
TWI721383B (zh) * 2019-03-08 2021-03-11 力成科技股份有限公司 具有多個積體電路單元的封裝結構及其製作方法
TW202034485A (zh) * 2019-03-08 2020-09-16 力成科技股份有限公司 具有多個積體電路單元的扇出型封裝結構及其製作方法
CN111710662B (zh) * 2020-07-01 2022-03-22 无锡中微亿芯有限公司 一种通用多裸片硅堆叠互连结构

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011097175A2 (en) * 2010-02-05 2011-08-11 Luxera, Inc. Integrated electronic device for controlling light emitting diodes
US8901527B2 (en) * 2010-07-02 2014-12-02 Nanya Technology Corp. Resistive random access memory structure with tri-layer resistive stack
US8963334B2 (en) 2011-08-30 2015-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. Die-to-die gap control for semiconductor structure and method
US8810006B2 (en) * 2012-08-10 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Interposer system and method
US10032696B2 (en) * 2012-12-21 2018-07-24 Nvidia Corporation Chip package using interposer substrate with through-silicon vias
US20140252632A1 (en) 2013-03-06 2014-09-11 Hans-Joachim Barth Semiconductor devices

Also Published As

Publication number Publication date
US9455243B1 (en) 2016-09-27
CN106206557A (zh) 2016-12-07
CN106206557B (zh) 2019-01-15

Similar Documents

Publication Publication Date Title
US11069656B2 (en) Three-layer package-on-package structure and method forming same
US11710693B2 (en) Wafer level package utilizing molded interposer
KR102256262B1 (ko) 집적 회로 패키지 및 방법
US11631611B2 (en) Wafer level chip scale packaging intermediate structure apparatus and method
KR101892801B1 (ko) 집적 팬아웃 패키지 및 그 제조 방법
US10181457B2 (en) Microelectronic package for wafer-level chip scale packaging with fan-out
TWI567916B (zh) 封裝與方法
TWI556349B (zh) 半導體裝置的結構及其製造方法
TWI575664B (zh) 封裝結構及其形成方法
TW201725659A (zh) 使用熱與機械強化層的裝置及其製造方法
TW201810570A (zh) 半導體封裝及其製作方法
US10008469B2 (en) Wafer-level packaging using wire bond wires in place of a redistribution layer
TW202010084A (zh) 半導體封裝及其製造方法
TW201635449A (zh) 電子封裝件及其製法與基板結構
US20220028842A1 (en) Heat dissipation in semiconductor packages and methods of forming same
KR20200074847A (ko) 임베디드 전압 조정기 구조물 및 그 형성 방법
TW201830607A (zh) 半導體晶片封裝
US10529693B2 (en) 3D stacked dies with disparate interconnect footprints
TW201642428A (zh) 矽中介層與其製作方法
TW201701429A (zh) 晶圓級封裝及其製作方法
TW202209618A (zh) 半導體封裝及其形成方法
US20230420331A1 (en) Semiconductor package and method
US20230011353A1 (en) Chip package structure and method for forming the same