CN107026153A - 封装件 - Google Patents

封装件 Download PDF

Info

Publication number
CN107026153A
CN107026153A CN201611046177.0A CN201611046177A CN107026153A CN 107026153 A CN107026153 A CN 107026153A CN 201611046177 A CN201611046177 A CN 201611046177A CN 107026153 A CN107026153 A CN 107026153A
Authority
CN
China
Prior art keywords
tube core
voltage regulator
integrated voltage
encapsulating material
regulator tube
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201611046177.0A
Other languages
English (en)
Other versions
CN107026153B (zh
Inventor
余振华
侯上勇
李云汉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN107026153A publication Critical patent/CN107026153A/zh
Application granted granted Critical
Publication of CN107026153B publication Critical patent/CN107026153B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/10—Inductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H10K19/10—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/101—Forming openings in dielectrics
    • H01L2221/1015—Forming openings in dielectrics for dual damascene structures
    • H01L2221/1026—Forming openings in dielectrics for dual damascene structures the via being formed by burying a sacrificial pillar in the dielectric and removing the pillar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/107—Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Electromagnetism (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

本发明的实施例提供了一种封装件，包括集成调压器(IVR)管芯，其中，IVR管芯包括位于第一IVR管芯的顶面处的金属柱。封装件还包括其中包封第一IVR管芯的第一包封材料，其中，第一包封材料具有与金属柱的顶面共面的顶面。多条再分布线位于第一包封材料和IVR管芯上方。多条再分布线电耦合至金属柱。核心芯片与多条再分布线重叠并且接合至多条再分布线。第二包封材料中包封核心芯片，其中，第一包封材料的边缘和第二包封材料的相应的边缘彼此垂直对准。***件或封装件衬底位于IVR管芯下面并且接合至IVR管芯。

Description

封装件
技术领域
本发明的实施例涉及半导体领域，更具体地涉及一种封装件。
背景技术
中央处理单元(CPU)对输入/输出(IO)和CPU消耗的功率具有较高的要求。例如，CPU可以包括多个核心并且需要消耗相当大的功率。另一方面，对提供的功率的要求也很高。例如，供电电压需要非常稳定。因此，多个调压器可以连接至同一CPU芯片以提供电源。
发明内容
本发明的实施例提供了一种封装件，包括：第一集成调压器(IVR)管芯，其中，所述第一集成调压器管芯包括：金属柱，位于所述第一集成调压器管芯的顶面处；第一包封材料，将所述第一集成调压器管芯包封在所述第一包封材料中，其中，所述第一包封材料具有与所述金属柱的顶面共面的顶面；多条再分布线，位于所述第一包封材料和所述第一集成调压器管芯上方，其中，所述多条再分布线电耦合至所述金属柱；第一核心芯片，与所述多条再分布线重叠并且接合至所述多条再分布线；第二包封材料，将所述第一核心芯片包封在所述第二包封材料中，其中，所述第一包封材料的边缘和所述第二包封材料的相应的边缘彼此垂直对准；以及***件或封装件衬底，位于所述第一集成调压器管芯下面并且接合至所述第一集成调压器管芯。
本发明的实施例还提供了一种封装件，包括：第一集成调压器(IVR)管芯和第二集成调压器管芯，每个都包括：金属柱；调压器电路，电耦合至所述金属柱；和电感器，电耦合至所述调压器电路；第一包封材料，将所述第一集成调压器管芯和所述第二集成调压器管芯包封在所述第一包封材料中，其中，所述第一包封材料具有与所述第一集成调压器管芯和所述第二集成调压器管芯中的所述金属柱的顶面共面的顶面；介电层，与所述第一集成调压器管芯、所述第二集成调压器管芯、和所述第一包封材料重叠；多条再分布线，具有位于所述介电层中的部分，其中，所述多条再分布线电耦合至所述第一集成调压器管芯和所述第二集成调压器管芯；第一中央处理单元(CPU)芯片和第二中央处理单元芯片，分别与所述第一集成调压器管芯和所述第二集成调压器管芯重叠并且分别电耦合至所述第一集成调压器管芯和所述第二集成调压器管芯；以及第二包封材料，将所述第一中央处理单元芯片和所述第二中央处理单元芯片包封在所述第二包封材料中。
本发明的实施例还提供了一种封装件，包括：第一器件管芯，包括：半导体衬底；第一贯通孔和第二贯通孔，贯穿所述半导体衬底；有源电路，位于所述半导体衬底的表面处；第一金属柱，位于所述第一器件管芯的顶面处，其中，所述第一金属柱电耦合至所述有源电路和所述第一贯通孔；以及第二金属柱，位于所述第一器件管芯的顶面处，其中，所述第二金属柱电耦合至所述第二贯通孔，并且所述第二金属柱与所述第一器件管芯中的所有有源电路电断开；第一包封材料，将所述第一器件管芯包封在所述第一包封材料中；第二器件管芯，与所述第一器件管芯重叠并且电耦合至所述第一器件管芯；以及封装件组件，位于所述第一器件管芯下面并且接合至所述第一器件管芯，其中，所述第二贯通孔和所述第二金属柱将所述封装件组件电耦合至所述第二器件管芯。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明的实施例。应该强调的是，根据工业中的标准实践，对各种部件没有按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或缩小。
图1至图9示出了根据一些实施例的在包括集成调压器的封装件的形成中的中间阶段的截面图。
图10示出了根据一些实施例的包括集成调压器的封装件的截面图。
图11示出了根据一些实施例的用于形成封装件的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件形成为直接接触的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字母。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…下面”、“在…下方”、“下部”、“在…上面”、“上部”等的空间相对术语，以便于描述如图所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而在此使用的空间相对描述符可以同样地作相应的解释。
根据各个示例性实施例提供了一种多层级封装件及其形成方法。可以使用衬底上晶圆上芯片(Chip-on-Wafer-on-Substrate，CoWoS)工艺形成多层级封装件。示出了形成该封装件的中间阶段。讨论了一些实施例的一些变型。贯穿各个视图和说明性实施例，相同的参考标号用于表示相同的元件。
图1至图9示出了根据一些实施例的在多层级封装件的形成中的中间阶段的截面图。图1至图9中示出的步骤也在图11中示出的工艺流程200中示意性地示出。
参照图1，提供了载体20，并且在载体20上方设置粘合层22。载体20可以是空白玻璃载体、空白陶瓷载体、有机载体等，并且可以具有圆形顶视图形状的半导体晶圆的形状。有时，载体20被称为载体晶圆。例如，粘合层22可以由光热转换(LTHC)材料形成，并且也可以使用其他类型的粘合剂。根据本发明的一些实施例，粘合层22在光的热量下能够分解，并且因此能够从形成在其上的结构释放载体20。
参照图2，在粘合层22上方放置器件管芯24(包括24A、24B、24C、24D和24E)。相应的步骤示出为图11中示出的工艺流程中的步骤202。贯穿说明书，器件管芯24还被称为层级1管芯。应该理解，在晶圆级下实施随后讨论的工艺步骤。因此，具有与包括器件管芯24A、24B、24C、24D、和24E的管芯组相同的多个管芯组。多个管芯组可以布置为包括多行和多列的阵列。器件管芯24可以彼此相同或彼此不同。例如，器件管芯24A、24B、24C、和24D可以彼此相同，并且不同于器件管芯24E。
根据本发明的一些实施例，器件管芯24为包括用于为上面的管芯调节电压供给的调压器的集成调压器(IVR)管芯。IVR中的电路示意性示出为在半导体衬底28上形成的26。根据本发明的可选实施例，器件管芯24包括逻辑管芯或诸如静态随机存取存储器(SRAM)管芯、动态随机存取存储器(DRAM)管芯等的存储器管芯。
IVR电路26可以包括模拟泵电路(pump circuit)、数字控制块、以及用于调节电压的其它电路。例如，模拟泵电路用于将电流泵入上面的逻辑管芯。数字控制块具有确定模拟电路何时需要泵电流(pump current)的功能。当被用于先进的IVR时，数字控制块可以确定需要开启模拟泵的多少相，从而优化至上面的器件管芯的电流输出。此外，器件管芯24还可以包括电耦合至模拟泵电路和数字控制块的电感器30。IVR电路还可以包括位于器件管芯52(包括52A、52B、和52C，图9)中的电压下降检测电路。电压下降检测电路由上面的器件管芯52(图8)使用以检测电压下降、数字化、并且反馈至器件管芯24中的模拟泵电路。
根据本发明的一些实施例，器件管芯24是独立IVR管芯，其中，除了由调压器电路使用的那些，没有其他逻辑电路设置在器件管芯24中。根据可选实施例，一些逻辑电路或存储器电路与调压器电路一起设置在器件管芯24内部。
器件管芯24包括半导体衬底28，其可以是硅衬底、硅碳衬底、III-V族化合物半导体衬底等。器件管芯24还包括互连结构32。根据本发明的一些实施例，互连结构32包括多个介电层34、以及在介电层34中的金属线和通孔(未示出)。介电层34可以包括可以由低k介电材料形成的金属间介电(IMD)层，例如，低k介电材料的介电常数(k值)低于3.5、低于约3.0、或低于约2.5。此外，靠近器件管芯24的顶面，可以具有诸如氮化硅层、氧化硅层、未掺杂的硅酸盐玻璃(USG)层、和/或聚合物层的非低k钝化层。此外，在表面介电层34中的金属柱40(包括40A和40B)位于互连结构32的表面处。金属柱40可以是含铜焊盘、含铝焊盘等。根据一些实施例，介电层34的顶部的一个的顶面与金属柱40的顶面共面。根据一些实施例，表面介电层34的一部分覆盖金属柱40。表面介电层34可以是聚合物层，例如，其可以由聚苯并恶唑(PBO)形成。
电感器30嵌入在互连结构32中，且还是调压器电路的部分。电感器30可以使用连接的金属线和通孔形成以具有线圈的形状。因此，根据本发明的一些实施例，电感器30是集成在与IVR电路相同的芯片中的芯片上电感器。根据本发明的可选实施例，电感器30形成在IVR管芯24的外部作为独立电感器。
器件管芯24还包括贯通孔(可选地称为硅贯通孔或衬底贯通孔)36(包括36A和36B)。应该理解，尽管贯通孔36示出为贯穿图2中的半导体衬底，但是在载体20上方放置器件管芯24时，贯通孔36可以不延伸至半导体衬底28的底面处。此外，贯通孔36延伸至介于半导体衬底28的顶面和底面之间的中间平面，并且如图7所示，贯通孔36的底端将在随后的背面研磨步骤中被暴露。每个贯通孔36都通过环绕相应的贯通孔36的介电层(未示出)与相应的半导体衬底28电绝缘。
贯通孔36A和36B用于将半导体衬底28上方的导电部件连接至相应的半导体衬底28下面的导电部件。贯通孔36B电耦合至相应的器件管芯24内部得器件(诸如IVR电路、导线、电感器30等)。贯通孔36B还可以电耦合至金属柱40B。另一方面，器件管芯24中的贯通孔36A单独地用于将相应的器件管芯24上方的导电部件(诸如图8中的器件管芯52)连接至器件管芯24下面的导电部件(诸如图8中的***件70中的金属焊盘)。贯通孔36A不连接至器件管芯24内部的任何其它电路(包括诸如晶体管和二极管的有源器件和诸如电容器、电感器、电阻器等的无源器件)。因此，贯通孔36A用于互连器件管芯24外部的部件，且不用于至器件管芯24内部的电路的内连接。或者说，贯通孔36A具有与模制贯通孔(未示出)相同的功能，而模制贯通孔可以设置在器件管芯24的外部且贯穿包封材料44(图8)。然而，在器件管芯24内部形成贯通孔36A没有额外的制造成本，这是因为与模制贯通孔不同，贯通孔36A和贯通孔36B同时形成。此外，由于贯通孔36A使用用于形成器件管芯的技术形成，所以贯通孔36可以具有比模制贯通孔更高的密度和更小的尺寸，并且贯通孔36A的总数可以高于模制贯通孔。
如图2所示，每个贯通孔36A都连接至将相应的贯通孔36A电耦合至金属柱40A的导电路径38中的一个。导电路径38可以是没有分支/分叉的单布线路径，且不连接至相应的器件管芯24中的任何其它金属柱40B、电感器、电阻器、电容器、晶体管、二极管等。因此，尽管位于器件管芯24中，但是贯通孔36A不涉及与电压调节有关的电压/信号传送。此外，尽管导电路径38被示出为直的路径，但是它们可以包括水平金属线。使用贯通孔36A(和导电路径38)以替代模制贯通孔的有益特征在与，导电路径38具有再布线功能，金属柱40A不必重叠相应的贯通孔36A，而模制贯通孔是直的且垂直，以及不能被再布线。
参照图3，在器件管芯24上包封包封材料44。相应的步骤示出为图11中示出的工艺流程中的步骤204。包封材料44被分配，并且然后例如，在热固化工艺中被固化。包封材料44填充器件管芯24之间的间隙，并且可以与粘合层22接触。包封材料44可以包括模塑料、模制底部填充物、环氧树脂和/或树脂。在包封工艺之后，包封材料44的顶面高于金属柱40和贯通孔14的顶端。
接下来，实施诸如化学机械抛光(CMP)步骤或研磨步骤的平坦化步骤以平坦化包封材料44，直到暴露器件管芯24的金属柱40。相应的步骤示出为图11中示出的工艺流程中的步骤206。图3中示出生成的结构。由于平坦化，所以金属柱40的顶面与包封材料44的顶面基本齐平(共面)。
参考图4，在包封材料44和器件管芯24上方形成介电层46和相应的再分布线(RDL)48的一层或多层。相应的步骤示出为图11中示出的工艺流程中的步骤208。根据本发明的一些实施例，介电层46由诸如PBO、聚酰亚胺等的聚合物形成。根据本发明的可选实施例，介电层46由诸如氮化硅、氧化硅、氮氧化硅等的无机介电材料形成。
RDL 48形成为电耦合至金属柱40。RDL 48可以包括金属迹线(金属线)和通孔，该通孔位于相应的金属迹线下面并且连接至相应的金属迹线。根据本发明的一些实施例，通过镀敷工艺形成RDL 48，其中，每个RDL 48都包括晶种层(未示出)和位于晶种层上方的镀敷的金属材料。晶种层和镀敷的金属材料可以由相同材料或不同材料形成。
在RDL 48的形成期间，图案化介电层46以形成通孔开口(由RDL 48占据)，并且上层RDL 48延伸至通孔开口内以接触下层RDL 48或金属柱40。此外，一些RDL 48可以电互连器件管芯24。可以图案化(例如，使用激光)顶部介电层46以在其中形成开口50，从而暴露RDL 48中的一些金属焊盘。
图5示出了器件管芯52(包括52A、52B、和52C)接合至RDL 48中的暴露的金属焊盘上。相应的步骤示出为图11中示出的工艺流程中的步骤210。贯穿说明书，器件管芯52还称为层级2管芯。器件管芯52可以通过焊料区56接合至金属焊盘48。每个器件管芯52都可以包括使其背面朝上的半导体衬底58。器件管芯52还包括位于半导体衬底58的正面(朝下的表面)处的集成电路器件54(诸如包括例如晶体管的有源器件，未示出)。器件管芯52A和52B可以包括诸如中央处理单元(CPU)管芯、图像处理单元(GPU)管芯、移动应用管芯等的逻辑管芯。器件管芯52A和52B可以彼此相同。器件管芯52C可以是用于器件管芯52A和52B的输入/输出的(高速)输入/输出(IO)管芯。使用虚线示出的RDL 60表示器件管芯52A和52B至IO管芯52C的电连接。
根据其中器件管芯52A和52B是CPU管芯的一些实施例，集成电路54可以包括多个功能电路，诸如控制单元、存储器组件、时钟电路、焊盘收发器电路、逻辑门单元库等。控制单元控制CPU的数据路径。存储器组件包括寄存器文件、高速缓冲存储器(SRAM单元)等。时钟电路包括时钟驱动器、锁相环(PLL)、时钟分配网络等。使用逻辑门单元库以执行逻辑操作。
器件管芯52A电连接至器件管芯24A和24B。此外，器件管芯24A和24B调节电压供给以用于器件管芯52A。器件管芯52B连接至器件管芯24C和24D。此外，器件管芯24C和24D调节电压供给以用于器件管芯52B。器件管芯52A和器件管芯52B中的每一个都可以包括多个核心，并且器件管芯52A和器件管芯52B可选地称为核心芯片。可以是IO芯片的器件管芯52C连接至器件管芯24E，器件管芯24E调节电压以用于IO芯片52C。根据本发明的一些实施例，器件管芯52A与器件管芯24A和24B完全重叠。器件管芯52A还可横向地延伸超过器件管芯24A和24B的边缘。器件管芯52B与器件管芯24C和24D完全重叠。器件管芯52B还可横向地延伸超过器件管芯24C和24D的边缘。
参照图6，在器件管芯52上包封包封材料64。相应的步骤示出为图11中示出的工艺流程中的步骤212。包封材料64可以包括模塑料、模制底部填充物、环氧树脂或树脂。包封材料64的底面物理接触顶部介电层46的顶面。在分配之后，例如，在热固化工艺中固化包封材料64。根据本发明的一些实施例，实施平坦化步骤以平坦化包封材料64直到包封材料64的顶面与器件管芯52的顶面共面。相应的步骤示出为图11中示出的工艺流程中的步骤214。根据本发明的可选实施例，不实施平坦化，且在最终结构中，包封材料64包括与器件管芯52重叠的一些部分。贯穿说明书，层22上面的结构称为封装件66，封装件66包括多个封装件，每个封装件都包括器件管芯24A、24B、24C、24D、24E、以及52A、52B、和52C。
接下来，封装件66从载体20脱离。相应的步骤示出为图11中示出的工艺流程中的步骤216。图7中示出生成的结构。例如，通过将UV光或激光投射在粘合层22上实施封装件66从载体20的脱离。例如，当粘合层22由LTHC形成时，由UV光或激光生成的热导致LTHC分解，并且因此载体20从封装件66分离。实施背面研磨以研磨器件管芯24和包封材料44的底部部分。实施背面研磨直到暴露贯通孔36A和36B的底端。根据一些实施例，在器件管芯24的底部处形成金属焊盘和/或金属迹线(未示出)以电连接至贯通孔36A和36B。根据可选实施例，在器件管芯24的底部处没有形成金属焊盘和/或金属迹线。
在随后的步骤中，实施管芯锯切以将封装件66锯切为分立的封装件68，分立的封装件68彼此相同，分立的封装件68中的一个示出在图8中。相应的步骤在图11所示的工艺流程图中示出为步骤216。
由于封装件68是从封装件68锯切的，所以包封材料44的边缘与包封材料64的相应边缘垂直对准。此外，包封材料44的边缘还与介电层46的相应边缘垂直对准。
接下来，参考图8，封装件68接合至***件70。根据一些示例性实施例，通过焊料区71实施接合。根据可选实施例，可以使用诸如混合接合的其它接合方法。相应的步骤示出为图11中示出的工艺流程中的步骤218。接合可以是晶圆上芯片(CoW)接合，其中，多个封装件(芯片)68接合至同一***件晶圆，该***件晶圆包括与示出的***件70相同的多个***件。根据本发明的一些实施例，基本与图10中的互连结构84相同的互连结构(未示出)可以形成在封装件68的底部处，其中，互连结构中的RDL电耦合至贯通孔36A和36B。***件70可以包括半导体衬底72(其可以是硅衬底)和半导体衬底72上方的互连结构74。在互连结构74中形成金属线和通孔76。在半导体衬底72中形成贯通孔78。***件70没有诸如晶体管和二极管的有源器件。***件70可以没有、或可以包括诸如电阻器、电感器、电容器等的无源器件(未示出)。可以在封装件68和***件70之间分配底部填充物73。然后，***件晶圆可以被锯开成多个封装件，每个封装件都包括***件70和上面的器件管芯24和52。
参照图9，例如，***件70通过焊料区82接合至封装件衬底80。相应的步骤示出为图11中示出的工艺流程中的步骤220。封装件衬底80可以是层压衬底(少核芯)或可以具有核心。封装件衬底80中的导电迹线和/或核心(未示出)电连接至焊料区82。封装件衬底80可以具有比上面的***件70的顶面面积大的顶面面积。
图10示出了根据可选实施例的封装件。除了没有使用***件，这些实施例类似于图9中的实施例，并且封装件68直接接合至封装件衬底80。根据本发明的一些实施例，封装件68包括在器件管芯24和包封材料44的底面处形成的互连结构84。可以使用与用于形成介电层46和RDL 48基本相同的方法和材料形成互连结构，并且因此在此不再赘述。
本发明的实施例具有一些有利的特征。如图9和图10所示，器件管芯52A可以具有比器件管芯24A和24B的总顶面面积大的顶面面积。相应地，可以在相应的核心芯片52A下面直接放置器件管芯24A和24B，且器件管芯24A、24B、以及52A的总顶面面积基本上是器件管芯52A的顶面面积。通过将IVR管芯(诸如24A和24B)直接放置在其对应的核心器件管芯(诸如52A)下面，从核心器件管芯至其调压器的距离被最小化。相似地，通过将IVR管芯24E直接放置在器件管芯52C下面，从器件管芯52C至IVR管芯24E中的该器件管芯的调压器的距离被最小化。因此提高了电源效率。作为对照，如果IVR管芯被放置在核心芯片的附近，因为IVR管芯更靠近核心芯片中的一些核心且远离核心芯片中的其它核心，所以布局不平衡。通过将IVR管芯24直接放置在IVR管芯24服务的核心芯片下面，使布局平衡。
此外，由于器件管芯24较小，所以模制贯通孔可以由贯通孔36A替代，否则，模制贯通孔将被形成(如果不使用本发明的实施例)以将***件70/封装件衬底80连接至器件管芯52。这消除了用于形成模制贯通孔的成本，同时没有用于形成贯通孔36A的产生成本(因为贯通孔36A与贯通孔36B同时形成)。此外，IVR管芯24在它们的互连结构中通常具有低密度的金属线和通孔。因此，IVR管芯的互连结构可以用于形成嵌入式电感器。
根据本发明的一些实施例，一种封装件包括IVR管芯，其中，IVR管芯包括位于第一IVR管芯的顶面处的金属柱。封装件还包括将第一IVR管芯包封在其中的第一包封材料，其中，第一包封材料具有与金属柱的顶面共面的顶面。多条再分布线位于第一包封材料和IVR管芯上方。多条再分布线电耦合至金属柱。核心芯片与多条再分布线重叠且接合至多条再分布线。第二包封材料将核心芯片包封在其中，其中，第一包封材料的边缘和第二包封材料的相应的边缘彼此垂直对准。***件或封装件衬底位于IVR管芯下面且接合至IVR管芯。
根据本发明的一些实施例，一种封装件包括第一IVR管芯和第二IVR管芯，每个IVR管芯都包括金属柱、电耦合至金属柱的调压器电路、以及电耦合至调压器电路的电感器。第一包封材料将第一IVR管芯和第二IVR管芯包封在其中。第一包封材料具有与位于第一IVR管芯和第二IVR管芯中的金属柱的顶面共面的顶面。介电层与第一IVR管芯、第二IVR管芯、和第一包封材料重叠。多条再分布线包括位于介电层中的部分。多条再分布线电耦合至第一IVR管芯和第二IVR管芯。第一CPU芯片和第二CPU芯片分别与第一IVR管芯和第二IVR管芯重叠且分别电耦合至第一IVR管芯和第二IVR管芯。第二包封材料将第一CPU芯片和第二CPU芯片包封在其中。
根据本发明的一些实施例，一种封装件包括：第一器件管芯，第一器件管芯包括半导体衬底、贯穿半导体衬底的第一贯通孔和第二贯通孔；半导体衬底的表面处的有源电路；第一器件管芯的顶面处的第一金属柱；以及第一器件管芯的顶面处的第二金属柱。第一金属柱电耦合至有源电路和第一贯通孔。第二金属柱电耦合至第二贯通孔，且与第一器件管芯中的所有有源电路电断开。封装件还包括将第一器件管芯包封在其中的第一包封材料，并且第二器件管芯与第一器件管芯重叠且电耦合至第一器件管芯。封装件组件位于器件管芯下面且接合至器件管芯。第二贯通孔和第二金属柱将封装件组件电耦合至第二器件管芯。
本发明的实施例提供了一种封装件，包括：第一集成调压器(IVR)管芯，其中，所述第一集成调压器管芯包括：金属柱，位于所述第一集成调压器管芯的顶面处；第一包封材料，将所述第一集成调压器管芯包封在所述第一包封材料中，其中，所述第一包封材料具有与所述金属柱的顶面共面的顶面；多条再分布线，位于所述第一包封材料和所述第一集成调压器管芯上方，其中，所述多条再分布线电耦合至所述金属柱；第一核心芯片，与所述多条再分布线重叠并且接合至所述多条再分布线；第二包封材料，将所述第一核心芯片包封在所述第二包封材料中，其中，所述第一包封材料的边缘和所述第二包封材料的相应的边缘彼此垂直对准；以及***件或封装件衬底，位于所述第一集成调压器管芯下面并且接合至所述第一集成调压器管芯。
根据本发明的一个实施例，其中，所述第一集成调压器管芯包括：半导体衬底；以及贯通孔，位于所述半导体衬底中，其中，所述贯通孔将所述第一核心芯片电耦合至所述***件或所述封装件衬底，而没有电耦合至所述第一集成调压器管芯中的电路。
根据本发明的一个实施例，其中，所述第一集成调压器管芯包括：半导体衬底；互连结构，位于所述半导体衬底上面；以及内置电感器，位于所述互连结构中。
根据本发明的一个实施例，封装件还包括与所述第一集成调压器管芯相同的第二集成调压器管芯，所述第二集成调压器管芯包封在所述第一包封材料中，其中，所述第二集成调压器管芯与所述第一核心芯片重叠并且电耦合至所述第一核心芯片。
根据本发明的一个实施例，封装件还包括：第三集成调压器管芯，包封在所述第一包封材料中；以及输入/输出管芯，包封在所述第二包封材料中，其中，所述输入/输出管芯与所述第三集成调压器管芯重叠并且电耦合至所述第三集成调压器管芯。
根据本发明的一个实施例，封装件还包括：第四集成调压器管芯和第五集成调压器管芯，包封在所述第一包封材料中，其中，所述第四集成调压器管芯和所述第五集成调压器管芯与所述第一集成调压器管芯相同；以及第二核心芯片，与所述第四集成调压器管芯和所述第五集成调压器管芯重叠并且电耦合至所述第四集成调压器管芯和所述第五集成调压器管芯。
根据本发明的一个实施例，其中，所述第一集成调压器管芯包括半导体衬底，所述半导体衬底的底面与所述第一包封材料的底面共面。
根据本发明的一个实施例，其中，所述***件接合至所述第一集成调压器管芯，以及所述***件横向地延伸超过所述第一包封材料的所述边缘。
根据本发明的一个实施例，其中，所述***件包括：附加的半导体衬底；以及附加的贯通孔，贯穿所述附加的半导体衬底。
本发明的实施例还提供了一种封装件，包括：第一集成调压器(IVR)管芯和第二集成调压器管芯，每个都包括：金属柱；调压器电路，电耦合至所述金属柱；和电感器，电耦合至所述调压器电路；第一包封材料，将所述第一集成调压器管芯和所述第二集成调压器管芯包封在所述第一包封材料中，其中，所述第一包封材料具有与所述第一集成调压器管芯和所述第二集成调压器管芯中的所述金属柱的顶面共面的顶面；介电层，与所述第一集成调压器管芯、所述第二集成调压器管芯、和所述第一包封材料重叠；多条再分布线，具有位于所述介电层中的部分，其中，所述多条再分布线电耦合至所述第一集成调压器管芯和所述第二集成调压器管芯；第一中央处理单元(CPU)芯片和第二中央处理单元芯片，分别与所述第一集成调压器管芯和所述第二集成调压器管芯重叠并且分别电耦合至所述第一集成调压器管芯和所述第二集成调压器管芯；以及第二包封材料，将所述第一中央处理单元芯片和所述第二中央处理单元芯片包封在所述第二包封材料中。
根据本发明的一个实施例，其中，所述第一集成调压器管芯和所述第二集成调压器管芯彼此相同，并且所述第一中央处理单元芯片和所述第二中央处理单元芯片彼此相同。
根据本发明的一个实施例，其中，所述第一包封材料的边缘与所述第二包封材料的相应的边缘垂直对准。
根据本发明的一个实施例，封装件还包括：***件或封装件衬底，位于所述第一集成调压器管芯和所述第二集成调压器管芯下面并且接合至所述第一集成调压器管芯和所述第二集成调压器管芯。
根据本发明的一个实施例，封装件还包括：第三集成调压器管芯，包封在所述第一包封材料中；以及输入/输出管芯，包封在所述第二包封材料中，其中，所述输入/输出管芯与所述第三集成调压器管芯重叠并且电耦合至所述第三集成调压器管芯。
本发明的实施例还提供了一种封装件，包括：第一器件管芯，包括：半导体衬底；第一贯通孔和第二贯通孔，贯穿所述半导体衬底；有源电路，位于所述半导体衬底的表面处；第一金属柱，位于所述第一器件管芯的顶面处，其中，所述第一金属柱电耦合至所述有源电路和所述第一贯通孔；以及第二金属柱，位于所述第一器件管芯的顶面处，其中，所述第二金属柱电耦合至所述第二贯通孔，并且所述第二金属柱与所述第一器件管芯中的所有有源电路电断开；第一包封材料，将所述第一器件管芯包封在所述第一包封材料中；第二器件管芯，与所述第一器件管芯重叠并且电耦合至所述第一器件管芯；以及封装件组件，位于所述第一器件管芯下面并且接合至所述第一器件管芯，其中，所述第二贯通孔和所述第二金属柱将所述封装件组件电耦合至所述第二器件管芯。
根据本发明的一个实施例，其中，所述第一器件管芯包括集成调压器(IVR)管芯，所述集成调压器管芯中包括集成调压器电路和电感器，以及所述第二器件管芯包括中央处理单元(CPU)管芯。
根据本发明的一个实施例，封装件还包括与所述第一集成调压器管芯相同的第二集成调压器管芯，其中，所述第二集成调压器管芯与所述第二器件管芯重叠并且电耦合至所述第二器件管芯。
根据本发明的一个实施例，封装件还包括：多条再分布线，位于所述第一包封材料和所述第一器件管芯上方，其中，所述多条再分布线电耦合至所述第一金属柱和所述第二金属柱；以及第二包封材料，将所述第二器件管芯包封在所述第二包封材料中，其中，所述第一包封材料的边缘和所述第二包封材料的相应的边缘彼此垂直对准。
根据本发明的一个实施例，封装件还包括：多个介电层，所述多条再分布线位于所述多个介电层中；以及焊料区，延伸至所述多个介电层的顶部的一个介电层中。
根据本发明的一个实施例，其中，所述第二金属柱未电耦合至所述第一器件管芯中的任何无源器件。
上面概述了若干实施例的部件、使得本领域技术人员可以更好地理解本发明的实施例。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实现与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围、并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种封装件，包括：
第一集成调压器(IVR)管芯，其中，所述第一集成调压器管芯包括：
金属柱，位于所述第一集成调压器管芯的顶面处；
第一包封材料，将所述第一集成调压器管芯包封在所述第一包封材料中，其中，所述第一包封材料具有与所述金属柱的顶面共面的顶面；
多条再分布线，位于所述第一包封材料和所述第一集成调压器管芯上方，其中，所述多条再分布线电耦合至所述金属柱；
第一核心芯片，与所述多条再分布线重叠并且接合至所述多条再分布线；
第二包封材料，将所述第一核心芯片包封在所述第二包封材料中，其中，所述第一包封材料的边缘和所述第二包封材料的相应的边缘彼此垂直对准；以及
***件或封装件衬底，位于所述第一集成调压器管芯下面并且接合至所述第一集成调压器管芯。
2.根据权利要求1所述的封装件，其中，所述第一集成调压器管芯包括：
半导体衬底；以及
贯通孔，位于所述半导体衬底中，其中，所述贯通孔将所述第一核心芯片电耦合至所述***件或所述封装件衬底，而没有电耦合至所述第一集成调压器管芯中的电路。
3.根据权利要求1所述的封装件，其中，所述第一集成调压器管芯包括：
半导体衬底；
互连结构，位于所述半导体衬底上面；以及
内置电感器，位于所述互连结构中。
4.根据权利要求1所述的封装件，还包括与所述第一集成调压器管芯相同的第二集成调压器管芯，所述第二集成调压器管芯包封在所述第一包封材料中，其中，所述第二集成调压器管芯与所述第一核心芯片重叠并且电耦合至所述第一核心芯片。
5.根据权利要求1所述的封装件，还包括：
第三集成调压器管芯，包封在所述第一包封材料中；以及
输入/输出管芯，包封在所述第二包封材料中，其中，所述输入/输出管芯与所述第三集成调压器管芯重叠并且电耦合至所述第三集成调压器管芯。
6.根据权利要求1所述的封装件，还包括：
第四集成调压器管芯和第五集成调压器管芯，包封在所述第一包封材料中，其中，所述第四集成调压器管芯和所述第五集成调压器管芯与所述第一集成调压器管芯相同；以及
第二核心芯片，与所述第四集成调压器管芯和所述第五集成调压器管芯重叠并且电耦合至所述第四集成调压器管芯和所述第五集成调压器管芯。
7.根据权利要求1所述的封装件，其中，所述第一集成调压器管芯包括半导体衬底，所述半导体衬底的底面与所述第一包封材料的底面共面。
8.根据权利要求1所述的封装件，其中，所述***件接合至所述第一集成调压器管芯，以及所述***件横向地延伸超过所述第一包封材料的所述边缘。
9.一种封装件，包括：
第一集成调压器(IVR)管芯和第二集成调压器管芯，每个都包括：
金属柱；
调压器电路，电耦合至所述金属柱；和
电感器，电耦合至所述调压器电路；
第一包封材料，将所述第一集成调压器管芯和所述第二集成调压器管芯包封在所述第一包封材料中，其中，所述第一包封材料具有与所述第一集成调压器管芯和所述第二集成调压器管芯中的所述金属柱的顶面共面的顶面；
介电层，与所述第一集成调压器管芯、所述第二集成调压器管芯、和所述第一包封材料重叠；
多条再分布线，具有位于所述介电层中的部分，其中，所述多条再分布线电耦合至所述第一集成调压器管芯和所述第二集成调压器管芯；
第一中央处理单元(CPU)芯片和第二中央处理单元芯片，分别与所述第一集成调压器管芯和所述第二集成调压器管芯重叠并且分别电耦合至所述第一集成调压器管芯和所述第二集成调压器管芯；以及
第二包封材料，将所述第一中央处理单元芯片和所述第二中央处理单元芯片包封在所述第二包封材料中。
10.一种封装件，包括：
第一器件管芯，包括：
半导体衬底；
第一贯通孔和第二贯通孔，贯穿所述半导体衬底；
有源电路，位于所述半导体衬底的表面处；
第一金属柱，位于所述第一器件管芯的顶面处，其中，所述第一金属柱电耦合至所述有源电路和所述第一贯通孔；以及
第二金属柱，位于所述第一器件管芯的顶面处，其中，所述第二金属柱电耦合至所述第二贯通孔，并且所述第二金属柱与所述第一器件管芯中的所有有源电路电断开；
第一包封材料，将所述第一器件管芯包封在所述第一包封材料中；
第二器件管芯，与所述第一器件管芯重叠并且电耦合至所述第一器件管芯；以及
封装件组件，位于所述第一器件管芯下面并且接合至所述第一器件管芯，其中，所述第二贯通孔和所述第二金属柱将所述封装件组件电耦合至所述第二器件管芯。
CN201611046177.0A 2015-11-30 2016-11-22 封装件 Active CN107026153B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201562260832P 2015-11-30 2015-11-30
US62/260,832 2015-11-30
US15/007,714 US9627365B1 (en) 2015-11-30 2016-01-27 Tri-layer CoWoS structure
US15/007,714 2016-01-27

Publications (2)

Publication Number Publication Date
CN107026153A true CN107026153A (zh) 2017-08-08
CN107026153B CN107026153B (zh) 2019-08-02

Family

ID=58692990

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201611046177.0A Active CN107026153B (zh) 2015-11-30 2016-11-22 封装件

Country Status (5)

Country Link
US (4) US9627365B1 (zh)
KR (1) KR101917418B1 (zh)
CN (1) CN107026153B (zh)
DE (1) DE102016102108B4 (zh)
TW (1) TWI627722B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111599768A (zh) * 2019-02-21 2020-08-28 力成科技股份有限公司 半导体封装及其制造方法

Families Citing this family (70)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10622310B2 (en) 2012-09-26 2020-04-14 Ping-Jung Yang Method for fabricating glass substrate package
US11069734B2 (en) 2014-12-11 2021-07-20 Invensas Corporation Image sensor device
US9768145B2 (en) * 2015-08-31 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming multi-die package structures including redistribution layers
US9627365B1 (en) 2015-11-30 2017-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-layer CoWoS structure
US9831148B2 (en) 2016-03-11 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package including voltage regulators and methods forming same
US9659911B1 (en) * 2016-04-20 2017-05-23 Powertech Technology Inc. Package structure and manufacturing method thereof
US11272618B2 (en) 2016-04-26 2022-03-08 Analog Devices International Unlimited Company Mechanically-compliant and electrically and thermally conductive leadframes for component-on-package circuits
US11625523B2 (en) 2016-12-14 2023-04-11 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips
TW202404049A (zh) 2016-12-14 2024-01-16 成真股份有限公司 標準大宗商品化現場可編程邏輯閘陣列(fpga)積體電路晶片組成之邏輯驅動器
WO2018129907A1 (zh) * 2017-01-11 2018-07-19 中芯长电半导体（江阴）有限公司 一种集成供电***的封装件及封装方法
US11430740B2 (en) * 2017-03-29 2022-08-30 Intel Corporation Microelectronic device with embedded die substrate on interposer
US10475718B2 (en) * 2017-05-18 2019-11-12 Advanced Semiconductor Engineering, Inc. Semiconductor device package comprising a dielectric layer with built-in inductor
US10217720B2 (en) 2017-06-15 2019-02-26 Invensas Corporation Multi-chip modules formed using wafer-level processing of a reconstitute wafer
US10373893B2 (en) * 2017-06-30 2019-08-06 Intel Corporation Embedded bridge with through-silicon vias
US10283474B2 (en) 2017-06-30 2019-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same
US10447274B2 (en) 2017-07-11 2019-10-15 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells
US10535643B2 (en) 2017-08-04 2020-01-14 Samsung Electronics Co., Ltd. Connection system of semiconductor packages using a printed circuit board
US10957679B2 (en) 2017-08-08 2021-03-23 iCometrue Company Ltd. Logic drive based on standardized commodity programmable logic semiconductor IC chips
US10630296B2 (en) 2017-09-12 2020-04-21 iCometrue Company Ltd. Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells
US10515888B2 (en) 2017-09-18 2019-12-24 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and method for manufacturing the same
US10403600B2 (en) * 2017-10-13 2019-09-03 Taiwan Semiconductor Manufacturing Co., Ltd. Modular voltage regulators
US10763239B2 (en) * 2017-10-27 2020-09-01 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-chip wafer level packages and methods of forming the same
US10867954B2 (en) 2017-11-15 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect chips
DE102018124695A1 (de) * 2017-11-15 2019-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Integrieren von Passivvorrichtungen in Package-Strukturen
US10608642B2 (en) 2018-02-01 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile radom access memory cells
US10623000B2 (en) 2018-02-14 2020-04-14 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US10497635B2 (en) 2018-03-27 2019-12-03 Linear Technology Holding Llc Stacked circuit package with molded base having laser drilled openings for upper package
US10608638B2 (en) 2018-05-24 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US10504873B1 (en) * 2018-06-25 2019-12-10 Taiwan Semiconductor Manufacturing Co., Ltd. 3DIC structure with protective structure and method of fabricating the same and package
US11462419B2 (en) 2018-07-06 2022-10-04 Invensas Bonding Technologies, Inc. Microelectronic assemblies
US11309334B2 (en) 2018-09-11 2022-04-19 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
US11450560B2 (en) * 2018-09-24 2022-09-20 Intel Corporation Microelectronic assemblies having magnetic core inductors
US11417593B2 (en) 2018-09-24 2022-08-16 Intel Corporation Dies with integrated voltage regulators
US10937762B2 (en) 2018-10-04 2021-03-02 iCometrue Company Ltd. Logic drive based on multichip package using interconnection bridge
US11410977B2 (en) 2018-11-13 2022-08-09 Analog Devices International Unlimited Company Electronic module for high power applications
US11211334B2 (en) 2018-11-18 2021-12-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
US11769735B2 (en) * 2019-02-12 2023-09-26 Intel Corporation Chiplet first architecture for die tiling applications
US11139270B2 (en) 2019-03-18 2021-10-05 Kepler Computing Inc. Artificial intelligence processor with three-dimensional stacked memory
US11836102B1 (en) 2019-03-20 2023-12-05 Kepler Computing Inc. Low latency and high bandwidth artificial intelligence processor
US11088068B2 (en) * 2019-04-29 2021-08-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of manufacturing the same
US10840190B1 (en) * 2019-05-16 2020-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and manufacturing method thereof
US11043472B1 (en) 2019-05-31 2021-06-22 Kepler Compute Inc. 3D integrated ultra high-bandwidth memory
US11844223B1 (en) 2019-05-31 2023-12-12 Kepler Computing Inc. Ferroelectric memory chiplet as unified memory in a multi-dimensional packaging
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US10985154B2 (en) 2019-07-02 2021-04-20 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cryptography circuits
US11227838B2 (en) 2019-07-02 2022-01-18 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cooperating or supporting circuits
KR20210007457A (ko) 2019-07-11 2021-01-20 삼성전자주식회사 반도체 패키지
KR102661671B1 (ko) * 2019-07-25 2024-04-29 삼성전자주식회사 적층된 반도체 칩들을 포함하는 반도체 패키지
US11887930B2 (en) 2019-08-05 2024-01-30 iCometrue Company Ltd. Vertical interconnect elevator based on through silicon vias
US11309243B2 (en) * 2019-08-28 2022-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package having different metal densities in different regions and manufacturing method thereof
US11637056B2 (en) 2019-09-20 2023-04-25 iCometrue Company Ltd. 3D chip package based on through-silicon-via interconnection elevator
US12021156B2 (en) * 2019-09-30 2024-06-25 Texas Instruments Incorporated Windowed wafer assemblies having interposers
KR20210079005A (ko) 2019-12-19 2021-06-29 삼성전자주식회사 반도체 패키지 및 그 제조방법
US11600526B2 (en) 2020-01-22 2023-03-07 iCometrue Company Ltd. Chip package based on through-silicon-via connector and silicon interconnection bridge
US11844178B2 (en) 2020-06-02 2023-12-12 Analog Devices International Unlimited Company Electronic component
US11715754B2 (en) * 2020-06-09 2023-08-01 Mediatek Inc. Semiconductor package with TSV inductor
IL275736A (en) * 2020-06-29 2022-01-01 Elta Systems Ltd You will include slice phase transducers, techniques and applications
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11587894B2 (en) * 2020-07-09 2023-02-21 Taiwan Semiconductor Manufacturing Company, Ltd. Package and method of fabricating the same
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
KR20220034596A (ko) * 2020-09-11 2022-03-18 삼성전자주식회사 반도체 패키지
US11355379B1 (en) * 2020-11-24 2022-06-07 International Business Machines Corporation Oxide-bonded wafer pair separation using laser debonding
EP4024222A1 (en) 2021-01-04 2022-07-06 Imec VZW An integrated circuit with 3d partitioning
US11791233B1 (en) 2021-08-06 2023-10-17 Kepler Computing Inc. Ferroelectric or paraelectric memory and logic chiplet with thermal management in a multi-dimensional packaging
US11942447B2 (en) * 2021-08-27 2024-03-26 Taiwan Semiconductor Manufacturing Co., Ltd. Storage layers for wafer bonding
US11967559B2 (en) 2021-11-24 2024-04-23 Advanced Semiconductor Engineering, Inc. Electronic package
US11881446B2 (en) * 2021-12-23 2024-01-23 Nanya Technology Corporation Semiconductor device with composite middle interconnectors
US20230253302A1 (en) * 2022-02-10 2023-08-10 Advanced Semiconductor Engineering, Inc. Electronic package
US20230268293A1 (en) * 2022-02-18 2023-08-24 Advanced Semiconductor Engineering, Inc. Electronic device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090194864A1 (en) * 2008-02-01 2009-08-06 International Business Machines Corporation Integrated module for data processing system
US20110317387A1 (en) * 2010-06-29 2011-12-29 Qualcomm Incorporated Integrated Voltage Regulator with Embedded Passive Device(s) for a Stacked IC
US20120112352A1 (en) * 2010-11-10 2012-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit system with distributed power supply
US20140306355A1 (en) * 2013-04-15 2014-10-16 Thorsten Meyer Chip interposer, semiconductor device, and method for manufacturing a semiconductor device

Family Cites Families (74)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070013080A1 (en) 2005-06-29 2007-01-18 Intel Corporation Voltage regulators and systems containing same
JP4509972B2 (ja) 2005-09-01 2010-07-21 日本特殊陶業株式会社 配線基板、埋め込み用セラミックチップ
US7701057B1 (en) 2007-04-25 2010-04-20 Xilinx, Inc. Semiconductor device having structures for reducing substrate noise coupled from through die vias
US7820543B2 (en) 2007-05-29 2010-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Enhanced copper posts for wafer level chip scale packaging
US7838424B2 (en) 2007-07-03 2010-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Enhanced reliability of wafer-level chip-scale packaging (WLCSP) die separation using dry etching
US20090008929A1 (en) * 2007-07-05 2009-01-08 David Vernon Person Pipe coupling spacer insert
US8759964B2 (en) 2007-07-17 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level package structure and fabrication methods
US7863742B2 (en) 2007-11-01 2011-01-04 Taiwan Semiconductor Manufacturing Company, Ltd. Back end integrated WLCSP structure without aluminum pads
US8039303B2 (en) 2008-06-11 2011-10-18 Stats Chippac, Ltd. Method of forming stress relief layer between die and interconnect structure
US7808258B2 (en) 2008-06-26 2010-10-05 Freescale Semiconductor, Inc. Test interposer having active circuit component and method therefor
US8193799B2 (en) * 2008-09-23 2012-06-05 Globalfoundries Inc. Interposer including voltage regulator and method therefor
US8067308B2 (en) 2009-06-08 2011-11-29 Stats Chippac, Ltd. Semiconductor device and method of forming an interconnect structure with TSV using encapsulant for structural support
TWI401753B (zh) 2009-12-31 2013-07-11 Advanced Semiconductor Eng 可堆疊式封裝結構之製造方法
US8822281B2 (en) 2010-02-23 2014-09-02 Stats Chippac, Ltd. Semiconductor device and method of forming TMV and TSV in WLCSP using same carrier
US8618654B2 (en) 2010-07-20 2013-12-31 Marvell World Trade Ltd. Structures embedded within core material and methods of manufacturing thereof
CN102859691B (zh) 2010-04-07 2015-06-10 株式会社岛津制作所 放射线检测器及其制造方法
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8217502B2 (en) 2010-06-08 2012-07-10 Stats Chippac Ltd. Integrated circuit packaging system with multipart conductive pillars and method of manufacture thereof
US8361842B2 (en) 2010-07-30 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded wafer-level bonding approaches
US8415781B2 (en) 2010-08-09 2013-04-09 Ibiden Co., Ltd. Electronic component and method for manufacturing the same
KR20120031697A (ko) 2010-09-27 2012-04-04 삼성전자주식회사 패키지 적층 구조 및 그 제조 방법
US8993377B2 (en) 2010-09-29 2015-03-31 Stats Chippac, Ltd. Semiconductor device and method of bonding different size semiconductor die at the wafer level
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8884431B2 (en) 2011-09-09 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures for semiconductor devices
TWI418269B (zh) 2010-12-14 2013-12-01 Unimicron Technology Corp 嵌埋穿孔中介層之封裝基板及其製法
JP5412462B2 (ja) * 2011-04-19 2014-02-12 日本パーカライジング株式会社 金属材料用耐食合金コーティング膜及びその形成方法
US8829676B2 (en) 2011-06-28 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for wafer level package
US8754514B2 (en) 2011-08-10 2014-06-17 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip wafer level package
CN102394227B (zh) 2011-11-30 2013-07-10 上海华力微电子有限公司 可降低方块电阻的铜互连结构的制造方法
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US8680647B2 (en) 2011-12-29 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with passive devices and methods of forming the same
US9263839B2 (en) 2012-12-28 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for an improved fine pitch joint
US9257333B2 (en) 2013-03-11 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures and methods of forming same
US8987058B2 (en) 2013-03-12 2015-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method for wafer separation
KR20130124858A (ko) 2012-05-07 2013-11-15 삼성전자주식회사 반도체 패키지
US8703542B2 (en) 2012-05-18 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level packaging mechanisms
US9991190B2 (en) 2012-05-18 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging with interposer frame
US9196532B2 (en) 2012-06-21 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit packages and methods for forming the same
US8809996B2 (en) 2012-06-29 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package with passive devices and method of forming the same
US8865585B2 (en) 2012-07-11 2014-10-21 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming post passivation interconnects
US8987884B2 (en) 2012-08-08 2015-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. Package assembly and methods for forming the same
US9275924B2 (en) 2012-08-14 2016-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package having a recess filled with a molding compound
US8754508B2 (en) 2012-08-29 2014-06-17 Taiwan Semiconductor Manufacturing Company, Ltd. Structure to increase resistance to electromigration
US8952530B2 (en) 2012-09-14 2015-02-10 Taiwan Semiconductor Manufacturing Company, Ltd. Post passivation interconnect structures and methods for forming the same
US8772151B2 (en) 2012-09-27 2014-07-08 Taiwan Semiconductor Manufacturing Company, Ltd. Passivation scheme
US9921640B2 (en) 2012-09-28 2018-03-20 Intel Corporation Integrated voltage regulators with magnetically enhanced inductors
US8785299B2 (en) 2012-11-30 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package with a fan-out structure and method of forming the same
US8884400B2 (en) 2012-12-27 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitor in Post-Passivation structures and methods of forming the same
US8846548B2 (en) 2013-01-09 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Post-passivation interconnect structure and methods for forming the same
US8803306B1 (en) 2013-01-18 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package structure and methods for forming the same
US8778738B1 (en) 2013-02-19 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging devices and methods
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US9773732B2 (en) 2013-03-06 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for packaging pad structure
US8933551B2 (en) 2013-03-08 2015-01-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3D-packages and methods for forming the same
US9196559B2 (en) 2013-03-08 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Directly sawing wafers covered with liquid molding compound
US8987922B2 (en) 2013-03-11 2015-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for wafer level packaging
US9275925B2 (en) 2013-03-12 2016-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for an improved interconnect structure
US8877554B2 (en) 2013-03-15 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
JP5889855B2 (ja) * 2013-10-11 2016-03-22 シャープ株式会社 画像形成装置
US9281297B2 (en) 2014-03-07 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Solution for reducing poor contact in info packages
US9735134B2 (en) 2014-03-12 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with through-vias having tapered ends
US9543170B2 (en) 2014-08-22 2017-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US10236209B2 (en) * 2014-12-24 2019-03-19 Intel Corporation Passive components in vias in a stacked integrated circuit package
US9633974B2 (en) 2015-03-04 2017-04-25 Apple Inc. System in package fan out stacking architecture and process flow
US9679801B2 (en) * 2015-06-03 2017-06-13 Apple Inc. Dual molded stack TSV package
US9627365B1 (en) * 2015-11-30 2017-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-layer CoWoS structure
US10319683B2 (en) * 2017-02-08 2019-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stacked package-on-package structures
US11282761B2 (en) * 2018-11-29 2022-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of manufacturing the same
US10970439B2 (en) * 2018-11-29 2021-04-06 Taiwan Semiconductor Manufacturing Company, Ltd System on chip (SOC) current profile model for integrated voltage regulator (IVR) co-design
US11195816B2 (en) * 2019-07-23 2021-12-07 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit packages comprising a plurality of redistribution structures and methods of forming the same
US11404316B2 (en) * 2019-12-27 2022-08-02 Taiwan Semiconductor Manufacturing Co., Ltd. System, device and methods of manufacture
US11482484B2 (en) * 2020-02-27 2022-10-25 Taiwan Semiconductor Manufacturing Co., Ltd. Symmetrical substrate for semiconductor packaging

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090194864A1 (en) * 2008-02-01 2009-08-06 International Business Machines Corporation Integrated module for data processing system
US20110317387A1 (en) * 2010-06-29 2011-12-29 Qualcomm Incorporated Integrated Voltage Regulator with Embedded Passive Device(s) for a Stacked IC
US20120112352A1 (en) * 2010-11-10 2012-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit system with distributed power supply
US20140306355A1 (en) * 2013-04-15 2014-10-16 Thorsten Meyer Chip interposer, semiconductor device, and method for manufacturing a semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111599768A (zh) * 2019-02-21 2020-08-28 力成科技股份有限公司 半导体封装及其制造方法
CN111599768B (zh) * 2019-02-21 2022-12-27 力成科技股份有限公司 半导体封装及其制造方法

Also Published As

Publication number Publication date
US20200381392A1 (en) 2020-12-03
US11244924B2 (en) 2022-02-08
US20190123019A1 (en) 2019-04-25
US20170221858A1 (en) 2017-08-03
KR101917418B1 (ko) 2018-11-09
DE102016102108B4 (de) 2022-06-09
US10748870B2 (en) 2020-08-18
KR20170063324A (ko) 2017-06-08
US9627365B1 (en) 2017-04-18
TW201733068A (zh) 2017-09-16
TWI627722B (zh) 2018-06-21
CN107026153B (zh) 2019-08-02
DE102016102108A1 (de) 2017-06-01
US10163851B2 (en) 2018-12-25

Similar Documents

Publication Publication Date Title
CN107026153B (zh) 封装件
CN107180795B (zh) 包括电压调节器的集成扇出封装件及其形成方法
EP2996146B1 (en) Semiconductor package assembly
CN107068669B (zh) 半导体装置封装以及半导体封装及其制造方法
US11217546B2 (en) Embedded voltage regulator structure and method forming same
CN104377171B (zh) 具有中介层的封装件及其形成方法
US9842831B2 (en) Semiconductor package and fabrication method thereof
CN107104087A (zh) 半导体封装结构及其形成方法
US20140206142A1 (en) Flip-chip wafer level package and methods thereof
TWI591737B (zh) 半導體封裝結構
CN104517930A (zh) 半导体封装
CN102169841A (zh) 凹入的半导体基底和相关技术
KR20220068969A (ko) 패키징층 인덕터
KR102307844B1 (ko) 임베디드 전압 조정기 구조물 및 그 형성 방법
CN108447860A (zh) 半导体封装结构
CN105895623A (zh) 用于半导体封装件的衬底设计及其形成方法
CN106206557A (zh) 硅中介层
US20240071880A1 (en) Package substrate for a semiconductor device
TWI778406B (zh) 電子封裝件及其製法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant