CN107026153A - 封装件 - Google Patents
封装件 Download PDFInfo
- Publication number
- CN107026153A CN107026153A CN201611046177.0A CN201611046177A CN107026153A CN 107026153 A CN107026153 A CN 107026153A CN 201611046177 A CN201611046177 A CN 201611046177A CN 107026153 A CN107026153 A CN 107026153A
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- CN
- China
- Prior art keywords
- tube core
- voltage regulator
- integrated voltage
- encapsulating material
- regulator tube
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
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- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
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- H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
- H10K19/10—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising field-effect transistors
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Abstract
本发明的实施例提供了一种封装件,包括集成调压器(IVR)管芯,其中,IVR管芯包括位于第一IVR管芯的顶面处的金属柱。封装件还包括其中包封第一IVR管芯的第一包封材料,其中,第一包封材料具有与金属柱的顶面共面的顶面。多条再分布线位于第一包封材料和IVR管芯上方。多条再分布线电耦合至金属柱。核心芯片与多条再分布线重叠并且接合至多条再分布线。第二包封材料中包封核心芯片,其中,第一包封材料的边缘和第二包封材料的相应的边缘彼此垂直对准。***件或封装件衬底位于IVR管芯下面并且接合至IVR管芯。
Description
技术领域
本发明的实施例涉及半导体领域,更具体地涉及一种封装件。
背景技术
中央处理单元(CPU)对输入/输出(IO)和CPU消耗的功率具有较高的要求。例如,CPU可以包括多个核心并且需要消耗相当大的功率。另一方面,对提供的功率的要求也很高。例如,供电电压需要非常稳定。因此,多个调压器可以连接至同一CPU芯片以提供电源。
发明内容
本发明的实施例提供了一种封装件,包括:第一集成调压器(IVR)管芯,其中,所述第一集成调压器管芯包括:金属柱,位于所述第一集成调压器管芯的顶面处;第一包封材料,将所述第一集成调压器管芯包封在所述第一包封材料中,其中,所述第一包封材料具有与所述金属柱的顶面共面的顶面;多条再分布线,位于所述第一包封材料和所述第一集成调压器管芯上方,其中,所述多条再分布线电耦合至所述金属柱;第一核心芯片,与所述多条再分布线重叠并且接合至所述多条再分布线;第二包封材料,将所述第一核心芯片包封在所述第二包封材料中,其中,所述第一包封材料的边缘和所述第二包封材料的相应的边缘彼此垂直对准;以及***件或封装件衬底,位于所述第一集成调压器管芯下面并且接合至所述第一集成调压器管芯。
本发明的实施例还提供了一种封装件,包括:第一集成调压器(IVR)管芯和第二集成调压器管芯,每个都包括:金属柱;调压器电路,电耦合至所述金属柱;和电感器,电耦合至所述调压器电路;第一包封材料,将所述第一集成调压器管芯和所述第二集成调压器管芯包封在所述第一包封材料中,其中,所述第一包封材料具有与所述第一集成调压器管芯和所述第二集成调压器管芯中的所述金属柱的顶面共面的顶面;介电层,与所述第一集成调压器管芯、所述第二集成调压器管芯、和所述第一包封材料重叠;多条再分布线,具有位于所述介电层中的部分,其中,所述多条再分布线电耦合至所述第一集成调压器管芯和所述第二集成调压器管芯;第一中央处理单元(CPU)芯片和第二中央处理单元芯片,分别与所述第一集成调压器管芯和所述第二集成调压器管芯重叠并且分别电耦合至所述第一集成调压器管芯和所述第二集成调压器管芯;以及第二包封材料,将所述第一中央处理单元芯片和所述第二中央处理单元芯片包封在所述第二包封材料中。
本发明的实施例还提供了一种封装件,包括:第一器件管芯,包括:半导体衬底;第一贯通孔和第二贯通孔,贯穿所述半导体衬底;有源电路,位于所述半导体衬底的表面处;第一金属柱,位于所述第一器件管芯的顶面处,其中,所述第一金属柱电耦合至所述有源电路和所述第一贯通孔;以及第二金属柱,位于所述第一器件管芯的顶面处,其中,所述第二金属柱电耦合至所述第二贯通孔,并且所述第二金属柱与所述第一器件管芯中的所有有源电路电断开;第一包封材料,将所述第一器件管芯包封在所述第一包封材料中;第二器件管芯,与所述第一器件管芯重叠并且电耦合至所述第一器件管芯;以及封装件组件,位于所述第一器件管芯下面并且接合至所述第一器件管芯,其中,所述第二贯通孔和所述第二金属柱将所述封装件组件电耦合至所述第二器件管芯。
附图说明
当结合附图进行阅读时,根据下面详细的描述可以更好地理解本发明的实施例。应该强调的是,根据工业中的标准实践,对各种部件没有按比例绘制。实际上,为了清楚的讨论,各种部件的尺寸可以被任意增大或缩小。
图1至图9示出了根据一些实施例的在包括集成调压器的封装件的形成中的中间阶段的截面图。
图10示出了根据一些实施例的包括集成调压器的封装件的截面图。
图11示出了根据一些实施例的用于形成封装件的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件形成为直接接触的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实例中重复参考标号和/或字母。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为便于描述,在此可以使用诸如“在…下面”、“在…下方”、“下部”、“在…上面”、“上部”等的空间相对术语,以便于描述如图所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),而在此使用的空间相对描述符可以同样地作相应的解释。
根据各个示例性实施例提供了一种多层级封装件及其形成方法。可以使用衬底上晶圆上芯片(Chip-on-Wafer-on-Substrate,CoWoS)工艺形成多层级封装件。示出了形成该封装件的中间阶段。讨论了一些实施例的一些变型。贯穿各个视图和说明性实施例,相同的参考标号用于表示相同的元件。
图1至图9示出了根据一些实施例的在多层级封装件的形成中的中间阶段的截面图。图1至图9中示出的步骤也在图11中示出的工艺流程200中示意性地示出。
参照图1,提供了载体20,并且在载体20上方设置粘合层22。载体20可以是空白玻璃载体、空白陶瓷载体、有机载体等,并且可以具有圆形顶视图形状的半导体晶圆的形状。有时,载体20被称为载体晶圆。例如,粘合层22可以由光热转换(LTHC)材料形成,并且也可以使用其他类型的粘合剂。根据本发明的一些实施例,粘合层22在光的热量下能够分解,并且因此能够从形成在其上的结构释放载体20。
参照图2,在粘合层22上方放置器件管芯24(包括24A、24B、24C、24D和24E)。相应的步骤示出为图11中示出的工艺流程中的步骤202。贯穿说明书,器件管芯24还被称为层级1管芯。应该理解,在晶圆级下实施随后讨论的工艺步骤。因此,具有与包括器件管芯24A、24B、24C、24D、和24E的管芯组相同的多个管芯组。多个管芯组可以布置为包括多行和多列的阵列。器件管芯24可以彼此相同或彼此不同。例如,器件管芯24A、24B、24C、和24D可以彼此相同,并且不同于器件管芯24E。
根据本发明的一些实施例,器件管芯24为包括用于为上面的管芯调节电压供给的调压器的集成调压器(IVR)管芯。IVR中的电路示意性示出为在半导体衬底28上形成的26。根据本发明的可选实施例,器件管芯24包括逻辑管芯或诸如静态随机存取存储器(SRAM)管芯、动态随机存取存储器(DRAM)管芯等的存储器管芯。
IVR电路26可以包括模拟泵电路(pump circuit)、数字控制块、以及用于调节电压的其它电路。例如,模拟泵电路用于将电流泵入上面的逻辑管芯。数字控制块具有确定模拟电路何时需要泵电流(pump current)的功能。当被用于先进的IVR时,数字控制块可以确定需要开启模拟泵的多少相,从而优化至上面的器件管芯的电流输出。此外,器件管芯24还可以包括电耦合至模拟泵电路和数字控制块的电感器30。IVR电路还可以包括位于器件管芯52(包括52A、52B、和52C,图9)中的电压下降检测电路。电压下降检测电路由上面的器件管芯52(图8)使用以检测电压下降、数字化、并且反馈至器件管芯24中的模拟泵电路。
根据本发明的一些实施例,器件管芯24是独立IVR管芯,其中,除了由调压器电路使用的那些,没有其他逻辑电路设置在器件管芯24中。根据可选实施例,一些逻辑电路或存储器电路与调压器电路一起设置在器件管芯24内部。
器件管芯24包括半导体衬底28,其可以是硅衬底、硅碳衬底、III-V族化合物半导体衬底等。器件管芯24还包括互连结构32。根据本发明的一些实施例,互连结构32包括多个介电层34、以及在介电层34中的金属线和通孔(未示出)。介电层34可以包括可以由低k介电材料形成的金属间介电(IMD)层,例如,低k介电材料的介电常数(k值)低于3.5、低于约3.0、或低于约2.5。此外,靠近器件管芯24的顶面,可以具有诸如氮化硅层、氧化硅层、未掺杂的硅酸盐玻璃(USG)层、和/或聚合物层的非低k钝化层。此外,在表面介电层34中的金属柱40(包括40A和40B)位于互连结构32的表面处。金属柱40可以是含铜焊盘、含铝焊盘等。根据一些实施例,介电层34的顶部的一个的顶面与金属柱40的顶面共面。根据一些实施例,表面介电层34的一部分覆盖金属柱40。表面介电层34可以是聚合物层,例如,其可以由聚苯并恶唑(PBO)形成。
电感器30嵌入在互连结构32中,且还是调压器电路的部分。电感器30可以使用连接的金属线和通孔形成以具有线圈的形状。因此,根据本发明的一些实施例,电感器30是集成在与IVR电路相同的芯片中的芯片上电感器。根据本发明的可选实施例,电感器30形成在IVR管芯24的外部作为独立电感器。
器件管芯24还包括贯通孔(可选地称为硅贯通孔或衬底贯通孔)36(包括36A和36B)。应该理解,尽管贯通孔36示出为贯穿图2中的半导体衬底,但是在载体20上方放置器件管芯24时,贯通孔36可以不延伸至半导体衬底28的底面处。此外,贯通孔36延伸至介于半导体衬底28的顶面和底面之间的中间平面,并且如图7所示,贯通孔36的底端将在随后的背面研磨步骤中被暴露。每个贯通孔36都通过环绕相应的贯通孔36的介电层(未示出)与相应的半导体衬底28电绝缘。
贯通孔36A和36B用于将半导体衬底28上方的导电部件连接至相应的半导体衬底28下面的导电部件。贯通孔36B电耦合至相应的器件管芯24内部得器件(诸如IVR电路、导线、电感器30等)。贯通孔36B还可以电耦合至金属柱40B。另一方面,器件管芯24中的贯通孔36A单独地用于将相应的器件管芯24上方的导电部件(诸如图8中的器件管芯52)连接至器件管芯24下面的导电部件(诸如图8中的***件70中的金属焊盘)。贯通孔36A不连接至器件管芯24内部的任何其它电路(包括诸如晶体管和二极管的有源器件和诸如电容器、电感器、电阻器等的无源器件)。因此,贯通孔36A用于互连器件管芯24外部的部件,且不用于至器件管芯24内部的电路的内连接。或者说,贯通孔36A具有与模制贯通孔(未示出)相同的功能,而模制贯通孔可以设置在器件管芯24的外部且贯穿包封材料44(图8)。然而,在器件管芯24内部形成贯通孔36A没有额外的制造成本,这是因为与模制贯通孔不同,贯通孔36A和贯通孔36B同时形成。此外,由于贯通孔36A使用用于形成器件管芯的技术形成,所以贯通孔36可以具有比模制贯通孔更高的密度和更小的尺寸,并且贯通孔36A的总数可以高于模制贯通孔。
如图2所示,每个贯通孔36A都连接至将相应的贯通孔36A电耦合至金属柱40A的导电路径38中的一个。导电路径38可以是没有分支/分叉的单布线路径,且不连接至相应的器件管芯24中的任何其它金属柱40B、电感器、电阻器、电容器、晶体管、二极管等。因此,尽管位于器件管芯24中,但是贯通孔36A不涉及与电压调节有关的电压/信号传送。此外,尽管导电路径38被示出为直的路径,但是它们可以包括水平金属线。使用贯通孔36A(和导电路径38)以替代模制贯通孔的有益特征在与,导电路径38具有再布线功能,金属柱40A不必重叠相应的贯通孔36A,而模制贯通孔是直的且垂直,以及不能被再布线。
参照图3,在器件管芯24上包封包封材料44。相应的步骤示出为图11中示出的工艺流程中的步骤204。包封材料44被分配,并且然后例如,在热固化工艺中被固化。包封材料44填充器件管芯24之间的间隙,并且可以与粘合层22接触。包封材料44可以包括模塑料、模制底部填充物、环氧树脂和/或树脂。在包封工艺之后,包封材料44的顶面高于金属柱40和贯通孔14的顶端。
接下来,实施诸如化学机械抛光(CMP)步骤或研磨步骤的平坦化步骤以平坦化包封材料44,直到暴露器件管芯24的金属柱40。相应的步骤示出为图11中示出的工艺流程中的步骤206。图3中示出生成的结构。由于平坦化,所以金属柱40的顶面与包封材料44的顶面基本齐平(共面)。
参考图4,在包封材料44和器件管芯24上方形成介电层46和相应的再分布线(RDL)48的一层或多层。相应的步骤示出为图11中示出的工艺流程中的步骤208。根据本发明的一些实施例,介电层46由诸如PBO、聚酰亚胺等的聚合物形成。根据本发明的可选实施例,介电层46由诸如氮化硅、氧化硅、氮氧化硅等的无机介电材料形成。
RDL 48形成为电耦合至金属柱40。RDL 48可以包括金属迹线(金属线)和通孔,该通孔位于相应的金属迹线下面并且连接至相应的金属迹线。根据本发明的一些实施例,通过镀敷工艺形成RDL 48,其中,每个RDL 48都包括晶种层(未示出)和位于晶种层上方的镀敷的金属材料。晶种层和镀敷的金属材料可以由相同材料或不同材料形成。
在RDL 48的形成期间,图案化介电层46以形成通孔开口(由RDL 48占据),并且上层RDL 48延伸至通孔开口内以接触下层RDL 48或金属柱40。此外,一些RDL 48可以电互连器件管芯24。可以图案化(例如,使用激光)顶部介电层46以在其中形成开口50,从而暴露RDL 48中的一些金属焊盘。
图5示出了器件管芯52(包括52A、52B、和52C)接合至RDL 48中的暴露的金属焊盘上。相应的步骤示出为图11中示出的工艺流程中的步骤210。贯穿说明书,器件管芯52还称为层级2管芯。器件管芯52可以通过焊料区56接合至金属焊盘48。每个器件管芯52都可以包括使其背面朝上的半导体衬底58。器件管芯52还包括位于半导体衬底58的正面(朝下的表面)处的集成电路器件54(诸如包括例如晶体管的有源器件,未示出)。器件管芯52A和52B可以包括诸如中央处理单元(CPU)管芯、图像处理单元(GPU)管芯、移动应用管芯等的逻辑管芯。器件管芯52A和52B可以彼此相同。器件管芯52C可以是用于器件管芯52A和52B的输入/输出的(高速)输入/输出(IO)管芯。使用虚线示出的RDL 60表示器件管芯52A和52B至IO管芯52C的电连接。
根据其中器件管芯52A和52B是CPU管芯的一些实施例,集成电路54可以包括多个功能电路,诸如控制单元、存储器组件、时钟电路、焊盘收发器电路、逻辑门单元库等。控制单元控制CPU的数据路径。存储器组件包括寄存器文件、高速缓冲存储器(SRAM单元)等。时钟电路包括时钟驱动器、锁相环(PLL)、时钟分配网络等。使用逻辑门单元库以执行逻辑操作。
器件管芯52A电连接至器件管芯24A和24B。此外,器件管芯24A和24B调节电压供给以用于器件管芯52A。器件管芯52B连接至器件管芯24C和24D。此外,器件管芯24C和24D调节电压供给以用于器件管芯52B。器件管芯52A和器件管芯52B中的每一个都可以包括多个核心,并且器件管芯52A和器件管芯52B可选地称为核心芯片。可以是IO芯片的器件管芯52C连接至器件管芯24E,器件管芯24E调节电压以用于IO芯片52C。根据本发明的一些实施例,器件管芯52A与器件管芯24A和24B完全重叠。器件管芯52A还可横向地延伸超过器件管芯24A和24B的边缘。器件管芯52B与器件管芯24C和24D完全重叠。器件管芯52B还可横向地延伸超过器件管芯24C和24D的边缘。
参照图6,在器件管芯52上包封包封材料64。相应的步骤示出为图11中示出的工艺流程中的步骤212。包封材料64可以包括模塑料、模制底部填充物、环氧树脂或树脂。包封材料64的底面物理接触顶部介电层46的顶面。在分配之后,例如,在热固化工艺中固化包封材料64。根据本发明的一些实施例,实施平坦化步骤以平坦化包封材料64直到包封材料64的顶面与器件管芯52的顶面共面。相应的步骤示出为图11中示出的工艺流程中的步骤214。根据本发明的可选实施例,不实施平坦化,且在最终结构中,包封材料64包括与器件管芯52重叠的一些部分。贯穿说明书,层22上面的结构称为封装件66,封装件66包括多个封装件,每个封装件都包括器件管芯24A、24B、24C、24D、24E、以及52A、52B、和52C。
接下来,封装件66从载体20脱离。相应的步骤示出为图11中示出的工艺流程中的步骤216。图7中示出生成的结构。例如,通过将UV光或激光投射在粘合层22上实施封装件66从载体20的脱离。例如,当粘合层22由LTHC形成时,由UV光或激光生成的热导致LTHC分解,并且因此载体20从封装件66分离。实施背面研磨以研磨器件管芯24和包封材料44的底部部分。实施背面研磨直到暴露贯通孔36A和36B的底端。根据一些实施例,在器件管芯24的底部处形成金属焊盘和/或金属迹线(未示出)以电连接至贯通孔36A和36B。根据可选实施例,在器件管芯24的底部处没有形成金属焊盘和/或金属迹线。
在随后的步骤中,实施管芯锯切以将封装件66锯切为分立的封装件68,分立的封装件68彼此相同,分立的封装件68中的一个示出在图8中。相应的步骤在图11所示的工艺流程图中示出为步骤216。
由于封装件68是从封装件68锯切的,所以包封材料44的边缘与包封材料64的相应边缘垂直对准。此外,包封材料44的边缘还与介电层46的相应边缘垂直对准。
接下来,参考图8,封装件68接合至***件70。根据一些示例性实施例,通过焊料区71实施接合。根据可选实施例,可以使用诸如混合接合的其它接合方法。相应的步骤示出为图11中示出的工艺流程中的步骤218。接合可以是晶圆上芯片(CoW)接合,其中,多个封装件(芯片)68接合至同一***件晶圆,该***件晶圆包括与示出的***件70相同的多个***件。根据本发明的一些实施例,基本与图10中的互连结构84相同的互连结构(未示出)可以形成在封装件68的底部处,其中,互连结构中的RDL电耦合至贯通孔36A和36B。***件70可以包括半导体衬底72(其可以是硅衬底)和半导体衬底72上方的互连结构74。在互连结构74中形成金属线和通孔76。在半导体衬底72中形成贯通孔78。***件70没有诸如晶体管和二极管的有源器件。***件70可以没有、或可以包括诸如电阻器、电感器、电容器等的无源器件(未示出)。可以在封装件68和***件70之间分配底部填充物73。然后,***件晶圆可以被锯开成多个封装件,每个封装件都包括***件70和上面的器件管芯24和52。
参照图9,例如,***件70通过焊料区82接合至封装件衬底80。相应的步骤示出为图11中示出的工艺流程中的步骤220。封装件衬底80可以是层压衬底(少核芯)或可以具有核心。封装件衬底80中的导电迹线和/或核心(未示出)电连接至焊料区82。封装件衬底80可以具有比上面的***件70的顶面面积大的顶面面积。
图10示出了根据可选实施例的封装件。除了没有使用***件,这些实施例类似于图9中的实施例,并且封装件68直接接合至封装件衬底80。根据本发明的一些实施例,封装件68包括在器件管芯24和包封材料44的底面处形成的互连结构84。可以使用与用于形成介电层46和RDL 48基本相同的方法和材料形成互连结构,并且因此在此不再赘述。
本发明的实施例具有一些有利的特征。如图9和图10所示,器件管芯52A可以具有比器件管芯24A和24B的总顶面面积大的顶面面积。相应地,可以在相应的核心芯片52A下面直接放置器件管芯24A和24B,且器件管芯24A、24B、以及52A的总顶面面积基本上是器件管芯52A的顶面面积。通过将IVR管芯(诸如24A和24B)直接放置在其对应的核心器件管芯(诸如52A)下面,从核心器件管芯至其调压器的距离被最小化。相似地,通过将IVR管芯24E直接放置在器件管芯52C下面,从器件管芯52C至IVR管芯24E中的该器件管芯的调压器的距离被最小化。因此提高了电源效率。作为对照,如果IVR管芯被放置在核心芯片的附近,因为IVR管芯更靠近核心芯片中的一些核心且远离核心芯片中的其它核心,所以布局不平衡。通过将IVR管芯24直接放置在IVR管芯24服务的核心芯片下面,使布局平衡。
此外,由于器件管芯24较小,所以模制贯通孔可以由贯通孔36A替代,否则,模制贯通孔将被形成(如果不使用本发明的实施例)以将***件70/封装件衬底80连接至器件管芯52。这消除了用于形成模制贯通孔的成本,同时没有用于形成贯通孔36A的产生成本(因为贯通孔36A与贯通孔36B同时形成)。此外,IVR管芯24在它们的互连结构中通常具有低密度的金属线和通孔。因此,IVR管芯的互连结构可以用于形成嵌入式电感器。
根据本发明的一些实施例,一种封装件包括IVR管芯,其中,IVR管芯包括位于第一IVR管芯的顶面处的金属柱。封装件还包括将第一IVR管芯包封在其中的第一包封材料,其中,第一包封材料具有与金属柱的顶面共面的顶面。多条再分布线位于第一包封材料和IVR管芯上方。多条再分布线电耦合至金属柱。核心芯片与多条再分布线重叠且接合至多条再分布线。第二包封材料将核心芯片包封在其中,其中,第一包封材料的边缘和第二包封材料的相应的边缘彼此垂直对准。***件或封装件衬底位于IVR管芯下面且接合至IVR管芯。
根据本发明的一些实施例,一种封装件包括第一IVR管芯和第二IVR管芯,每个IVR管芯都包括金属柱、电耦合至金属柱的调压器电路、以及电耦合至调压器电路的电感器。第一包封材料将第一IVR管芯和第二IVR管芯包封在其中。第一包封材料具有与位于第一IVR管芯和第二IVR管芯中的金属柱的顶面共面的顶面。介电层与第一IVR管芯、第二IVR管芯、和第一包封材料重叠。多条再分布线包括位于介电层中的部分。多条再分布线电耦合至第一IVR管芯和第二IVR管芯。第一CPU芯片和第二CPU芯片分别与第一IVR管芯和第二IVR管芯重叠且分别电耦合至第一IVR管芯和第二IVR管芯。第二包封材料将第一CPU芯片和第二CPU芯片包封在其中。
根据本发明的一些实施例,一种封装件包括:第一器件管芯,第一器件管芯包括半导体衬底、贯穿半导体衬底的第一贯通孔和第二贯通孔;半导体衬底的表面处的有源电路;第一器件管芯的顶面处的第一金属柱;以及第一器件管芯的顶面处的第二金属柱。第一金属柱电耦合至有源电路和第一贯通孔。第二金属柱电耦合至第二贯通孔,且与第一器件管芯中的所有有源电路电断开。封装件还包括将第一器件管芯包封在其中的第一包封材料,并且第二器件管芯与第一器件管芯重叠且电耦合至第一器件管芯。封装件组件位于器件管芯下面且接合至器件管芯。第二贯通孔和第二金属柱将封装件组件电耦合至第二器件管芯。
本发明的实施例提供了一种封装件,包括:第一集成调压器(IVR)管芯,其中,所述第一集成调压器管芯包括:金属柱,位于所述第一集成调压器管芯的顶面处;第一包封材料,将所述第一集成调压器管芯包封在所述第一包封材料中,其中,所述第一包封材料具有与所述金属柱的顶面共面的顶面;多条再分布线,位于所述第一包封材料和所述第一集成调压器管芯上方,其中,所述多条再分布线电耦合至所述金属柱;第一核心芯片,与所述多条再分布线重叠并且接合至所述多条再分布线;第二包封材料,将所述第一核心芯片包封在所述第二包封材料中,其中,所述第一包封材料的边缘和所述第二包封材料的相应的边缘彼此垂直对准;以及***件或封装件衬底,位于所述第一集成调压器管芯下面并且接合至所述第一集成调压器管芯。
根据本发明的一个实施例,其中,所述第一集成调压器管芯包括:半导体衬底;以及贯通孔,位于所述半导体衬底中,其中,所述贯通孔将所述第一核心芯片电耦合至所述***件或所述封装件衬底,而没有电耦合至所述第一集成调压器管芯中的电路。
根据本发明的一个实施例,其中,所述第一集成调压器管芯包括:半导体衬底;互连结构,位于所述半导体衬底上面;以及内置电感器,位于所述互连结构中。
根据本发明的一个实施例,封装件还包括与所述第一集成调压器管芯相同的第二集成调压器管芯,所述第二集成调压器管芯包封在所述第一包封材料中,其中,所述第二集成调压器管芯与所述第一核心芯片重叠并且电耦合至所述第一核心芯片。
根据本发明的一个实施例,封装件还包括:第三集成调压器管芯,包封在所述第一包封材料中;以及输入/输出管芯,包封在所述第二包封材料中,其中,所述输入/输出管芯与所述第三集成调压器管芯重叠并且电耦合至所述第三集成调压器管芯。
根据本发明的一个实施例,封装件还包括:第四集成调压器管芯和第五集成调压器管芯,包封在所述第一包封材料中,其中,所述第四集成调压器管芯和所述第五集成调压器管芯与所述第一集成调压器管芯相同;以及第二核心芯片,与所述第四集成调压器管芯和所述第五集成调压器管芯重叠并且电耦合至所述第四集成调压器管芯和所述第五集成调压器管芯。
根据本发明的一个实施例,其中,所述第一集成调压器管芯包括半导体衬底,所述半导体衬底的底面与所述第一包封材料的底面共面。
根据本发明的一个实施例,其中,所述***件接合至所述第一集成调压器管芯,以及所述***件横向地延伸超过所述第一包封材料的所述边缘。
根据本发明的一个实施例,其中,所述***件包括:附加的半导体衬底;以及附加的贯通孔,贯穿所述附加的半导体衬底。
本发明的实施例还提供了一种封装件,包括:第一集成调压器(IVR)管芯和第二集成调压器管芯,每个都包括:金属柱;调压器电路,电耦合至所述金属柱;和电感器,电耦合至所述调压器电路;第一包封材料,将所述第一集成调压器管芯和所述第二集成调压器管芯包封在所述第一包封材料中,其中,所述第一包封材料具有与所述第一集成调压器管芯和所述第二集成调压器管芯中的所述金属柱的顶面共面的顶面;介电层,与所述第一集成调压器管芯、所述第二集成调压器管芯、和所述第一包封材料重叠;多条再分布线,具有位于所述介电层中的部分,其中,所述多条再分布线电耦合至所述第一集成调压器管芯和所述第二集成调压器管芯;第一中央处理单元(CPU)芯片和第二中央处理单元芯片,分别与所述第一集成调压器管芯和所述第二集成调压器管芯重叠并且分别电耦合至所述第一集成调压器管芯和所述第二集成调压器管芯;以及第二包封材料,将所述第一中央处理单元芯片和所述第二中央处理单元芯片包封在所述第二包封材料中。
根据本发明的一个实施例,其中,所述第一集成调压器管芯和所述第二集成调压器管芯彼此相同,并且所述第一中央处理单元芯片和所述第二中央处理单元芯片彼此相同。
根据本发明的一个实施例,其中,所述第一包封材料的边缘与所述第二包封材料的相应的边缘垂直对准。
根据本发明的一个实施例,封装件还包括:***件或封装件衬底,位于所述第一集成调压器管芯和所述第二集成调压器管芯下面并且接合至所述第一集成调压器管芯和所述第二集成调压器管芯。
根据本发明的一个实施例,封装件还包括:第三集成调压器管芯,包封在所述第一包封材料中;以及输入/输出管芯,包封在所述第二包封材料中,其中,所述输入/输出管芯与所述第三集成调压器管芯重叠并且电耦合至所述第三集成调压器管芯。
本发明的实施例还提供了一种封装件,包括:第一器件管芯,包括:半导体衬底;第一贯通孔和第二贯通孔,贯穿所述半导体衬底;有源电路,位于所述半导体衬底的表面处;第一金属柱,位于所述第一器件管芯的顶面处,其中,所述第一金属柱电耦合至所述有源电路和所述第一贯通孔;以及第二金属柱,位于所述第一器件管芯的顶面处,其中,所述第二金属柱电耦合至所述第二贯通孔,并且所述第二金属柱与所述第一器件管芯中的所有有源电路电断开;第一包封材料,将所述第一器件管芯包封在所述第一包封材料中;第二器件管芯,与所述第一器件管芯重叠并且电耦合至所述第一器件管芯;以及封装件组件,位于所述第一器件管芯下面并且接合至所述第一器件管芯,其中,所述第二贯通孔和所述第二金属柱将所述封装件组件电耦合至所述第二器件管芯。
根据本发明的一个实施例,其中,所述第一器件管芯包括集成调压器(IVR)管芯,所述集成调压器管芯中包括集成调压器电路和电感器,以及所述第二器件管芯包括中央处理单元(CPU)管芯。
根据本发明的一个实施例,封装件还包括与所述第一集成调压器管芯相同的第二集成调压器管芯,其中,所述第二集成调压器管芯与所述第二器件管芯重叠并且电耦合至所述第二器件管芯。
根据本发明的一个实施例,封装件还包括:多条再分布线,位于所述第一包封材料和所述第一器件管芯上方,其中,所述多条再分布线电耦合至所述第一金属柱和所述第二金属柱;以及第二包封材料,将所述第二器件管芯包封在所述第二包封材料中,其中,所述第一包封材料的边缘和所述第二包封材料的相应的边缘彼此垂直对准。
根据本发明的一个实施例,封装件还包括:多个介电层,所述多条再分布线位于所述多个介电层中;以及焊料区,延伸至所述多个介电层的顶部的一个介电层中。
根据本发明的一个实施例,其中,所述第二金属柱未电耦合至所述第一器件管芯中的任何无源器件。
上面概述了若干实施例的部件、使得本领域技术人员可以更好地理解本发明的实施例。本领域技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实现与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围、并且在不背离本发明的精神和范围的情况下,在此他们可以做出多种变化、替换以及改变。
Claims (10)
1.一种封装件,包括:
第一集成调压器(IVR)管芯,其中,所述第一集成调压器管芯包括:
金属柱,位于所述第一集成调压器管芯的顶面处;
第一包封材料,将所述第一集成调压器管芯包封在所述第一包封材料中,其中,所述第一包封材料具有与所述金属柱的顶面共面的顶面;
多条再分布线,位于所述第一包封材料和所述第一集成调压器管芯上方,其中,所述多条再分布线电耦合至所述金属柱;
第一核心芯片,与所述多条再分布线重叠并且接合至所述多条再分布线;
第二包封材料,将所述第一核心芯片包封在所述第二包封材料中,其中,所述第一包封材料的边缘和所述第二包封材料的相应的边缘彼此垂直对准;以及
***件或封装件衬底,位于所述第一集成调压器管芯下面并且接合至所述第一集成调压器管芯。
2.根据权利要求1所述的封装件,其中,所述第一集成调压器管芯包括:
半导体衬底;以及
贯通孔,位于所述半导体衬底中,其中,所述贯通孔将所述第一核心芯片电耦合至所述***件或所述封装件衬底,而没有电耦合至所述第一集成调压器管芯中的电路。
3.根据权利要求1所述的封装件,其中,所述第一集成调压器管芯包括:
半导体衬底;
互连结构,位于所述半导体衬底上面;以及
内置电感器,位于所述互连结构中。
4.根据权利要求1所述的封装件,还包括与所述第一集成调压器管芯相同的第二集成调压器管芯,所述第二集成调压器管芯包封在所述第一包封材料中,其中,所述第二集成调压器管芯与所述第一核心芯片重叠并且电耦合至所述第一核心芯片。
5.根据权利要求1所述的封装件,还包括:
第三集成调压器管芯,包封在所述第一包封材料中;以及
输入/输出管芯,包封在所述第二包封材料中,其中,所述输入/输出管芯与所述第三集成调压器管芯重叠并且电耦合至所述第三集成调压器管芯。
6.根据权利要求1所述的封装件,还包括:
第四集成调压器管芯和第五集成调压器管芯,包封在所述第一包封材料中,其中,所述第四集成调压器管芯和所述第五集成调压器管芯与所述第一集成调压器管芯相同;以及
第二核心芯片,与所述第四集成调压器管芯和所述第五集成调压器管芯重叠并且电耦合至所述第四集成调压器管芯和所述第五集成调压器管芯。
7.根据权利要求1所述的封装件,其中,所述第一集成调压器管芯包括半导体衬底,所述半导体衬底的底面与所述第一包封材料的底面共面。
8.根据权利要求1所述的封装件,其中,所述***件接合至所述第一集成调压器管芯,以及所述***件横向地延伸超过所述第一包封材料的所述边缘。
9.一种封装件,包括:
第一集成调压器(IVR)管芯和第二集成调压器管芯,每个都包括:
金属柱;
调压器电路,电耦合至所述金属柱;和
电感器,电耦合至所述调压器电路;
第一包封材料,将所述第一集成调压器管芯和所述第二集成调压器管芯包封在所述第一包封材料中,其中,所述第一包封材料具有与所述第一集成调压器管芯和所述第二集成调压器管芯中的所述金属柱的顶面共面的顶面;
介电层,与所述第一集成调压器管芯、所述第二集成调压器管芯、和所述第一包封材料重叠;
多条再分布线,具有位于所述介电层中的部分,其中,所述多条再分布线电耦合至所述第一集成调压器管芯和所述第二集成调压器管芯;
第一中央处理单元(CPU)芯片和第二中央处理单元芯片,分别与所述第一集成调压器管芯和所述第二集成调压器管芯重叠并且分别电耦合至所述第一集成调压器管芯和所述第二集成调压器管芯;以及
第二包封材料,将所述第一中央处理单元芯片和所述第二中央处理单元芯片包封在所述第二包封材料中。
10.一种封装件,包括:
第一器件管芯,包括:
半导体衬底;
第一贯通孔和第二贯通孔,贯穿所述半导体衬底;
有源电路,位于所述半导体衬底的表面处;
第一金属柱,位于所述第一器件管芯的顶面处,其中,所述第一金属柱电耦合至所述有源电路和所述第一贯通孔;以及
第二金属柱,位于所述第一器件管芯的顶面处,其中,所述第二金属柱电耦合至所述第二贯通孔,并且所述第二金属柱与所述第一器件管芯中的所有有源电路电断开;
第一包封材料,将所述第一器件管芯包封在所述第一包封材料中;
第二器件管芯,与所述第一器件管芯重叠并且电耦合至所述第一器件管芯;以及
封装件组件,位于所述第一器件管芯下面并且接合至所述第一器件管芯,其中,所述第二贯通孔和所述第二金属柱将所述封装件组件电耦合至所述第二器件管芯。
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US11244924B2 (en) | 2022-02-08 |
US20190123019A1 (en) | 2019-04-25 |
US20170221858A1 (en) | 2017-08-03 |
KR101917418B1 (ko) | 2018-11-09 |
DE102016102108B4 (de) | 2022-06-09 |
US10748870B2 (en) | 2020-08-18 |
KR20170063324A (ko) | 2017-06-08 |
US9627365B1 (en) | 2017-04-18 |
TW201733068A (zh) | 2017-09-16 |
TWI627722B (zh) | 2018-06-21 |
CN107026153B (zh) | 2019-08-02 |
DE102016102108A1 (de) | 2017-06-01 |
US10163851B2 (en) | 2018-12-25 |
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