CN105590916A - 晶片封装体及其制造方法 - Google Patents

晶片封装体及其制造方法 Download PDF

Info

Publication number
CN105590916A
CN105590916A CN201510450190.1A CN201510450190A CN105590916A CN 105590916 A CN105590916 A CN 105590916A CN 201510450190 A CN201510450190 A CN 201510450190A CN 105590916 A CN105590916 A CN 105590916A
Authority
CN
China
Prior art keywords
wafer
layer
perforation
weld pad
insulating barrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201510450190.1A
Other languages
English (en)
Other versions
CN105590916B (zh
Inventor
刘建宏
温英男
李士仪
姚皓然
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
XinTec Inc
Original Assignee
XinTec Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by XinTec Inc filed Critical XinTec Inc
Publication of CN105590916A publication Critical patent/CN105590916A/zh
Application granted granted Critical
Publication of CN105590916B publication Critical patent/CN105590916B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/2633—Bombardment with radiation with high-energy radiation for etching, e.g. sputteretching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/43—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02311—Additive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02371—Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H01L2224/06182—On opposite sides of the body with specially adapted redistribution layers [RDL]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/14104—Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body
    • H01L2224/1411—Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body the bump connectors being bonded to at least one common bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/43—Manufacturing methods
    • H01L2224/432—Mechanical processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4502—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

一种晶片封装体及其制造方法，该晶片封装体包含晶片、激光阻档件、绝缘层、重布线层、阻隔层与导电结构。晶片具有焊垫、及相对的第一表面与第二表面。焊垫位于第一表面上。第二表面具有第一穿孔，使焊垫从第一穿孔裸露。激光阻档件位于焊垫上。绝缘层位于第二表面上与第一穿孔中。绝缘层具有相对第二表面的第三表面。绝缘层与焊垫共同具有第二穿孔，使激光阻档件从第二穿孔裸露。重布线层位于第三表面上、第二穿孔的壁面上与第二穿孔中的激光阻档件上。阻隔层位于第三表面上与重布线层上。导电结构位于重布线层上，使导电结构电性连接焊垫。本发明不仅能节省制程的时间与机台的成本，还可提升晶片封装体侦测时的准确度。

Description

晶片封装体及其制造方法
技术领域
本发明有关一种晶片封装体及其制造方法。
背景技术
指纹感测装置(fingerprintsensor)或射频感测装置(RFsensor)需利用平坦的感测面来侦测信号。若感测面不平整，会影响感测装置侦测时的准确度。举例来说，当指头按压于指纹感测装置的感测面时，若感测面不平整，将难以侦测到完整的指纹。
此外，上述的感测装置在制作时，会先于晶圆中形成硅穿孔(ThroughSiliconVia；TSV)，使焊垫从硅穿孔裸露。接着，会以化学气相沉积法(ChemicalVaporDeposition；CVD)在焊垫上与硅穿孔的壁面上形成绝缘层。之后，还需通过图案化制程于焊垫上的绝缘层形成开口。一般而言图案化制程包含曝光、显影与蚀刻制程。在后续制程中，重布线层便可形成在绝缘层上并电性连接绝缘层开口中的焊垫。
然而，化学气相沉积与图案化制程均需耗费大量的制程时间与机台的成本。
发明内容
本发明的一技术态样为一种晶片封装体。
根据本发明一实施方式，一种晶片封装体包含晶片、激光阻档件、绝缘层、重布线层、阻隔层与导电结构。晶片具有焊垫、及相对的第一表面与第二表面。焊垫位于第一表面上。第二表面具有第一穿孔，使焊垫从第一穿孔裸露。激光阻档件位于焊垫上。绝缘层位于第二表面上与第一穿孔中。绝缘层具有相对第二表面的第三表面。绝缘层与焊垫共同具有第二穿孔，使激光阻档件从第二穿孔裸露。重布线层位于绝缘层的第三表面上、第二穿孔的壁面上与第二穿孔中的激光阻档件上。阻隔层位于第三表面上与重布线层上。阻隔层具有开口，使重布线层从开口裸露。导电结构位于开口中的重布线层上，使导电结构电性连接焊垫。
本发明的一技术态样为一种晶片封装体的制造方法。
根据本发明一实施方式，一种晶片封装体的制造方法包含下列步骤。(a)提供晶圆与激光阻档件，其中晶圆具有焊垫、及相对的第一表面与第二表面，且焊垫位于第一表面，激光阻档件位于焊垫上。(b)于晶圆的第一表面暂时接合支撑件。(c)在晶圆的第二表面中形成第一穿孔，使焊垫从第一穿孔裸露。(d)于晶圆的第二表面上与第一穿孔中形成绝缘层，其中绝缘层具有相对第二表面的第三表面。(e)使用激光贯穿绝缘层与焊垫以形成第二穿孔，其中激光由激光阻档件阻挡，且激光阻档件从第二穿孔裸露。(f)于绝缘层的第三表面上、第二穿孔的壁面上与第二穿孔中的激光阻档件上电镀重布线层。
在本发明上述实施方式中，由于激光阻档件位于焊垫上，因此当激光贯穿绝缘层与焊垫时，激光可由激光阻档件阻挡，并于绝缘层与焊垫中形成裸露激光阻档件的第二穿孔。待第二穿孔形成后，便可电镀重布线层于绝缘层的第三表面上、第二穿孔的壁面上与第二穿孔中的激光阻档件上。其中，第二穿孔的壁面包含焊垫的表面与绝缘层的表面，使得重布线层可电性连接焊垫。本发明的晶片封装体及其制造方法可省略已知化学气相沉积绝缘层与图案化绝缘层的制程，能节省制程的时间与机台的成本。此外，晶片的第一表面未经额外的加工，因此平坦性佳，可提升晶片封装体侦测时的准确度。
附图说明
图1绘示根据本发明一实施方式的晶片封装体的俯视图。
图2绘示图1的晶片封装体沿线段2-2的剖面图。
图3绘示图2的晶片封装体的局部放大图。
图4绘示根据本发明一实施方式的晶片封装体的制造方法的流程图。
图5绘示根据本发明一实施方式的晶圆与激光阻档件的剖面图。
图6绘示图5的晶圆接合支撑件后的剖面图。
图7绘示图6的晶圆形成第一穿孔后的剖面图。
图8绘示图7的晶圆的第二表面上与第一穿孔中形成绝缘层后的剖面图。
图9绘示图8的绝缘层与焊垫中形成第二穿孔后的剖面图。
图10绘示图9的绝缘层的第三表面、第二穿孔的壁面与激光阻档件上形成重布线层后的剖面图。
图11绘示图10的绝缘层与重布线层上形成阻隔层后的剖面图。
图12绘示图11的重布线层上形成导电结构后的剖面图。
其中，附图中符号的简单说明如下：
100：晶片封装体
110：晶片
110a：晶圆
111：第一表面
112：焊垫
113：第二表面
114：第一穿孔
115：表面
120：激光阻档件
122：第四表面
140：绝缘层
141：第三表面
142：表面
150：第二穿孔
152：壁面
160：重布线层
170：阻隔层
172：开口
180：导电结构
190：空穴
210：支撑件
2-2：线段
D1～D2：孔径
D3～D5：厚度
L1：线段
L2：线段
S1～S6：步骤。
具体实施方式
以下将以图式揭露本发明的多个实施方式，为明确说明起见，许多实务上的细节将在以下叙述中一并说明。然而，应了解到，这些实务上的细节不应用以限制本发明。也就是说，在本发明部分实施方式中，这些实务上的细节是非必要的。此外，为简化图式起见，一些已知惯用的结构与元件在图式中将以简单示意的方式绘示。
图1绘示根据本发明一实施方式的晶片封装体100的俯视图。图2绘示图1的晶片封装体100沿线段2-2的剖面图。同时参阅图1与图2，晶片封装体100包含感测晶片110、激光阻档件120、绝缘层140、重布线层160(RedistributionLayer；RDL)、阻隔层170与导电结构180。晶片110具有焊垫112、及相对的第一表面111与第二表面113。第一表面111为感测面。焊垫112位于第一表面111上。第二表面113具有第一穿孔114，使焊垫112从第一穿孔114裸露。激光阻档件120位于焊垫112上。绝缘层140位于晶片110的第二表面113上与第一穿孔114中，且绝缘层140具有相对第二表面113的第三表面141。绝缘层140与焊垫112共同具有第二穿孔150，使激光阻档件120从第二穿孔150裸露。重布线层160位于绝缘层140的第三表面141上、第二穿孔150的壁面上与第二穿孔150中的激光阻档件120上。阻隔层170位于绝缘层140的第三表面141上与重布线层160上。阻隔层170具有开口172，使重布线层160从阻隔层170的开口172裸露。导电结构180位于开口172中的重布线层160上，使导电结构180通过重布线层160电性连接焊垫112。
在本实施方式中，晶片封装体100可以为指纹感测装置(fingerprintsensor)或射频感测装置(RFsensor)，但并不用以限制本发明。晶片110的材质可以包含硅。激光阻档件120的材质可以包含金，例如为金球(goldball)。重布线层160的材质可以包含铜，可采用电镀的方式形成。绝缘层140的材质可以包含环氧树脂(epoxy)。
图3绘示图2的晶片封装体100的局部放大图。激光阻档件120具有朝向重布线层160的第四表面122。第二穿孔150可利用激光贯穿绝缘层140与焊垫112而形成。通过激光的使用，第二穿孔150的孔径D2可小于第一穿孔114的孔径D1，对于微小化设计有所助益。由于第二穿孔150由激光形成，因此第二穿孔150的壁面152与激光阻档件120的第四表面122均为粗糙面。第二穿孔150的壁面152包含焊垫112的表面115与绝缘层140的表面142。也就是说，壁面152为焊垫112与绝缘层140朝向第二穿孔150的表面。
由于激光阻档件120位于焊垫112上，因此当激光贯穿绝缘层140与焊垫112时，激光可由激光阻档件120阻挡，并于绝缘层140与焊垫112中形成裸露激光阻档件120的第二穿孔150。待第二穿孔150形成后，便可以化镀加电镀重布线层160于绝缘层140的第三表面141上、第二穿孔150的壁面152上与第二穿孔150中的激光阻档件120上，使得重布线层160可电性连接焊垫112。
此外，由于重布线层160以电镀的方式形成，因此重布线层160在绝缘层140的第三表面141上的厚度D3大于重布线层160在第二穿孔150的壁面152上的厚度D4，且重布线层160在第二穿孔150的壁面152上的厚度D4大于重布线层160在激光阻档件120上的厚度D5。在本实施方式中，晶片封装体100还具有空穴190，且空穴190位于阻隔层170与第二穿孔150中的重布线层160之间。
在以下叙述中，将说明晶片封装体100的制造方法。
图4绘示根据本发明一实施方式的晶片封装体的制造方法的流程图。晶片封装体的制造方法包含下列步骤。在步骤S1中，提供晶圆与激光阻档件，其中晶圆具有焊垫、及相对的第一表面与第二表面，且焊垫位于第一表面，激光阻档件位于焊垫上。接着在步骤S2中，于晶圆的第一表面暂时接合支撑件。之后在步骤S3中，在晶圆的第二表面中形成第一穿孔，使焊垫从第一穿孔裸露。接着在步骤S4中，于晶圆的第二表面上与第一穿孔中形成绝缘层，其中绝缘层具有相对第二表面的第三表面。之后在步骤S5中，使用激光贯穿绝缘层与焊垫以形成第二穿孔，其中激光由激光阻档件阻挡，且激光阻档件从第二穿孔裸露。最后在步骤S6中，于绝缘层的第三表面上、第二穿孔的壁面上与第二穿孔中的激光阻档件上电镀重布线层。在以下叙述中，将说明上述步骤。
图5绘示根据本发明一实施方式的晶圆110a与激光阻档件120的剖面图。晶圆110a意指切割后可形成多个图2的晶片110的半导体基板。首先，可提供晶圆110a与激光阻档件120，其中晶圆110a具有焊垫112、及相对的第一表面111与第二表面113，且焊垫112位于第一表面111，激光阻档件120位于焊垫112上。在本实施方式中，可通过打一导线(例如金线)于晶圆110a的焊垫112上，接着切除部分导线，使晶圆110a的焊垫112上残留另一部分导线而形成激光阻档件120。激光阻档件120例如为金球。
图6绘示图5的晶圆110a接合支撑件210后的剖面图。同时参阅图5与图6，待图5的结构形成后，可暂时接合支撑件210于晶圆110a的第一表面111。支撑件210可提供晶圆110a支撑力，防止晶圆110a在后续制程中因受力而破裂。待接合支撑件210于晶圆110a后，可研磨晶圆110a的第二表面113，以减薄晶圆110a的厚度。
图7绘示图6的晶圆110a形成第一穿孔114后的剖面图。同时参阅图6与图7，接着，可在晶圆110a的第二表面113中形成第一穿孔114，使焊垫112从第一穿孔114裸露。在此步骤中，可采用蚀刻制程在晶圆110a中形成第一穿孔114，例如干蚀刻制程。
图8绘示图7的晶圆110a的第二表面113上与第一穿孔114中形成绝缘层140后的剖面图。同时参阅图7与图8，待第一穿孔114形成后，便可形成绝缘层140于晶圆110a的第二表面113上与第一穿孔114中，其中绝缘层140具有相对第二表面113的第三表面141。在此步骤中，绝缘层140可采用印刷的方式形成于晶圆110a的第二表面113上与第一穿孔114中。接着，设计者可依需求涂布、压印、制模或研磨绝缘层140的第三表面141，以减薄绝缘层140的厚度。
图9绘示图8的绝缘层140与焊垫112中形成第二穿孔150后的剖面图。同时参阅图8与图9，待图8的结构形成后，可使用激光贯穿绝缘层140与焊垫112以形成第二穿孔150。激光可由焊垫112上的激光阻档件120阻挡，使激光阻档件120从第二穿孔150裸露。此外，激光对准第一穿孔114与激光阻档件120发射，因此第二穿孔150可由第一穿孔114环绕。
图10绘示图9的绝缘层140的第三表面141、第二穿孔150的壁面与激光阻档件120上形成重布线层160后的剖面图。同时参阅图9与图10，待第二穿孔150形成于绝缘层140与焊垫112中后，可电镀重布线层160于绝缘层140的第三表面141上、第二穿孔150的壁面上与第二穿孔150中的激光阻档件120上。
图11绘示图10的绝缘层140与重布线层160上形成阻隔层170后的剖面图。同时参阅图10与图11，待图10的结构形成后，可形成阻隔层170于绝缘层140的第三表面141上与重布线层160上。接着，可图案化阻隔层170以形成开口172，使部分的重布线层160可从阻隔层170的开口172裸露。
图12绘示图11的重布线层160上形成导电结构180后的剖面图。同时参阅图11与图12，待阻隔层170的开口172形成后，可形成导电结构180于开口172中的重布线层160上，使得导电结构180可通过重布线层160电性连接焊垫112。在此步骤后，便可移除晶圆110a的第一表面111上的支撑件210。
最后，可沿线段L1、L2切割晶圆110a、绝缘层140与阻隔层170，以形成图2的晶片封装体100。
本发明的晶片封装体及其制造方法可省略已知化学气相沉积绝缘层与图案化绝缘层的制程，能节省制程的时间与机台的成本。此外，晶片的第一表面未经额外的加工，因此平坦性佳，可提升晶片封装体侦测时的准确度。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。

Claims (18)

1.一种晶片封装体，其特征在于，包含：
一晶片，具有一焊垫、及相对的一第一表面与一第二表面，其中该焊垫位于该第一表面上，该第二表面具有一第一穿孔，使该焊垫从该第一穿孔裸露；
一激光阻档件，位于该焊垫上；
一绝缘层，位于该第二表面上与该第一穿孔中，该绝缘层具有相对该第二表面的一第三表面，该绝缘层与该焊垫共同具有一第二穿孔，使该激光阻档件从该第二穿孔裸露；
一重布线层，位于该第三表面上、该第二穿孔的一壁面上与该第二穿孔中的该激光阻档件上；
一阻隔层，位于该第三表面上与该重布线层上，该阻隔层具有一开口，使该重布线层从该开口裸露；以及
一导电结构，位于该开口中的该重布线层上，使该导电结构电性连接该焊垫。
2.根据权利要求1所述的晶片封装体，其特征在于，该激光阻档件的材质包含金。
3.根据权利要求1所述的晶片封装体，其特征在于，该第二穿孔的孔径小于该第一穿孔的孔径。
4.根据权利要求1所述的晶片封装体，其特征在于，具有一空穴，且该空穴位于该阻隔层与该第二穿孔中的该重布线层之间。
5.根据权利要求1所述的晶片封装体，其特征在于，该第二穿孔的该壁面为一粗糙面。
6.根据权利要求1所述的晶片封装体，其特征在于，该激光阻档件具有朝向该重布线层的一第四表面，且该第四表面为一粗糙面。
7.根据权利要求1所述的晶片封装体，其特征在于，该重布线层在该绝缘层的该第三表面上的厚度大于该重布线层在该第二穿孔的该壁面上的厚度。
8.根据权利要求1所述的晶片封装体，其特征在于，该重布线层在该第二穿孔的该壁面上的厚度大于该重布线层在该激光阻档件上的厚度。
9.根据权利要求1所述的晶片封装体，其特征在于，该绝缘层的材质包含环氧树脂。
10.一种晶片封装体的制造方法，其特征在于，包含：
(a)提供一晶圆与一激光阻档件，其中该晶圆具有一焊垫、及相对的一第一表面与一第二表面，该焊垫位于该第一表面，该激光阻档件位于该焊垫上；
(b)于该晶圆的该第一表面暂时接合一支撑件；
(c)在该晶圆的该第二表面中形成一第一穿孔，使该焊垫从该第一穿孔裸露；
(d)于该晶圆的该第二表面上与该第一穿孔中形成一绝缘层，其中该绝缘层具有相对该第二表面的一第三表面；
(e)使用一激光贯穿该绝缘层与该焊垫以形成一第二穿孔，其中该激光由该激光阻档件阻挡，且该激光阻档件从该第二穿孔裸露；以及
(f)于该绝缘层的该第三表面上、该第二穿孔的一壁面上与该第二穿孔中的该激光阻档件上电镀一重布线层。
11.根据权利要求10所述的晶片封装体的制造方法，其特征在于，还包含：
于该绝缘层的该第三表面上与该重布线层上形成一阻隔层；以及
图案化该阻隔层以形成一开口，使该重布线层从该开口裸露。
12.根据权利要求11所述的晶片封装体的制造方法，其特征在于，还包含：
于该开口中的该重布线层上形成一导电结构。
13.根据权利要求11所述的晶片封装体的制造方法，其特征在于，还包含：
切割该晶圆、该绝缘层与该阻隔层，以形成该晶片封装体。
14.根据权利要求10所述的晶片封装体的制造方法，其特征在于，还包含：
于该晶圆的该焊垫上打一导线；以及
切除部分该导线，使该晶圆的该焊垫上残留另一部分该导线而形成该激光阻档件。
15.根据权利要求10所述的晶片封装体的制造方法，其特征在于，还包含：
研磨该晶圆的该第二表面。
16.根据权利要求10所述的晶片封装体的制造方法，其特征在于，该步骤(d)包含：
于该晶圆的该第二表面上与该第一穿孔中印刷该绝缘层。
17.根据权利要求10所述的晶片封装体的制造方法，其特征在于，还包含：
涂布、压印、制模或研磨该绝缘层的该第三表面。
18.根据权利要求10所述的晶片封装体的制造方法，其特征在于，还包含：
移除该晶圆的该第一表面上的该支撑件。
CN201510450190.1A 2014-11-12 2015-07-28 晶片封装体及其制造方法 Active CN105590916B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201462078876P 2014-11-12 2014-11-12
US62/078,876 2014-11-12

Publications (2)

Publication Number Publication Date
CN105590916A true CN105590916A (zh) 2016-05-18
CN105590916B CN105590916B (zh) 2018-07-31

Family

ID=55912834

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510450190.1A Active CN105590916B (zh) 2014-11-12 2015-07-28 晶片封装体及其制造方法

Country Status (3)

Country Link
US (2) US9543233B2 (zh)
CN (1) CN105590916B (zh)
TW (1) TWI581325B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108022870A (zh) * 2016-11-04 2018-05-11 凤凰先驱股份有限公司 封装基板及其制作方法
CN109087897A (zh) * 2017-06-13 2018-12-25 精材科技股份有限公司 晶片封装体及其制作方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI581325B (zh) * 2014-11-12 2017-05-01 精材科技股份有限公司 晶片封裝體及其製造方法
TWI582918B (zh) * 2014-11-12 2017-05-11 精材科技股份有限公司 晶片封裝體及其製造方法
TWI603447B (zh) 2014-12-30 2017-10-21 精材科技股份有限公司 晶片封裝體及其製造方法
TWI617992B (zh) * 2016-06-29 2018-03-11 關鍵禾芯科技股份有限公司 指紋辨識裝置及其製造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020059951A1 (en) * 2000-09-29 2002-05-23 Aisin Seiki Kabushiki Kaisha Thermoelectric module and process for producing thermoelectric module
CN101807662A (zh) * 2009-02-18 2010-08-18 财团法人工业技术研究院 热电元件及其制作方法、芯片堆叠结构及芯片封装结构
CN101996978A (zh) * 2009-08-20 2011-03-30 精材科技股份有限公司 芯片封装体及其形成方法
CN102629560A (zh) * 2011-02-08 2012-08-08 旭德科技股份有限公司 封装载板及其制作方法

Family Cites Families (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6444576B1 (en) * 2000-06-16 2002-09-03 Chartered Semiconductor Manufacturing, Ltd. Three dimensional IC package module
JP4072677B2 (ja) * 2003-01-15 2008-04-09 セイコーエプソン株式会社 半導体チップ、半導体ウエハ、半導体装置及びその製造方法、回路基板並びに電子機器
US7091124B2 (en) * 2003-11-13 2006-08-15 Micron Technology, Inc. Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices
US7419852B2 (en) * 2004-08-27 2008-09-02 Micron Technology, Inc. Low temperature methods of forming back side redistribution layers in association with through wafer interconnects, semiconductor devices including same, and assemblies
US7271482B2 (en) * 2004-12-30 2007-09-18 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US20080284041A1 (en) * 2007-05-18 2008-11-20 Samsung Electronics Co., Ltd. Semiconductor package with through silicon via and related method of fabrication
US8253230B2 (en) * 2008-05-15 2012-08-28 Micron Technology, Inc. Disabling electrical connections using pass-through 3D interconnects and associated systems and methods
JP2009295676A (ja) * 2008-06-03 2009-12-17 Oki Semiconductor Co Ltd 半導体装置及びその製造方法
US7800238B2 (en) * 2008-06-27 2010-09-21 Micron Technology, Inc. Surface depressions for die-to-die interconnects and associated systems and methods
US8193632B2 (en) * 2008-08-06 2012-06-05 Industrial Technology Research Institute Three-dimensional conducting structure and method of fabricating the same
US8889548B2 (en) * 2008-09-30 2014-11-18 Infineon Technologies Ag On-chip RF shields with backside redistribution lines
CN102197479A (zh) * 2008-10-30 2011-09-21 Nxp股份有限公司 具有金属膏的基板贯通过孔和重分布层
US7838337B2 (en) * 2008-12-01 2010-11-23 Stats Chippac, Ltd. Semiconductor device and method of forming an interposer package with through silicon vias
US8513119B2 (en) * 2008-12-10 2013-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bump structure having tapered sidewalls for stacked dies
JP5532394B2 (ja) * 2009-10-15 2014-06-25 セイコーエプソン株式会社 半導体装置及び回路基板並びに電子機器
JP5518091B2 (ja) * 2009-11-12 2014-06-11 パナソニック株式会社 半導体装置及び半導体装置の製造方法
US8618654B2 (en) * 2010-07-20 2013-12-31 Marvell World Trade Ltd. Structures embedded within core material and methods of manufacturing thereof
US8710680B2 (en) * 2010-03-26 2014-04-29 Shu-Ming Chang Electronic device package and fabrication method thereof
US8847380B2 (en) * 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
US8610259B2 (en) * 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
JP2012099548A (ja) * 2010-10-29 2012-05-24 Fujikura Ltd 貫通配線基板の製造方法及び貫通配線基板
US8736066B2 (en) * 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
KR101789765B1 (ko) * 2010-12-16 2017-11-21 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US8883561B2 (en) * 2011-04-30 2014-11-11 Stats Chippac, Ltd. Semiconductor device and method of embedding TSV semiconductor die within encapsulant with TMV for vertical interconnect in POP
US8900994B2 (en) * 2011-06-09 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for producing a protective structure
US8894868B2 (en) * 2011-10-06 2014-11-25 Electro Scientific Industries, Inc. Substrate containing aperture and methods of forming the same
US8466062B2 (en) * 2011-11-02 2013-06-18 Globalfoundries Singapore Pte Ltd TSV backside processing using copper damascene interconnect technology
US8872196B2 (en) * 2011-12-19 2014-10-28 Xintec Inc. Chip package
US20130307147A1 (en) * 2012-05-18 2013-11-21 Xintec Inc. Chip package and method for forming the same
US8796829B2 (en) * 2012-09-21 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal dissipation through seal rings in 3DIC structure
TWI536547B (zh) * 2013-01-10 2016-06-01 精材科技股份有限公司 影像感測晶片封裝體之製作方法
TWI560825B (en) * 2013-02-08 2016-12-01 Xintec Inc Chip scale package structure and manufacturing method thereof
EP2772939B1 (en) * 2013-03-01 2016-10-19 Ams Ag Semiconductor device for detection of radiation and method of producing a semiconductor device for detection of radiation
US9093462B2 (en) * 2013-05-06 2015-07-28 Qualcomm Incorporated Electrostatic discharge diode
KR101514137B1 (ko) * 2013-08-06 2015-04-21 앰코 테크놀로지 코리아 주식회사 반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지
EP2871456B1 (en) * 2013-11-06 2018-10-10 Invensense, Inc. Pressure sensor and method for manufacturing a pressure sensor
TWI582918B (zh) * 2014-11-12 2017-05-11 精材科技股份有限公司 晶片封裝體及其製造方法
TWI581325B (zh) * 2014-11-12 2017-05-01 精材科技股份有限公司 晶片封裝體及其製造方法
TWI603447B (zh) * 2014-12-30 2017-10-21 精材科技股份有限公司 晶片封裝體及其製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020059951A1 (en) * 2000-09-29 2002-05-23 Aisin Seiki Kabushiki Kaisha Thermoelectric module and process for producing thermoelectric module
CN101807662A (zh) * 2009-02-18 2010-08-18 财团法人工业技术研究院 热电元件及其制作方法、芯片堆叠结构及芯片封装结构
CN101996978A (zh) * 2009-08-20 2011-03-30 精材科技股份有限公司 芯片封装体及其形成方法
CN102629560A (zh) * 2011-02-08 2012-08-08 旭德科技股份有限公司 封装载板及其制作方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108022870A (zh) * 2016-11-04 2018-05-11 凤凰先驱股份有限公司 封装基板及其制作方法
CN108022870B (zh) * 2016-11-04 2021-04-06 恒劲科技股份有限公司 封装基板及其制作方法
CN109087897A (zh) * 2017-06-13 2018-12-25 精材科技股份有限公司 晶片封装体及其制作方法
US11476293B2 (en) 2017-06-13 2022-10-18 Xintec Inc. Manufacturing method of chip package

Also Published As

Publication number Publication date
US20160133544A1 (en) 2016-05-12
TWI581325B (zh) 2017-05-01
US9543233B2 (en) 2017-01-10
US9768067B2 (en) 2017-09-19
US20170076981A1 (en) 2017-03-16
TW201618176A (zh) 2016-05-16
CN105590916B (zh) 2018-07-31

Similar Documents

Publication Publication Date Title
CN105590916A (zh) 晶片封装体及其制造方法
TWI534969B (zh) 晶片封裝體及其製造方法
CN105590911A (zh) 晶片封装体及其制造方法
CN102593094B (zh) 晶片封装体及其形成方法
TWI459485B (zh) 晶片封裝體的形成方法
CN106098639B (zh) 晶片封装体及其制造方法
CN105701443B (zh) 晶片封装体及其制造方法
US8994148B2 (en) Device bond pads over process control monitor structures in a semiconductor die
US9431321B2 (en) Method of manufacturing a semiconductor device and semiconductor integrated circuit wafer
CN105789172A (zh) 晶片封装体及其制造方法
CN105975114A (zh) 晶片尺寸等级的感测晶片封装体及其制造方法
JP6235383B2 (ja) 半導体装置の製造方法および半導体集積回路ウェハ
TWI603241B (zh) 一種觸控面板-感測晶片封裝體模組複合體及其製造方法
TWI593069B (zh) 晶片封裝體及其製造方法
US9568386B2 (en) MEMS device with protective structure
CN106098711A (zh) 晶片封装体及其制造方法
US9365415B2 (en) Compact electronic package with MEMS IC and related methods
CN105742254B (zh) 晶片封装体及其制造方法
JP2016105463A (ja) 半導体ウェハおよび半導体装置の製造方法
US20160118348A1 (en) Strain detection structures for bonded wafers and chips
US20180166390A1 (en) Planar package structure and manufacturing method thereof
JP2007048849A (ja) 半導体装置
JP2012033822A (ja) 半導体装置及びその製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant