TWI515829B - 一種晶圓級之封裝方法及封裝結構 - Google Patents

一種晶圓級之封裝方法及封裝結構 Download PDF

Info

Publication number
TWI515829B
TWI515829B TW102131200A TW102131200A TWI515829B TW I515829 B TWI515829 B TW I515829B TW 102131200 A TW102131200 A TW 102131200A TW 102131200 A TW102131200 A TW 102131200A TW I515829 B TWI515829 B TW I515829B
Authority
TW
Taiwan
Prior art keywords
wafer
layer
interposer
conductive pillar
disposed
Prior art date
Application number
TW102131200A
Other languages
English (en)
Other versions
TW201508864A (zh
Inventor
廖宗仁
Original Assignee
南茂科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 南茂科技股份有限公司 filed Critical 南茂科技股份有限公司
Priority to TW102131200A priority Critical patent/TWI515829B/zh
Priority to CN201410064021.XA priority patent/CN104425397B/zh
Priority to US14/198,493 priority patent/US9087912B2/en
Publication of TW201508864A publication Critical patent/TW201508864A/zh
Application granted granted Critical
Publication of TWI515829B publication Critical patent/TWI515829B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/1624—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24101—Connecting bonding areas at the same height
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/244—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/9202—Forming additional connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

一種晶圓級之封裝方法及封裝結構
本揭露涉及一種封裝方法及封裝結構，更具體地說，涉及一種晶圓級之封裝方法及封裝結構。
目前的矽中介層主要係運用矽穿孔(TSV)技術及銅電鍍製程來形成導通矽中介層之上層與矽中介層之下層的介面。由於矽穿孔(TSV)技術所形成的孔徑較小，因此銅電鍍製程很難於矽穿孔中形成導通的電路。此外，銅電鍍製程完成後，還需要將矽中介層進行研磨而促進矽中介層之上層與矽中介層之下層間的電性導通，因此良率不高。且銅電鍍製程中，電鍍藥水及機台均需重新調配及設計，而使整體成本升高。
本揭露提供一種晶圓級之封裝方法及封裝結構，其方法包含下列步驟： 提供一第一晶圓，其包含一表面，其中一介電層及一第一導電柱於該表面上，且該第一導電柱穿透該介電層；切割該第一晶圓而形成一第一晶片；形成一貫穿孔於一中介層，其中該中介層的厚度不大於該第一導電柱的長度；設置該第一導電柱於該貫穿孔；覆蓋一封裝層於該第一晶片及部份之中介層(30)上；塗布一第一電絕緣層於該中介層之一表面上；沉積一線路重佈層於該第一電絕緣層上，其中該線路重佈層電性連接該第一導電柱；以及設置一錫球於該線路重佈層上，進而完成晶圓級之封裝結構。
本揭露提供一種晶圓級之封裝結構包含一第一晶片、一中介層、一封裝層、一第一電絕緣層、一線路重佈層及一錫球。第一晶片包含一表面，其中一介電層及一第一導電柱設置於該表面上，且該第一導電柱穿透該介電層。中介層具有至少一貫穿孔，其中該中介層的厚度不大於該第一導電柱的長度。該第一晶片設置於該中介層上，使該第一導電柱設置於該貫穿孔中。封裝層覆蓋於該第一晶片及部份之中介層上。第一電絕緣層設置於該中介層之一表面上。線路重佈層設置於該第一電絕緣層上，其中該線路重佈層電性連接該第一導電柱以及錫球連接於該線路重佈層上。
本揭露之其他目的，部分將在後續說明中陳述，而部分可由內容說明中輕易得知，或可由本揭露之實施而得知。本 揭露之各方面將可利用後附之申請專利範圍中所特別指出之元件及組合而理解並達成。需了解，先述的一般說明及下列詳細說明均僅作舉例之用，並非用以限制本揭露。
10‧‧‧第一晶圓
11‧‧‧表面
12‧‧‧底面
13‧‧‧介電層
14‧‧‧第一導電柱
15‧‧‧第一晶片
20‧‧‧第二晶圓
21‧‧‧上表面
22‧‧‧下表面
23‧‧‧電隔離層
24‧‧‧第二導電柱
25‧‧‧第二晶片
30‧‧‧中介層
31‧‧‧貫穿孔
32‧‧‧表面
33‧‧‧面
40‧‧‧封裝層
50‧‧‧第一電絕緣層
60‧‧‧線路重佈層
70‧‧‧第二電絕緣層
80‧‧‧錫球
為了使本揭露之敘述更加詳盡與完備，可參照下列描述並配合下列圖式，其中類似的元件符號代表類似的元件。然以下實施例中所述，僅用以說明本揭露，並非用以限制本揭露的範圍。
圖1為根據本揭露之一實施例之第一晶圓之示意圖；圖2為根據本揭露之一實施例之第一晶圓切割後所形成的第一晶片之示意圖；圖3為根據本揭露之一實施例之第二晶圓之示意圖；圖4為根據本揭露之一實施例之第二晶圓切割後所形成的第二晶片之示意圖；圖5為根據本揭露之一實施例之形成貫穿孔於中介層之示意圖；圖6為根據本揭露之一實施例之第一晶片及第二晶片設置於中介層上之示意圖；圖7為根據本揭露之一實施例之覆蓋封裝層於中介層上之示意圖；圖8為根據本揭露之一實施例之塗布第一電絕緣層於中介層上之示意圖；圖9為根據本揭露之一實施例之沉積線路重佈層於電絕緣 層上之示意圖；圖10為根據本揭露之一實施例之塗布第二電絕緣層於中介層上之示意圖；以及圖11為根據本揭露之一實施例之設置錫球於線路重佈層上之示意圖。
本揭露之晶圓級封裝方法及封裝結構包含下列所述的各種圖式之步驟，然而並不限於此，亦可因應不同的設計而省略或修正特定步驟。
如圖1所示，提供一第一晶圓10。第一晶圓10包含一表面11。至少一第一導電柱14形成於晶圓10表面11上。此外，一介電層13形成於表面11，但不覆蓋第一導電柱14。換言之，第一導電柱14穿透介電層13。如圖1所示，至少一第一導電柱14設置於表面11上。在此說明書及申請專利範圍中的名詞「上」包含第一物件直接或間接地設置於第二物件的上方。例如，至少一第一導電柱14設置於表面11上就包含，第一導電柱14「直接」設置於表面11上及第一導電柱14「間接」設置於表面11上，兩種意義。此處的「間接」係指兩個物件在某一方位的垂直方向中具有上與下的關係，且兩者中間仍有其他物體、物質或間隔將兩者隔開。
如圖2所示，第一晶圓10切割而形成第一晶片15。換言之，第一晶片15就是部分之第一晶圓10。因此，第一晶片15的結構與第一晶圓10相同。
如圖3所示，第二晶圓20包含一上表面21。至少一第二導電柱24形成於上表面21上。此外，一電隔離層23形成設於上表面21，但不覆蓋第二導電柱24。換言之，第二導電柱24穿透電隔離層23。在此實施例中，第二導電柱24與第一導電柱14的直徑或寬度並不相同。具體而言，第二導電柱24的半徑小於第一導電柱14的半徑。然而在其他實施例(圖未示)中，第二導電柱24亦可設計為與第一導電柱14的直徑或寬度相同。
如圖4所示，第二晶圓20切割而形成第二晶片25。換言之，第二晶片25就是部分之第二晶圓20。因此，第二晶片25的結構與第二晶圓20相同。此外，此實施例中，設置於上表面21上之電隔離層23的厚度與介電層13的厚度不相同。具體而言，電隔離層23的厚度厚於介電層13的厚度。此厚度的差異可用來避免寄生效應或短路的現象。再者，此實施例中，第二導電柱24之間的距離與第一導電柱14之間的距離並不相同。具體而言，第二導電柱24之間的距離小於第一導電柱14之間的距離。然而在其他實施例(圖未示)中，第一晶圓10與第二晶圓20可為相同的結構。換言之，第一導電柱14與第二導電柱24之間的直徑或寬度、距離可為相同，且電隔離層23的厚度亦可與介電層13的厚度相同。
在其他實施例中，第一晶片15與第二晶片25為具有相同功能的晶片，因此第一晶片15與第二晶片25的厚度、大小為相同。在此實施例中，第一晶片15與第二晶片25相對應的介電層13與電隔離層23亦可為相同的材料及厚度。再者，至少一第一導電柱14間的間距亦可與至少一第二導電柱24間的間 距相同，此時第一導電柱14及第二導電柱24的長度與直徑亦可相同。
如圖5所示，貫穿孔31形成於中介層30中。在此實施例中，中介層30之材質例如可為矽晶圓，貫穿孔31的孔徑係因應於第一導電柱14與第二導電柱24的位置及直徑或寬度而調整，因此貫穿孔31彼此之間具有差異。然而在其他實施例(圖未示)中，貫穿孔31亦可設計於具有相同的孔徑。
於貫穿孔31形成步驟中，貫穿孔31係對齊於第一導電柱14與第二導電柱24，以供第一導電柱14與第二導電柱24容置於貫穿孔31內。
如圖5所示，中介層30的厚度不大於第一導電柱14與第二導電柱24之長度。具體而言，中介層30的厚度不大於第一導電柱14與第二導電柱24分別扣掉介電層13與電隔離層23之長度。
如圖6所示，第一晶片15及第二晶片25設置於中介層30上。使第一導電柱14與第二導電柱24分別設置於貫穿孔31內。具體而言，設置電隔離層23及介電層13於中介層30之另一面33，亦即是第一晶片15與第二晶片25相對於中介層30之間的表面33上。在另一可行之實施例中，電隔離層23及介電層13例如為一黏晶膠，使第一晶片15與第二晶片25可先行黏置於中介層30上，做為初步的定位。
如圖7所示，進行一封裝作業，使封裝層40覆蓋於第一晶片15及第二晶片25上。換言之，封裝層40覆蓋於第一晶圓10、第二晶圓20及部分之中介層30上。具體而言，第一晶圓10包含 一底面12而第二晶圓20包含一下表面22，封裝層40主要係覆蓋於底面12及下表面22上。封裝層40的覆蓋可協助將第一晶片15及第二晶片25固定於中介層30上，因此對於中介層30之下層的進一步製程時，並不會因為將中介層30翻面而導致第一晶片15及第二晶片25脫離中介層30。
如圖8所示，塗布一第一電絕緣層50於中介層30之一表面32。由於貫穿孔31與第一導電柱14及第二導電柱24之間具有間隔，因此第一電絕緣層50位於貫穿孔31附近的區域會下陷沈入貫穿孔31中填充塗佈後，再利用一道曝光顯影製程使第一導電柱14與第二導電柱24局部顯露出來，以供後續電性連接。是故，由於電隔離層23及介電層13與第一電絕緣層50之存在，使得中介層30之上層不會電性短路於中介層30之下層。
如圖9所示，沉積(或電鍍)一圖案化之線路重佈層60於第一電絕緣層50上。由於第一電絕緣層50並無覆蓋第一導電柱14與第二導電柱24，因此線路重佈層60電性連接第一導電柱14與第二導電柱24。如圖10所示，塗布一第二電絕緣層70於第一電絕緣層50與線路重佈層60上，再利用一道曝光顯影製程，使部份的線路重佈層60露出。具體而言，第二電絕緣層70可全面覆蓋線路重佈層60僅暴露出後續需與外部端子(例如是錫球)連接的區域，藉以透過第二電絕緣層70保護線路重佈層60避免氧化。
如圖11所示，設置一錫球80於暴露出之部分線路重佈層60上，進而完成晶圓級之封裝結構。
本發明之技術內容及技術特點已揭示如上，然而本發明 所屬技術領域中具有通常知識者應瞭解，在不背離後附申請專利範圍所界定之本發明精神和範圍內，本發明之教示及揭示可作種種之替換及修飾。例如，上文揭示之許多裝置或結構可以不同之方法實施或以其它結構予以取代，或者採用上述二種方式之組合。
10‧‧‧第一晶圓
14‧‧‧第一導電柱
20‧‧‧第二晶圓
40‧‧‧封裝層
60‧‧‧線路重佈層
70‧‧‧第二電絕緣層
80‧‧‧錫球

Claims (12)

  1. 一種晶圓級之封裝方法，包含：提供一第一晶圓，其包含一表面，其中一介電層及一第一導電柱於該表面上，且該第一導電柱穿透該介電層；切割該第一晶圓而形成一第一晶片；形成一貫穿孔於一中介層，其中該中介層包含一第一表面及一相對於該第一表面之第二表面，該中介層的厚度不大於該第一導電柱的長度；設置該第一晶片於該中介層之該第一表面且設置該第一導電柱於該貫穿孔；覆蓋一封裝層於該第一晶片及部份之中介層上；塗布一第一電絕緣層於該中介層之該第二表面上；形成一線路重佈層於該第一電絕緣層上，其中該線路重佈層電性連接該第一導電柱；以及設置一錫球於該線路重佈層上。
  2. 根據請求項1所述之封裝方法，進一步包含步驟：塗布一第二電絕緣層於該線路重佈層及該第一電絕緣層上。
  3. 根據請求項1所述之封裝方法，其中該貫穿孔形成步驟包含對齊該貫穿孔於該第一導電柱之步驟。
  4. 根據請求項1所述之封裝方法，進一步包含步驟：提供一第二晶圓，其包含一上表面，其中一電隔離層及一第二導電柱於該上表面上，且該第二導電柱穿透該電隔離層。
  5. 根據請求項4所述之封裝方法，進一步包含步驟：切割該第二晶圓而形成一第二晶片。
  6. 根據請求項5所述之封裝方法，其中該第一晶圓包含一底面，而該第二晶圓包含一下表面，於封裝層覆蓋步驟中另包含覆蓋該封裝層於該底面及該下表面上之步驟。
  7. 根據請求項6所述之封裝方法，其中該介電層之厚度等於該電隔離層之厚度。
  8. 根據請求項4所述之封裝方法，進一步包含步驟：設置該電隔離層及該介電層於該中介層之另一面上。
  9. 根據請求項4所述之封裝方法，進一步包含步驟：設置該第二導電柱於該貫穿孔。
  10. 根據請求項5所述之封裝方法，進一步包含步驟：覆蓋一封裝層於該第二晶片及部份之中介層上。
  11. 根據請求項4所述之封裝方法，其中該線路重佈層形成步驟包含電性連接該線路重佈層於該第二導電柱之步驟。
  12. 一種晶圓級之封裝結構，包含：一第一晶片，包含一表面，其中一介電層及一第一導電柱設置於該表面上，且該第一導電柱穿透該介電層；一中介層具有一第一表面、一相對於該第一表面之第二表面及至少一貫穿孔，其中該中介層的厚度不大於該第一導電柱的長度；該第一晶片設置於該中介層之該第一表面上，使該第一導電柱設置於該貫穿孔中；一封裝層覆蓋於該第一晶片及部份之中介層上； 一第一電絕緣層設置於該中介層之該第二表面上；一線路重佈層設置於該第一電絕緣層上，其中該線路重佈層電性連接該第一導電柱；以及一錫球連接於該線路重佈層上。
TW102131200A 2013-08-30 2013-08-30 一種晶圓級之封裝方法及封裝結構 TWI515829B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW102131200A TWI515829B (zh) 2013-08-30 2013-08-30 一種晶圓級之封裝方法及封裝結構
CN201410064021.XA CN104425397B (zh) 2013-08-30 2014-02-25 一种晶圆级封装方法及封装结构
US14/198,493 US9087912B2 (en) 2013-08-30 2014-03-05 Method for wafer level packaging and a package structure thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW102131200A TWI515829B (zh) 2013-08-30 2013-08-30 一種晶圓級之封裝方法及封裝結構

Publications (2)

Publication Number Publication Date
TW201508864A TW201508864A (zh) 2015-03-01
TWI515829B true TWI515829B (zh) 2016-01-01

Family

ID=52582067

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102131200A TWI515829B (zh) 2013-08-30 2013-08-30 一種晶圓級之封裝方法及封裝結構

Country Status (3)

Country Link
US (1) US9087912B2 (zh)
CN (1) CN104425397B (zh)
TW (1) TWI515829B (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10483237B2 (en) * 2016-11-11 2019-11-19 Semiconductor Components Industries, Llc Vertically stacked multichip modules
TWI672779B (zh) * 2016-12-28 2019-09-21 曦威科技股份有限公司 指紋辨識裝置、使用其之行動裝置以及指紋辨識裝置的製造方法
CN106783644A (zh) * 2017-01-13 2017-05-31 中芯长电半导体（江阴）有限公司 一种双面扇出型晶圆级封装方法及封装结构
CN106684006B (zh) * 2017-01-13 2022-04-01 盛合晶微半导体(江阴)有限公司 一种双面扇出型晶圆级封装方法及封装结构
CN109037425A (zh) * 2018-08-10 2018-12-18 付伟 带有延伸双围堰及金属层的芯片封装结构及其制作方法
US11069622B2 (en) 2019-03-22 2021-07-20 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Interposer-type component carrier and method of manufacturing the same
US11201136B2 (en) * 2020-03-10 2021-12-14 International Business Machines Corporation High bandwidth module

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3633559B2 (ja) * 1999-10-01 2005-03-30 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
SG104293A1 (en) * 2002-01-09 2004-06-21 Micron Technology Inc Elimination of rdl using tape base flip chip on flex for die stacking
JPWO2011058977A1 (ja) * 2009-11-10 2013-04-04 ローム株式会社 半導体装置および半導体装置の製造方法
KR20120123919A (ko) * 2011-05-02 2012-11-12 삼성전자주식회사 칩 적층 반도체 패키지 제조 방법 및 이에 의해 제조된 칩 적층 반도체 패키지
TWI492680B (zh) * 2011-08-05 2015-07-11 Unimicron Technology Corp 嵌埋有中介層之封裝基板及其製法

Also Published As

Publication number Publication date
CN104425397A (zh) 2015-03-18
US9087912B2 (en) 2015-07-21
CN104425397B (zh) 2017-04-12
US20150061121A1 (en) 2015-03-05
TW201508864A (zh) 2015-03-01

Similar Documents

Publication Publication Date Title
TWI515829B (zh) 一種晶圓級之封裝方法及封裝結構
US10446522B2 (en) Methods of forming multiple conductive features in semiconductor devices in a same formation process
US8963316B2 (en) Semiconductor device and method for manufacturing the same
US20140363967A1 (en) Through silicon vias for semiconductor devices and manufacturing method thereof
JP6317475B2 (ja) ウェーハレベルパッケージングのためのダイシング方法、およびウェーハレベルパッケージングに適応したダイシング構造を有する半導体チップ
US11133236B2 (en) Polymer-based-semiconductor structure with cavity
US10720495B2 (en) Semiconductor device and manufacturing method thereof
KR102206113B1 (ko) 관통 전극을 갖는 반도체 소자, 이를 구비하는 반도체 패키지 및 반도체 소자의 제조방법
TWI676244B (zh) 半導體封裝及其製造方法
US9659806B2 (en) Semiconductor package having conductive pillars
US10224243B2 (en) Method of fabricating electronic package
US9646944B2 (en) Alignment structures and methods of forming same
CN105633055B (zh) 半导体封装结构的制法
US8652939B2 (en) Method and apparatus for die assembly
TWI596715B (zh) 半導體封裝件及其製法
CN113707566A (zh) 半导体结构的制造方法及半导体结构
TWI548049B (zh) 半導體結構及其製法
KR102076305B1 (ko) 반도체 소자 및 그 형성 방법
US20150279796A1 (en) Quad-flat no-leads package structure and method of manufacturing the same
TW201533866A (zh) 半導體封裝件及其製法
TWI806263B (zh) 電子封裝件及其製法
TWI541948B (zh) 半導體封裝件及其製法
TWI611484B (zh) 電子封裝結構及其製法
US9466553B2 (en) Package structure and method for manufacturing package structure
TWI550704B (zh) 半導體製程及其晶片結構與晶片組合結構