CN104867967B - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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- CN104867967B CN104867967B CN201410327473.2A CN201410327473A CN104867967B CN 104867967 B CN104867967 B CN 104867967B CN 201410327473 A CN201410327473 A CN 201410327473A CN 104867967 B CN104867967 B CN 104867967B
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Classifications
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
本发明提供了一种半导体器件及其制造方法。半导体器件包括衬底、位于衬底上的栅极结构、在衬底中邻近一对间隔件的源极/漏极区、紧邻栅极结构并上覆衬底的蚀刻停止层、延伸到源极/漏极区中并与栅极结构部分重叠的接触塞、位于上覆衬底的蚀刻停止层上方并覆盖紧邻栅极结构而没有接触塞的蚀刻停止层的保护层以及位于保护层上方的层间介电层。接触塞与栅极结构没有接触件与栅极的短路问题。
Description
技术领域
本发明一般地涉及半导体技术领域,更具体地,涉及半导体器件及其形成方法。
背景技术
半导体工艺经历了快速发展。集成电路(IC)的制造集中于增加IC的数目和晶圆中各个IC的微型化。IC器件包括各种微电子部件,诸如金属氧化物半导体场效应晶体管(MOSFET)。此外,MOSFET包括若干部件,诸如栅电极、栅极介电层、间隔件、以及源极区和漏极区的扩散区。通常,沉积层间介电(ILD)层以覆盖MOSFET,随后通过在ILD层中形成连接源极/漏极区的接触塞来形成电连接件。由于IC器件的尺寸减小,栅极长度和MOSFET之间的距离都减小,从而会导致各种问题,诸如IC器件制造的过程中的接触短路。
发明内容
为了解决现有技术中所存在的缺陷,根据本发明的一方面,提供了一种半导体器件,包括:衬底;栅极结构,位于所述衬底上方,包括:栅极介电层,位于所述衬底上方;栅电极,位于所述栅极介电层上方;隔离层,位于所述栅电极上方;以及一对间隔件,紧邻所述栅电极的两侧;源极/漏极区,邻近所述一对间隔件位于所述衬底中;蚀刻停止层,紧邻所述一对间隔件并上覆所述衬底;接触塞,延伸到所述源极/漏极区中并穿过所述间隔件与所述栅极结构部分地重叠;保护层,位于上覆所述衬底的蚀刻停止层的上方并覆盖紧邻所述间隔件而没有所述接触塞的所述蚀刻停止层;以及层间介电层,位于所述保护层上方。
在该半导体器件中,所述层间介电层的材料的折射率在2.5至4的范围内。
在该半导体器件中,所述层间介电层的材料为可流动性氧化物。
在该半导体器件中,所述栅电极为金属电极且所述栅极介电层为高k介电层。
在该半导体器件中,所述保护层的材料的折射率可在1.4至2的范围内。
在该半导体器件中,所述保护层的材料选自包含SiON、SiOCN和SiO2的组。
在该半导体器件中,所述保护层的厚度在约1nm至约5nm的范围内。
在该半导体器件中,所述蚀刻停止层的厚度在约1nm至约15nm的范围内。
在该半导体器件中,所述蚀刻停止层的材料包含Si3N4或SiN。
在该半导体器件中,所述隔离层的材料包含SiN。
在该半导体器件中,所述蚀刻停止层的厚度小于所述隔离层的厚度。
根据本发明的另一方面,提供了一种半导体器件,包括:衬底;栅极结构,位于所述衬底上方,包括:栅极介电层,位于所述衬底上方;栅电极,位于所述栅极介电层上方;隔离层,位于所述栅电极上方;以及一对间隔件,紧邻所述栅电极的两侧;源极/漏极区,邻近所述一对间隔件位于所述衬底中;蚀刻停止层,紧邻所述一对间隔件并上覆所述衬底;接触塞,延伸到所述源极/漏极区中并穿过所述间隔件与所述栅极结构部分地重叠;保护层,位于上覆所述衬底的蚀刻停止层的上方;以及层间介电层,位于所述保护层上方。
在该半导体器件中,所述保护层的材料选自包含SiON、SiOCN和SiO2的组。
在该半导体器件中,所述保护层的厚度在约1nm至约5nm的范围内。
在该半导体器件中,所述蚀刻停止层的厚度在约1nm至约15nm的范围内。
根据本发明的又一方面,提供了一种制造半导体器件的方法,包括:形成具有伪栅电极的栅极结构并且邻近衬底上方的伪栅极结构形成源极/漏极区;将蚀刻停止层沉积在所述衬底上方;将保护层沉积在所述蚀刻停止层上方;将层间介电层沉积在所述蚀刻停止层上方;将所述层间介电层进行抛光并退火;通过替换所述伪栅极结构的一部分形成金属栅极结构;将隔离层沉积在所述金属栅极结构上方;形成穿过所述层间介电层并到达所述源极/漏极区和所述隔离层的接触开口;以及在所述接触开口中形成接触塞。
在该方法中,通过替换所述伪栅极结构的一部分形成所述金属栅极结构包括:去除所述伪栅电极;将栅极介电层沉积在所述栅极结构中;将功函层沉积在所述栅极介电层上方;以及在所述功函层上方形成金属电极。
在该方法中,形成穿过所述层间介电层到达所述源极/漏极区和所述隔离层的所述接触开口包括:蚀刻紧邻间隔件的所述层间介电层和所述保护层的一部分;以及蚀刻所述蚀刻停止层的一部分以接触所述源极/漏极区。
在该方法中,将所述保护层沉积在所述蚀刻停止层上方,所述保护层的厚度在约1nm至约5nm的范围内。
在该方法中,将所述层间介电层沉积在所述蚀刻停止层上方,所述层间介电层的材料包括可流动性氧化物。
附图说明
当结合附图进行阅读时,根据下面详细的描述可以更好地理解本发明的各个方面。应该注意,根据工业中的标准实践,各种部件没有被按比例绘制。实际上,为了清楚的讨论,各种部件的尺寸可以被任意增加或减少。
图1是根据本发明的多个实施例的半导体器件的截面图;
图2A至图2I是根据本发明的多个实施例处于制造半导体器件的各个阶段的截面图;以及
图3是根据本发明的各个实施例的半导体器件的截面图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同的实施例或实例。以下描述部件和配置的具体实例以简化所提供的主题。当然,这些仅仅是实例而不用于限制。例如,在以下描述中第一部件形成在第二部件上方或第二部件上可包括第一和第二部件被形成为直接接触的实施例,并且还可以包括在第一和第二部件之间的形成附加部件以使第一和第二部件不直接接触的实施例。再者,本公开内容可在各个实例中重复参考标号和/或字母。该重复是为了简明和清楚,而且其本身没有规定所述各种实施例和/或结构之间的关系。
正如本文中所使用的,术语“由···组成”、“包括着”、“具有”、“包含着”、“涉及”等应当被理解为是开放式的,即,意味着包括但不限制。
除非文章中清楚地作出另外的指示,否则本文所使用的单数形式“一”、“一个”和“该”包括复数。因此,例如,除非文章中清楚地作出另外的指示,否则参考介电层包括具有两个或更多这种介电层的实施例。整个本说明书中引用“一实施例”、“一个实施例”意味着在本发明的至少一个实施例中包括结合该实施例所描述的特定的部件、结构或特征。因此,整个说明书中的各个位置出现的短语“在一个实施中”或“在一实施例中”不一定都的是指同一个实施例。而且,在一个或多个实施例中可以以任何合适的方式组合特定部件、结构或特征。应该理解,以下附图没有按比例绘制;而这些附图只是为了阐明。
由于半导体器件间距减小,所以也需要调整接触塞的结构。根据本发明的各个实施例,设计接触塞的一种方式是直接紧邻栅极结构形成接触塞以节省接触塞与其它栅极结构之间的间距。根据本发明的各个实施例,另一种设计接触塞的方式是使接触塞中位于栅极结构之上的一部分延伸以使其它接触件易于与该接触塞对准。在形成这种部分延伸的接触塞的过程中,将隔离层沉积在栅极结构上方以防止接触件与栅极之间的短路问题。然而,根据本发明的各个实施例,当将用于接触塞结构的上述两种方法结合起来时,引发了另一接触件与栅极的短路问题。用于直接紧邻栅极结构的接触塞的开口的形成包括暴露源极/漏极区的一部分和隔离层的一部分,在蚀刻处理期间过蚀刻隔离层,从而导致接触件与栅极短路。因此,提供了一种用于形成半导体器件的机制。
参照图1,图1是根据本发明的各个实施例的半导体器件的截面图。半导体器件100包括衬底110、衬底110上方的栅极结构120、邻近栅极结构120的衬底110中的源极/漏极区130、紧邻栅极结构120并位于衬底110上方的蚀刻停止层140、延伸到源极/漏极区130中并与栅极结构120部分地重叠的接触塞170、位于上覆衬底的蚀刻停止层140上方并覆盖紧邻的栅极结构120而没有接触塞170的蚀刻停止层140的保护层150,以及位于保护层150上方的层间介电层160。栅极结构120包括位于衬底110上方的栅极介电层122、位于栅极介电层122上方的栅电极124、位于栅电极124上方的隔离层126以及紧邻栅电极124的两侧的一对间隔件128。
在本发明的各个实施例中,衬底110可包括硅。源极/漏极区130可掺杂硼、磷或砷。栅极介电层122可包括氧化硅,且栅电极124可包括多晶硅。在本发明的各个实施例中,栅极介电层122可包括高k介电材料,诸如HfO2、HfSiO、HfSiON、HfTaO、HfTiO或HfZrO;且栅电极124可包括金属,诸如铝、铜、钨或金属合金。隔离层126可包括氮化硅(SiN)。隔离层126的厚度在约5nm至约50nm的范围内。间隔件128可包括氮化硅。蚀刻停止层140可以包括氮化硅(Si3N4)。蚀刻停止层140的厚度在约1nm至约15nm的范围内。保护层150可包括折射率在约1.4至约2的范围内的氧化物,诸如氮氧化硅(SiON)。并且保护层150的厚度在约1nm至约5nm的范围内。层间介电层160可包括折射率在约2.5至约4的范围内的氧化物,诸如可流动性氧化物。并且接触塞170可包括钨。
根据本发明的一些实施例,保护层150用于保护衬底。当蚀刻停止层140的厚度接近隔离层126的厚度时,在突破(break through)蚀刻停止层140的蚀刻操作期间,可以穿透隔离层126,以形成连接源极/漏极区130的接触塞170。因此,根据一些实施例,由于蚀刻停止层140与隔离层126之间的低蚀刻选择性,半导体器件100可出现接触件与栅极的短路问题。解决上述问题的一种方法是减小蚀刻停止层140的厚度。但在蚀刻停止层140的厚度减小的情况下,在对层间介电层160进行退火操作时,氧气会穿透蚀刻停止层140并到达源极/漏极区130,从而会导致较高的接触电阻,甚至会导致衬底的氧化。沉积在蚀刻停止层140上方的包括高质量氧化物(包括折射率在约1.4至约2的范围内的氧化物)的保护层150(诸如氮氧化硅(SiON))可防止氧气穿透问题。此外,保护层150相较于蚀刻停止层140与隔离层126具有高蚀刻选择性,所以在突破保护层150时没有蚀刻隔离层126。因此,可减小蚀刻停止层140的厚度,以避免在突破蚀刻停止层140的蚀刻操作期间穿透隔离层126,从而形成连接源极/漏极区130的接触塞170。
参照图2A至图2I,图2A至图2I是根据本发明的各个实施例处于制造半导体器件的不同阶段的截面图。参照图2A,栅极结构216包括伪栅电极212,且在衬底200上方形成一对间隔件214。衬底200中的源极/漏极区210邻近栅极结构216。衬底200包括半导体材料,比如硅、锗、碳、如III-V族或II-VI族材料的其他半导体材料或它们的组合。在一些实施例中,衬底210包括晶体硅衬底(例如,晶圆)。此外,衬底210可包括产生应变的外延层和/或绝缘体上硅(SOI)结构。根据本发明的各个实施例,衬底200可包括有源区,其根据设计需求包括诸如p阱和n阱的各种掺杂结构。源极/漏极区210可掺杂有p型或n型掺杂剂。例如,源极/漏极区可掺杂有诸如硼或BF2的p型掺杂剂;诸如磷或砷的n型掺杂剂;和/或它们的组合。
栅电极212可包括多晶硅,且间隔件214可包括介电材料,诸如氮化硅、氧化硅、碳化硅、氮氧化硅、其它合适的材料和/或它们的组合。在一些实施例中,间隔件214可包括多层结构。栅极结构216可通过任意合适的工艺形成。例如,栅极结构216可通过沉积、光刻图案化和蚀刻工艺和/或它们的组合形成。沉积工艺可包括化学汽相沉积(CVD)、物理汽相沉积(PVD)、原子层沉积(ALD)、等离子体增强的CVD(PECVD)、高密度等离子体CVD(HDPCVD)、金属有机CVD(MOCVD)、远程等离子体CVD(PECVD)、外延生长方法(例如,选择性外延生长)、溅射、镀、旋涂、其它合适方法和/或它们的组合。光刻图案化工艺可包括光刻胶涂覆(例如,旋涂)、软烘、掩模对准、曝光、曝光后烘烤、显影光刻胶、漂洗、干燥(例如,硬烘)、其它合适的工艺和/或它们的组合。蚀刻工艺可包括干法蚀刻、湿法蚀刻和/或其它蚀刻方法(例如,反应离子蚀刻)。该蚀刻工艺还可为纯化学的(等离子体蚀刻)、纯物理的(离子研磨)和/或它们的组合。
参照图2B,根据本发明的各个实施例,将蚀刻停止层220沉积在栅极结构216和衬底200上方。该蚀刻停止层220可包括氮化硅(Si3N4)。可通过任何合适的方法(诸如CVD)来沉积蚀刻停止层220。蚀刻停止层220的厚度可在约1nm至约15nm的范围内。
参照图2C,根据本发明的各个实施例,将保护层230沉积在蚀刻停止层220上方。保护层230可包括高质量氧化物,其中,高质量意味着氧化物的折射率在约1.4至约2的范围内。例如,保护层230可包括SiO2、SiOCN、SiON和/或它们的组合。可通过任何合适的方法(诸如高密度等离子体CVD(HDP-CVD)或ALD)来沉积保护层230。保护层230可防止氧气穿过蚀刻停止层220扩散到衬底200中。因此,可减小蚀刻停止层220的厚度以防止接触件与栅极的问题。保护层230的厚度可在约1nm至约5nm的范围内。
参照图2D,根据本发明的各个实施例,将层间介电层240沉积在保护层230上方。因为半导体器件间距按比例减小,例如,两个金属栅极之间的间隔小于50nm,所以层间介电层240的材料需要良好的间隙填充能力来填充该间隔。良好的间隙填充能力的材料可以是折射率在约2.5至约4的范围内的氧化物。在本发明的各个实施例中,层间介电层240的材料可为可流动性氧化物,且可通过流动式CVD(FCVD)或其它合适的沉积方法来沉积层间介电层240。
参照图2E,根据本发明的各个实施例,将半导体器件平坦化以暴露栅极结构216的顶面。通过化学机械抛光(CMP)去除层间介电层240、保护层230和蚀刻停止层220的位于栅极结构216的顶面上方的部分以暴露栅极结构216。然后,通过氧气对半导体器件进行退火以增加层间介电层240的密度。包括高质量氧化物的保护层230可在退火工艺中阻挡氧气扩散,因此可保护衬底不被氧化。
参照图2F,根据本发明的各个实施例,去除伪栅电极212并由金属栅电极254替换。例如,在多个实施例中,伪栅电极212通过位于衬底上方的介于两个间隔件214之间的高k介电层250、位于高k介电层250上方的功函层252及位于功函层252上方的金属栅电极254进行替换以形成高k金属栅极(HKMG)结构。可以去除伪栅电极212以通过任何合适的工艺在间隔件214之间形成沟槽。然后可在栅极结构216的沟槽中形成高k介电层250、功函层252和金属栅电极254。高k介电层250可包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、金属氧化物、金属氮化物、金属硅酸盐、过渡金属氧化物、过渡金属氮化物、过渡金属-硅酸盐、金属氮氧化物、金属铝酸盐、硅酸锆、铝酸锆、氧化硅、氮化硅、氮氧化硅、氧化锆、氧化钛、氧化铝、二氧化铪-氧化铝(HfO2-Al2O3)合金、其它合适的高k介电材料和/或它们的组合。功函层252可包括用于PMOS的TiN、WN或W以及用于NMOS的TiAl、TiAlN或TaCN,或者是具有适当功函的其它合适的材料。金属栅电极254可包括导电材料,诸如铝、铜、钨、钛、钽、氮化钛、氮化钽、硅化镍、硅化钴、TaC、TaSiN、TaCN、TiAl、TiAlN、其它合适的材料和/或它们的组合。在一些实施例中,栅极结构216中的高k介电层250、功函层252和金属栅电极254可包括多层。且高k介电层250、功函层252和金属栅电极254可通过任意合适的工艺形成为任意合适的厚度。
参照图2G,根据本发明的各个实施例,去除金属栅电极254的一部分,且将隔离层260沉积在两个间隔件214之间的金属栅电极254上方。去除金属栅电极254、功函层252和高k介电层250的部分。然后以自对准的方式将隔离层260沉积在两个间隔件214之间的金属栅电极254上方。隔离层260可保护金属栅电极254不与接触塞接触。在各个实施例中,隔离层260可包括氮化硅(SiN)或其它合适的材料。隔离层260的厚度大于蚀刻层220的厚度,使得在形成接触开口时,不会穿透隔离层260。在本发明的各个实施例中,隔离层260的厚度可在约5nm至约50nm的范围内。可以通过任意合适的工艺(诸如本文所公开的CVD)来形成隔离层260。
参照图2H,根据本发明的多个实施例,接触开口270形成在层间介电层240中并与隔离层260和源极/漏极区210接触。接触开口270可形成为紧邻栅极结构216并栅极结构216的一部分上方,同时延伸到隔离层260与间隔件214的一部分中。可通过两步蚀刻操作形成接触开口270。第一蚀刻操作可蚀刻紧邻间隔件214的层间介电层240和保护层230的一部分,然后在蚀刻停止层220与隔离层260处停止。第一蚀刻工艺对于蚀刻停止层220和保护层230及隔离层260和层间介电层240具有蚀刻选择性。因为保护层230和层间介电层240都包括氧化物,而蚀刻停止层220和隔离层260都包括氮化物。因此保护层230不会影响蚀刻工艺,可与层间介电层240共同被蚀刻并且还可保护衬底不被氧化。因此可减小蚀刻停止层220的厚度并且在整个退火工艺的过程中不具有氧气扩散。第二蚀刻工艺可突破蚀刻停止层220的一部分以接触源极/漏极区。同时,因为隔离层260与蚀刻停止层220之间的蚀刻选择性低于氮化硅与氧化硅之间的选择性。还可通过第二蚀刻工艺蚀刻隔离层260的一部分。因为隔离层260的厚度大于蚀刻停止层220的厚度,所以隔离层260不会被过蚀刻,以不暴露金属栅电极254,从而避免接触件与栅极的短路问题。
参照图2I,根据本发明的各个实施例,在接触开口270中形成接触塞280。形成在层间介电层240中的接触塞280会接触隔离层260并延伸穿过保护层230和蚀刻停止层220,以接触源极/漏极区210。接触塞280可穿过间隔件214与栅极结构216部分重叠,并延伸到隔离层260中。直接紧邻栅极结构216所形成的接触塞280可节省半导体器件中的栅极结构之间的空间。并且接触塞280与栅极结构216重叠的部分可延伸接触塞280的顶面,从而放大了后续操作的工艺窗口。
参照图2A至图2I,根据本发明的各个实施例,提供了一种制造半导体的方法。该制造方法包括形成具有伪栅电极的栅极结构和邻近衬底上方的伪栅极结构的源极/漏极区。蚀刻停止层形成在衬底上方,且保护层沉积在蚀刻停止层上方。此外,层间介电层沉积在蚀刻停止层上方。此后,对层间介电层进行抛光和退火。通过替换伪栅极结构的一部分形成金属栅极结构,并将隔离层沉积在金属栅极结构上方。形成穿过层间介电层到达源极/漏极区和隔离层的接触开口,以及在接触开口中形成接触塞。根据一些实施例,通过替换伪栅极结构的一部分形成金属栅极结构的操作包括:去除伪栅电极;在栅极结构中形成栅极介电层;在栅极介电层上方形成功函层;以及在功函层上方形成金属电极。根据一些实施例,形成穿过层间介电层到达源极/漏极区和隔离层的接触开口的操作包括蚀刻紧邻间隔件的层间介电层和保护层的一部分并蚀刻部分蚀刻停止层以接触源极/漏极区。
参照图3、图2C和图2I,图3是根据本发明的各个实施例的半导体器件的截面图。图2I和图3的差别在于图3中的保护层230仅形成在上覆衬底200的蚀刻停止层220上方,但图2I中的保护层230形成在上覆衬底200的蚀刻停止层220上方,并覆盖紧邻间隔件214而没有接触塞280的蚀刻停止层220。可以在与图2I中的半导体器件几乎相同的工艺中形成图3的半导体器件,仅当处于图2C中的操作时,保护层230仅形成在上覆衬底200的蚀刻停止层220上方,而不覆盖栅极结构216。可通过沉积、光刻图案化和蚀刻工艺和/或它们的组合形成保护层230。在一些实施例中,可通过PVD或其它沉积方法通过不良的阶梯式覆盖(poorsidewall step coverage)形成保护层230,随后进行各向同性蚀刻(诸如湿法蚀刻)。
根据本发明的各个实施例,提供了制造半导体器件的机制。所公开的半导体器件可通过形成与栅极结构部分重叠但不具有接触件与栅极的短路问题的接触塞来扩展接触塞的顶面。在上覆衬底的蚀刻停止层上方所形成的保护层可保护衬底在退火操作的过程中不被氧气氧化,因此可减小蚀刻停止层的厚度以避免在接触开口形成操作的过程中过蚀刻隔离层而产生接触件与栅极的短路问题。
根据本发明的各个实施例,半导体器件包括:衬底;位于衬底上方的栅极结构,包括位于衬底上方的栅极介电层、位于栅极介电层上方的栅电极、位于栅电极上方的隔离层及紧邻栅电极的两侧的一对间隔件;在衬底中邻近一对间隔件的源极/漏极区;紧邻一对间隔件并上覆衬底的蚀刻停止层;延伸到源极/漏极区中并穿过间隔件与栅极结构部分重叠的接触塞;位于上覆衬底的蚀刻停止层上方并覆盖紧邻间隔件的蚀刻停止层(而不覆盖接触塞)的保护层;以及位于保护层上方的层间介电层。
根据本发明的各个实施例,半导体器件包括:衬底;位于衬底上方的栅极结构,包括位于衬底上方的栅极介电层、位于栅极介电层上方的栅电极、位于栅电极上方的隔离层及紧邻栅电极的两侧的一对间隔件;在衬底中邻近一对间隔件的源极/漏极区;紧邻一对间隔件并上覆衬底的蚀刻停止层;延伸到源极/漏极区中并穿过间隔件与栅极结构部分重叠的接触塞;位于上覆衬底的蚀刻停止层上方的保护层;以及位于保护层上方的层间介电层。
根据本发明的各个实施例,制造半导体器件的方法包括以下操作。在衬底上方形成具有伪栅电极的栅极结构和邻近伪栅极结构的源极/漏极区。在衬底上方沉积蚀刻停止层。在蚀刻停止层上方沉积保护层。在蚀刻停止层上方沉积层间介电层。对层间介电层进行抛光和退火。通过替换伪栅极结构的一部分形成金属栅极结构。在金属栅极结构上方沉积隔离层。形成穿过层间介电层到达源极/漏极区和隔离层的接触开口。此外,在接触开口中形成接触塞。
上面概述了若干实施例的部件,使得本领域普通技术人员可以更好地理解本发明的各个方面。本领域普通技术人员应该理解,可以很容易地使用本发明作为基础来设计或更改其他用于达到与这里所介绍实施例相同的目的和/或实现相同优点的其他工艺和结构。本领域普通技术人员也应该意识到,这种等效构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,可以进行多种变化、替换以及改变。
Claims (19)
1.一种半导体器件,包括:
衬底;
栅极结构,位于所述衬底上方,包括:
栅极介电层,位于所述衬底上方;
栅电极,位于所述栅极介电层上方;
隔离层,位于所述栅电极上方;以及
一对间隔件,紧邻所述栅电极的两侧;
源极/漏极区,邻近所述一对间隔件位于所述衬底中;
蚀刻停止层,紧邻所述一对间隔件并上覆所述衬底;
接触塞,延伸到所述源极/漏极区中并穿过所述间隔件与所述栅极结构部分地重叠;
保护层,位于上覆所述衬底的蚀刻停止层的上方并覆盖紧邻所述间隔件而没有所述接触塞的所述蚀刻停止层;以及
层间介电层,位于所述保护层上方。
2.根据权利要求1所述的半导体器件,其中,所述层间介电层的材料的折射率在2.5至4的范围内。
3.根据权利要求2所述的半导体器件,其中,所述层间介电层的材料为可流动性氧化物。
4.根据权利要求1所述的半导体器件,其中,所述栅电极为金属电极且所述栅极介电层为高k介电层。
5.根据权利要求1所述的半导体器件,其中,所述保护层的材料的折射率可在1.4至2的范围内。
6.根据权利要求5所述的半导体器件,其中,所述保护层的材料选自包含SiON、SiOCN和SiO2的组。
7.根据权利要求1所述的半导体器件,其中,所述保护层的厚度在1nm至5nm的范围内。
8.根据权利要求1所述的半导体器件,其中,所述蚀刻停止层的厚度在1nm至15nm的范围内。
9.根据权利要求1所述的半导体器件,其中,所述蚀刻停止层的材料包含Si3N4或SiN。
10.根据权利要求1所述的半导体器件,其中,所述隔离层的材料包含SiN。
11.根据权利要求1所述的半导体器件,其中,所述蚀刻停止层的厚度小于所述隔离层的厚度。
12.一种半导体器件,包括:
衬底;
栅极结构,位于所述衬底上方,包括:
栅极介电层,位于所述衬底上方;
栅电极,位于所述栅极介电层上方;
隔离层,位于所述栅电极上方;以及
一对间隔件,紧邻所述栅电极的两侧;
源极/漏极区,邻近所述一对间隔件位于所述衬底中;
蚀刻停止层,紧邻所述一对间隔件并上覆所述衬底;
接触塞,延伸到所述源极/漏极区中并穿过所述间隔件与所述栅极结构部分地重叠;
保护层,位于上覆所述衬底的蚀刻停止层的上方;以及
层间介电层,位于所述保护层上方。
13.根据权利要求12所述的半导体器件,其中,所述保护层的材料选自包含SiON、SiOCN和SiO2的组。
14.根据权利要求12所述的半导体器件,其中,所述保护层的厚度在1nm至5nm的范围内。
15.根据权利要求12所述的半导体器件,其中,所述蚀刻停止层的厚度在1nm至15nm的范围内。
16.一种制造半导体器件的方法,包括:
形成具有伪栅电极的栅极结构并且邻近衬底上方的伪栅极结构形成源极/漏极区;
将蚀刻停止层沉积在所述衬底上方;
将保护层沉积在所述蚀刻停止层上方;
将层间介电层沉积在所述蚀刻停止层上方;
将所述层间介电层进行抛光并退火;
通过替换所述伪栅极结构的一部分形成金属栅极结构;
将隔离层沉积在所述金属栅极结构上方;
形成穿过所述层间介电层并到达所述源极/漏极区和所述隔离层的接触开口;以及
在所述接触开口中形成接触塞;
其中,形成穿过所述层间介电层到达所述源极/漏极区和所述隔离层的所述接触开口包括:蚀刻紧邻间隔件的所述层间介电层和所述保护层的一部分;以及蚀刻所述蚀刻停止层的一部分以接触所述源极/漏极区。
17.根据权利要求16所述的方法,其中,通过替换所述伪栅极结构的一部分形成所述金属栅极结构包括:
去除所述伪栅电极;
将栅极介电层沉积在栅极结构中;
将功函层沉积在所述栅极介电层上方;以及
在所述功函层上方形成金属电极。
18.根据权利要求16所述的方法,其中,将所述保护层沉积在所述蚀刻停止层上方,所述保护层的厚度在1nm至5nm的范围内。
19.根据权利要求16所述的方法,其中,将所述层间介电层沉积在所述蚀刻停止层上方,所述层间介电层的材料包括可流动性氧化物。
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