CN113410215A - 半导体封装结构及其制备方法 - Google Patents

半导体封装结构及其制备方法 Download PDF

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Publication number
CN113410215A
CN113410215A CN202110251462.0A CN202110251462A CN113410215A CN 113410215 A CN113410215 A CN 113410215A CN 202110251462 A CN202110251462 A CN 202110251462A CN 113410215 A CN113410215 A CN 113410215A
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die
package substrate
active side
element die
component
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CN202110251462.0A
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CN113410215B (zh
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杨吴德
尤俊煌
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Nanya Technology Corp
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Nanya Technology Corp
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Abstract

本公开提供一种半导体封装结构及其制备方法。该半导体封装结构具有一第一元件裸片、多个第一电连接件、一第二元件裸片以及多个第二电连接件。该第一元件裸片贴合到一封装基底。该第一元件裸片的一主动侧面朝该封装基底。多个第一电连接件连接该第一元件裸片的该主动侧到该封装基底。该第二元件裸片的一主动侧面朝该封装基底。该第二元件裸片的该主动侧的一部分位于一区域外，该区域为重叠该第一元件裸片。多个所述第二电连接件连接该第二元件裸片的该主动侧的该部分到该封装基底。

Description

半导体封装结构及其制备方法
本发明主张2020年3月16日申请的美国正式申请案第16/819,709号的优先权及益处，该美国正式申请案的内容以全文引用的方式并入本文中。
技术领域
本公开涉及一种半导体封装结构及其制备方法。尤其涉及一种三维半导体封装结构及其制备方法。
背景技术
由于各种电子元件的集成密度的不断改善，所以半导体产业经历了持续的增长。此等改善主要来自最小特征尺寸的不断减小，从而允许将更多元件整合到一给定的芯片面积中。
因为集成元件所占据的体积基本上在半导体晶片的表面上，所以这些整合的改善本质上是二维的(2D)。虽然光刻技术的显著改善已导致在二维集成电路形成中的显著改进，但是其可在二维所达到的密度仍是有实体上的限制。当二维的缩放(scaling)仍是一些新设计的一选项，但采用利用z方向的三维封装组合已成为业界研究的重点。
上文的“现有技术”说明仅提供背景技术，并未承认上文的“现有技术”说明公开本公开的标的，不构成本公开的现有技术，且上文的“现有技术”的任何说明均不应作为本发明的任一部分。
发明内容
本公开的目的在于提供一种半导体封装结构及其制备方法，以解决上述至少一个问题。
本公开的一实施例提供一种半导体封装结构。该半导体封装结构包括一第一元件裸片，贴合到一封装基底，其中该第一元件裸片的一主动侧面朝该封装基底；多个第一电连接件，连接该第一元件裸片的该主动侧到该封装基底；一第二元件裸片，堆叠到该第一元件裸片上，其中该第二元件裸片的一主动侧面朝该封装基底，且该第二元件裸片的该主动侧的一部分位于一区域，该区域重叠该第一元件裸片；以及多个第二电连接件，连接该第二元件裸片的该主动侧的该部分到该封装基底。
在本公开的一些实施例中，多个所述第二电连接件具有一高度，大于多个所述第一电连接件的一高度。
在本公开的一些实施例中，该半导体封装结构还包括：一第一粘贴材料，设置在该第一元件裸片与该封装基底之间；以及一第二粘贴材料，设置在该第一元件裸片与该第二元件裸片之间。
在本公开的一些实施例中，该第一元件裸片的一部分并未被该第二粘贴材料所覆盖。
在本公开的一些实施例中，多个所述第一电连接件分别包括一第一导电柱以及一第一焊料接头(first solder joint)，该第一焊料接头连接该第一导电柱到该封装基底，而多个所述第二电连接件分别包括一第二导电柱以及一第二焊料接头，该第二焊料接头连接该第二导电柱到该封装基底。
在本公开的一些实施例中，多个所述第二导电柱具有一高度，大于多个所述第一导电柱的一高度。
在本公开的一些实施例中，该封装基底包括多个积层介电层的一堆叠以及多个导电图案的多层，而多个所述导电图案的该多层分别形成在其中一积层介电层的一侧。
在本公开的一些实施例中，该半导体封装结构还包括一囊封体(encapsulant)，侧向地囊封该第一元件裸片、该第二元件裸片、多个所述第一电连接件以及多个所述第二电连接件。
在本公开的一些实施例中，该囊封体的一侧壁大致地与该封装基底的一侧壁共面。
在本公开的一些实施例中，该半导体封装结构还包括多个封装输入/输出(package inputs/outputs(I/Os))，形成在该封装基底面向远离该第一元件裸片与该第二元件裸片的一侧处。
本公开的一实施例提供一种半导体封装结构。该半导体封装结构包括一第一元件裸片，贴合到一封装基底，其中该第一元件裸片的一主动侧面朝该封装基底；多个第一电连接件，连接该第一元件裸片的该主动侧到该封装基底；一第二元件裸片，堆叠在该第一元件裸片上，且在该第二元件裸片的一主动侧处具有多个导电垫以及多个重分布结构，其中该第二元件裸片的该主动侧面朝该封装基底，多个所述导电垫位于该第二元件裸片的该主动侧重叠该第一元件裸片的一中心区内，且多个所述重分布结构连接多个所述导电垫到该第二元件裸片的该主动侧未重叠该第一元件裸片的一周围区；以及多个第二电连接件，连接该封装基底到该重分布结构位于该第二元件裸片的该主动侧的该周围区内的一些部分。
在本公开的一些实施例中，多个所述重分布结构分别包括：一重分布垫，位于该第二元件裸片的该主动侧的该周围区内；以及一导电线，连接该重分布垫到其中一导电垫。
在本公开的一些实施例中，多个所述第二电连接件连接多个所述重分布垫到该封装基底。
在本公开的一些实施例中，该第一元件裸片具有多个导电垫，形成在该第一元件裸片的该主动侧处，且多个所述第一电连接件连接该第一元件裸片的多个所述导电垫到该封装基底。
本公开的一实施例提供一种半导体封装结构的制备方法。该制备方法包括贴合一第一元件裸片到一封装基底，其中该贴合的第一元件裸片的一主动侧面朝该封装基底，多个第一电连接件在该第一元件裸片的贴合前，即预先形成在该第一元件裸片的该主动侧上，且多个所述第一电连接件在该第一元件裸片的贴合之后，即连接该第一元件裸片的该主动侧到该封装基底；以及贴合一第二元件裸片到该第一元件裸片与该封装基底，其中该贴合的第二元件裸片的一主动侧面朝该第一元件裸片与该封装基底，该贴合的第二元件裸片的该主动侧的一部分位于一区域外，该区域重叠该贴合的第一元件裸片，多个第二电连接件在该第二元件裸片的贴合之前，即预先形成在该第二元件裸片的该主动侧的该部分，且多个所述第二电连接件在该第二元件裸片的贴合之后，即连接该第二元件裸片的该主动侧的该部分到该封装基底。
在本公开的一些实施例中，该制备方法还包括在该第一元件裸片的贴合之前，即形成一第一粘贴材料在该封装基底上，其中在该第一元件裸片的贴合之后，该第一粘贴材料设置在该封装基底与该第一元件裸片的该主动侧之间。
在本公开的一些实施例中，该制备方法还包括在该第二元件裸片的贴合之前，形成一第二粘贴材料在该第一元件裸片上，其中在该第二元件裸片的贴合之后，该第二粘贴材料位于该第一元件裸片与该第二元件裸片的该主动侧之间。
在本公开的一些实施例中，该第二元件裸片预先形成有多个导电垫与多个重分布结构在该第二元件裸片的该主动侧处，多个所述导电垫位于该第二元件裸片的该主动侧重叠该第一元件裸片的一中心区内，多个所述重分布结构连接多个所述导电垫到该第二元件裸片的该主动侧位于重叠该第一元件裸片的一区域外的一周围区，且多个所述第二电连接件在该第二元件裸片的贴合之后，即连接多个所述重分布结构到该封装基底。
在本公开的一些实施例中，该制备方法还包括在该第二元件裸片的贴合之后，通过一囊封体而侧向囊封该第一元件裸片与该第二元件裸片。
在本公开的一些实施例中，该制备方法还包括形成多个封装输入/输出在该封装基底面向远离该贴合的第一元件裸片与该贴合的第二元件裸片的一侧处。
如上所述，依据本公开的一些实施例的半导体封装结构具有一下元件裸片以及一上元件裸片，该上元件裸片堆叠在该下元件裸片上。该下元件裸片与该上元件裸片经由多个电连接件而接合到一封装基底，且该下元件裸片与该上元件裸片的各主动侧面朝该封装基底。与其中每个元件裸片的主动侧面向远离该封装基板处并通过多个接合线(bondingwires)而电性连接到该封装基板的一多裸片半导体封装相比，本公开的多个所述电连接件可具有一较小的长度。再者，由于具有多个导电柱而不是多个接合线，所以本公开的多个所述电连接件具有一较厚的直径。因此，可以减小多个所述电连接件的电阻率(resistivity)以及在高频下的多个所述电连接器的阻抗(impedance)，并可改善在裸片堆叠(die stack)(包括该下元件裸片与该上元件裸片)之间的电性连接。
上文已相当广泛地概述本公开的技术特征及优点，以使下文的本公开详细描述得以获得较佳了解。构成本公开的权利要求标的的其它技术特征及优点将描述于下文。本公开所属技术领域中技术人员应了解，可相当容易地利用下文公开的概念与特定实施例可作为修改或设计其它结构或工艺而实现与本公开相同的目的。本公开所属技术领域中技术人员亦应了解，这类等效建构无法脱离随附的权利要求所界定的本公开的精神和范围。
附图说明
参阅实施方式与权利要求合并考虑附图时，可得以更全面了解本发明的公开内容，附图中相同的元件符号是指相同的元件。
图1A为依据本公开一些实施例的一种半导体封装结构的剖视示意图。
图1B为如图1A所示的该半导体封装结构中一上元件裸片的一主动侧的平面示意图。
图1C为如图1A所示的该半导体封装结构中一下元件裸片的一主动侧的平面示意图。
图2为依据本公开一些实施例的该半导体封装结构的制备方法的流程示意图。
图3A到图3F为在如图1A所示的半导体封装结构的制备流程期间在不同阶段的结构的剖视示意图。
图4为依据本公开一些实施例的一种半导体封装结构的剖视示意图。
附图标记如下：
10:半导体封装结构
10a:半导体封装结构
100:下元件裸片
110:上元件裸片
120:封装基底
122:积层介电层
124:导电图案
126:封装输入/输出
130:囊封体
AM1:粘贴材料
AM2:粘贴材料
AP:导电垫
AS1:主动侧
AS2:主动侧
BS1:后侧
BS:后侧
CL:导电线
CP:导电柱
EC:电连接件
RP:重分布垫
RS:重分布结构
SJ:焊料接头
S11:步骤
S13:步骤
S15:步骤
S17:步骤
S19:步骤
S21:步骤
S23:步骤
具体实施方式
本公开的以下说明伴随并入且组成说明书的一部分的附图，说明本公开的实施例，然而本公开并不受限于该实施例。此外，以下的实施例可适当整合以下实施例以完成另一实施例。
“一实施例”、“实施例”、“例示实施例”、“其他实施例”、“另一实施例”等是指本公开所描述的实施例可包含特定特征、结构或是特性，然而并非每一实施例必须包含该特定特征、结构或是特性。再者，重复使用“在实施例中”一语并非必须指相同实施例，然而可为相同实施例。
为了使得本公开可被完全理解，以下说明提供详细的步骤与结构。显然，本公开的实施不会限制该技艺中的技术人士已知的特定细节。此外，已知的结构与步骤不再详述，以免不必要地限制本公开。本公开的较佳实施例详述如下。然而，除了详细说明之外，本公开亦可广泛实施于其他实施例中。本公开的范围不限于详细说明的内容，而是由权利要求定义。
应当理解，以下公开内容提供用于实作本发明的不同特征的诸多不同的实施例或实例。以下阐述组件及排列形式的具体实施例或实例以简化本公开内容。当然，多个仅为实例且不旨在进行限制。举例而言，元件的尺寸并非仅限于所公开范围或值，而是可相依于工艺条件及/或装置的所期望性质。此外，以下说明中将第一特征形成于第二特征“之上”或第二特征“上”可包括其中第一特征及第二特征被形成为直接接触的实施例，且亦可包括其中第一特征与第二特征之间可形成有附加特征、进而使得所述第一特征与所述第二特征可能不直接接触的实施例。为简洁及清晰起见，可按不同比例任意绘制各种特征。在附图中，为简化起见，可省略一些层/特征。
此外，为易于说明，本文中可能使用例如“之下(beneath)”、”下面(below)”、“下部的(lower)”、“上方(above)”、“上部的(upper)”等空间相对关系用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对关系用语旨在除图中所示出的取向外亦囊括元件在使用或操作中的不同取向。所述装置可具有其他取向(旋转90度或处于其他取向)且本文中所用的空间相对关系描述语可同样相应地进行解释。
图1A为依据本公开一些实施例的一种半导体封装结构的剖视示意图。图1B为如图1A所示的该半导体封装结构中一上元件裸片的一主动侧的平面示意图。图1C为如图1A所示的该半导体封装结构中一下元件裸片的一主动侧的平面示意图。
请参考图1A，在一些实施例中，半导体封装结构10为一双裸片半导体封装结构。在这些实施例中，半导体封装结构10可具有一下元件裸片100以及一上元件裸片110，上元件裸片110堆叠在下元件裸片100上。下元件裸片100与上元件裸片110经由一倒装芯片结合(flip chip bonding)程序而均接合到一封装基底120。因此，当上元件裸片110的一后侧BS1与下元件裸片100的一后侧BS2面向远离封装基底120处时，上元件裸片110的一主动侧AS1与下元件裸片100的一主动侧AS2面朝封装基底120，而后侧BS1与后侧BS2相对主动侧AS1与主动侧AS2设置。一元件裸片的主动侧(例如上元件裸片110的主动侧AS1或下元件裸片100的主动侧AS2)表示该元件裸片在有多个导电垫AP形成在其上的一侧。多个导电垫AP当成是形成在该元件裸片中的一集成电路的多个输入/输出的功能，并可经由多个内连接结构(图未示)而电性连接到多个主动/被动元件。在一些实施例中，上元件裸片110与下元件裸片100为存储器裸片，例如动态随机存取存储器(DRAM)裸片。此外，就电路与尺寸而言，上元件裸片110可大致与下元件裸片100相同。或者是，就电路、尺寸以及其他特征而言，上元件裸片110与下元件裸片100可相互不同。
上元件裸片110从下元件裸片100侧向偏移，以使上元件裸片110的一周围部位于一区域外，而该区域重叠下元件裸片100，也因此上元件裸片110可经由该周围部而接合到封装基底120。在一些实施例中，上元件裸片110与下元件裸片100通过多个电连接件EC而接合到封装基底120。多个电连接件EC可分别具有一导电柱CP以及一焊料接头SJ。导电柱CP的一端子(terminal)连接到其中一导电垫AP，且导电柱CP的另一端子经由焊料接头SJ而连接到封装基底120。因为在上元件裸片110与封装基底120间的一垂直空间大于在下元件裸片100与封装基底120之间的一垂直空间，所以连接上元件裸片110到封装基底120的多个导电柱CP高于连接下元件裸片100到封装基底120的多个导电柱CP。在一些实施例中，当连接下元件裸片100到封装基底120的多个导电柱CP的一高度介于30到190μm时，连接上元件裸片110到封装基底120的多个导电柱CP的一高度可介于50到250μm之间。在一些实施例中，当各焊料接头SJ由一焊锡材料(solder material)所制时，导电柱CP的一材料可包含金属(例如铜或铜合金)。然而，本公开并不以此为限，且所属技术领域中技术人员可依据工艺所需改良多个电连接件EC的尺寸与材料。
请参考图1A、图1B以及图1C，在一些实施例中，多个导电垫AP形成在上元件裸片110与下元件裸片100的中心部。举例来说，如图1B所示，在上元件裸片110的中心部内的多个导电垫AP配置成两行。类似地，如图1C所示，在下元件裸片100的中心部内的多个导电垫AP可配置成两行。然而，本公开并未以此为限，且所属技术领域中技术人员可依据设计需求而改良多个导电垫AP的配置。在一些实施例中，如图1A与图1B所示，连接上元件裸片110的周围部到封装基底120的多个电连接件EC，可从在上元件裸片110的中心部内的多个导电垫AP侧向偏移。一重分布结构RS可形成在上元件裸片110的主动侧AS1上，以将上元件裸片110的多个导电垫AP布线到上元件裸片110的周围部，以便可建立位于上元件裸片110内的多个导电垫AP与连接到上元件裸片110的多个导电柱CP之间的一电连接。在一些实施例中，多个重分布结构RS分别具有一导电线CL以及一重分布垫RP。导电线CL从上元件裸片110的其中一导电垫AP延伸到其中一重分布垫RP。举例来说，如图1A所示，导电线CL从上元件裸片110的其中一导电垫AP的一下表面延伸，且侧向接触其中一重分布垫RP。如图1B所示，导电线CL可形成如当作一直线(straight line)，或可沿其延伸方向而具有至少一转弯(turn)。另一方面，连接下元件裸片100到封装基底120的多个电连接件EC延伸到下元件裸片100的中心部，并接触下元件裸片100没有一重分布结构在其间的多个导电垫AP。换言之，下元件裸片100的多个导电垫AP重叠连接到下元件裸片100的多个导电垫AP的多个电连接件EC。
请参考图1A、图1B以及图1C，一粘贴材料AM1设置在下元件裸片100与封装基底120之间，以及一粘贴材料AM2设置在上元件裸片110与下元件裸片100之间。如图1A与图1B所示，粘贴材料AM2并未覆盖上元件裸片110的整个主动侧AS1。反而是，粘贴材料AM2覆盖上元件裸片110的一部分，该部分重叠下元件裸片100，但粘贴材料AM2并未延伸到上元件裸片110的周围部，而一些电连接件EC连接到上元件裸片110的周围部。因此，当每一导电线CL的余留部分以及多个重分布垫RP未被粘贴材料AM2所覆盖时，在上元件裸片110的中心部内的多个导电垫AP与每一导线CL连接此等导电垫AP到多个重分布垫RP的一部分，被粘贴材料AM2所覆盖。应当理解，虽然粘贴材料AM2被描述成具有对准上元件裸片110的各边缘的多个边缘，但是粘贴材料AM2的此等边缘可交错地侧向从上元件裸片110的此等边缘突出或凹陷。另一方面，如图1A与图1C所示，覆盖下元件裸片100的主动侧AS2的粘贴材料AM1，设置在多个导电垫AP位于下元件裸片100的主动侧AS2的相对侧，且并未覆盖此等导电垫AP。在一些实施例中，粘贴材料AM1具有二分离的子部分，每一个设置在多个导电垫AP位于下元件裸片100的主动侧AS2的一侧。应当理解，虽然粘贴材料AM1描述成具有对准下元件裸片100的各边缘的多个边缘，但是粘贴材料AM1的此等边缘可交错地侧向从下元件裸片100的此等边缘突出或凹陷。
请参考图1A，封装基底120可为一积层基底(built-up substrate)。在一些实施例中，积层基底为一无核心(core-less)积层基底，且具有多个积层介电层122的一堆叠以及多个导电图案124的多层，其分别形成在其中一积层介电层122的一侧。多个导电图案124的各层可具有至少一层接地面(ground plane)、至少一层电源面(power plane)以及至少一信号面(signal plane)与连接多个电连接件EC到形成在封装基底120的下侧处的接地面、电源面、信号面以及多个封装输入/输出126的多个布线结构。当最下方的导电图案124接触多个封装输入/输出126时，最上方的导电图案124接触多个电连接件EC。在特定实施例中，一信号面跨越在一接地面与一电源面之间。多个布线结构可具有多个导电迹线(conductive traces)以及多个导电通孔(conductive vias)。当多个导电通孔分别穿过一或多个积层介电层122并电性连接多个电连接件EC到接地面、信号面、电源面或多个封装输入/输出126时，多个导电迹线分别延伸在其中一积层介电层122的一表面上。因此，一些导电通孔可穿经多个积层介电层122的整个堆叠，并可表示成导电贯穿通孔(conductivethrough vias)。接地面电性接地或经配置以接收一参考电压。电源面经配置以接收一或多个电源供应电压(power supply voltage(s))。信号面可经配置以传送在裸片堆叠与多个封装输入/输出126之间的输入/输出信号。在一些实施例中，多个封装输入/输出126可为球状栅格阵列(ball grid array，BGA)球、受控塌陷芯片连接(controlled-collapse-chip-connection，C4)凸块或其类似物。
或者是，封装基底120可具有一刚性介电核心层(rigid dielectric corelayer)。在此等其他实施例中，如图1A所示的其中一积层介电层122可被介电核心层所取代。举例来说，多个积层介电层122的该堆叠的中间一个可被介电核心层所取代。介电核心层可具有一厚度，甚大于每一积层介电层122的一厚度。因此，可改善封装基底120的机械强度。另一方面，如图1A所示的无核心积层基底可具有优点，例如重量轻以及Z方向的低高度。
请参考图1A，半导体封装结构10还具有一囊封体(encapsulant)130。囊封体130侧向囊封裸片堆叠，而裸片堆叠包括上元件裸片110与下元件裸片100。此外，囊封体130填满上元件裸片110与封装基底120之间的空间，并填满下元件裸片100与封装基底120之间的空间。因此，每一电连接件EC侧向地被囊封体130所围绕。在一些实施例中，裸片堆叠(包括上元件裸片110与下元件裸片100)被囊封体130所过度膜封(over-molded)。在此等实施例中，上元件裸片110的一上表面被囊封体130的一上部所覆盖。此外，在一些实施例中，囊封体130的一侧壁大致与封装基底120的一侧壁为共面。囊封体130具有一模塑化合物(moldingcompound)，例如环氧树脂(epoxy resin)。在一些实施例中，囊封体130还具有多个填充粒子(filler particles)(图未示)，分散在模塑化合物中。多个填充粒子可典型地由一非有机材料(inorganic material)(例如硅石(silica))所制，并经配置以改良囊封体130的材料特性(例如热膨胀系数(coefficient of thermal expansion，CTE))。
如上所述，依据本公开的一些实施例的半导体封装结构10为一双裸片半导体封装，并具有下元件裸片100与上元件裸片110，而上元件裸片110堆叠在下元件裸片100上。下元件裸片100与上元件裸片110经由多个电连接件EC而接合到封装基底120，且下元件裸片100的主动侧AS2与上元件裸片110的主动侧AS1均朝向封装基底120。当相较于位于每一元件裸片面向远离一封装基底并经由多个接合线(bonding wires)而电性连接到封装基底处的一主动侧的一多裸片半导体封装时，本公开的多个电连接件EC可具有一较小长度。再者，多个电连接件EC可具有一较厚的直径，所以具有多个导电柱CP，而不是多个接合线。因此，可降低多个电连接件EC的电阻率以及多个电连接件EC在高频下的阻抗，并可改善在裸片堆叠(包括下元件裸片100与上元件裸片110)之间的电性连接。为了实现在多个元件裸片与封装基底120之间如此的电性连接，上元件裸片110可从下元件裸片100侧向偏移，且连接到上元件裸片110的多个电连接件EC可具有一垂直长度，大于连接到下元件裸片100的多个电连接件EC的一垂直长度。换言之，具有不同垂直长度的多个电连接件EC用于连接在裸片堆叠中的多个元件裸片到封装基底120。
在其他的实施例中，裸片堆叠可具有三或多个元件裸片。换言之，附加的元件裸片(图未示)可进一步堆叠在上元件裸片110上。如此附加的元件裸片可从下层的一个侧向偏移，且经由多个电连接件而电性连接到封装基底120，多个电连接件类似于如上所述的多个电连接件EC。
图2为依据本公开一些实施例如图1A所示的该半导体封装结构的制备方法的流程示意图。图3A到图3F为在如图1A所示的半导体封装结构的制备流程期间在不同阶段的结构的剖视示意图。
请参考图2及图3A，执行步骤S11，并准备封装基底120。在一些实施例中，封装基底120为一无核心积层基底。在如此的实施例中，多个积层介电层122以及多个导电图案124的多层交错地形成在一载体(carrier)(图未示)上。每一积层介电层122的形成包括叠层工艺(lamination process)。此外，多个导电图案124的每一层的形成可包括一光刻(lithography)工艺以及一镀覆(plating)工艺，且还可包括一蚀刻工艺，其用于形成多个导电通孔在下层积层介电层122中。接着，载体(图未示)可从形成上述的结构剥离(debonded)，且余留的结构形成封装基底120。在其他的实施例中，封装基底120具有一核心介电层。在如此的实施例中，多个积层介电层122与多个导电图案124的各层形成在核心介电层的一单一侧或两相对侧上，且一导电贯穿通孔可通过一钻孔(drilling)工艺(例如激光钻孔工艺)而形成在核心介电层中。
请参考图2及图3B，执行步骤S13，且粘贴材料AM1提供在封装基底120的一上侧上。在一些实施例中，粘贴材料AM1施加在封装基底120上。如参考图1A及图1C所描述的，可形成粘贴材料AM1当作二分离子部分。封装基底120的一些最上方的导电图案可暴露在粘贴材料AM1的多个子部分之间的一空间中，以便贴合多个电连接件EC，而多个电连接件EC连接到在接下来的步骤中的下元件裸片100(如图3C所示)。
请参考图2及图3C，执行步骤S15，且下元件裸片100经由一些电连接件EC而贴合到封装基底120。在一些实施例中，多个电连接件EC预先形成在下元件裸片100的多个导电垫AP上，且多个电连接件EC贴合到多个导电图案124暴露在粘贴材料AM1的多个子部分之间的部分。与此同时，下元件裸片100的主动侧AS2的其他部分接触粘贴材料AM1。在一些实施例中，一拾取及放置工艺(pick and place process)用于贴合下元件裸片100到封装基底120。此外，可接着执行一热处理，以接合下元件裸片100到封装基底120。
在其他实施例中，在下元件裸片100接合到封装基底120之前，粘贴材料AM1可提供在下元件裸片100的主动侧AS2上。
请参考图2及图3D，执行步骤S17，且粘贴材料AM2提供在下元件裸片100的后侧BS2上。如参考图1A及图1B所描述的，在一些实施例中，粘贴材料AM2并非必须覆盖下元件裸片100的整个后侧BS2，原因是接下来要贴合的上元件裸片110从下元件裸片100侧向偏移。举例来说，如图3D所示，下元件裸片100的后侧BS2的一左周围区并未被粘贴材料AM2所覆盖。在一些实施例中，用于提供粘贴材料AM2的一方法包括一点胶工艺(dispensing process)。
请参考图2及图3E，执行步骤S19，且上元件裸片110贴合到下元件裸片100与封装基底120。上元件裸片110的主动侧AS1面朝下元件裸片100与封装基底120。上元件裸片110的一部分经由粘贴材料AM2而贴合到下元件裸片100，而上元件裸片110的其他部分经由一些电连接件EC而接触封装基底120。在一些实施例中，如此的电连接件EC预先形成在多个重分布结构RS的多个重分布垫RP上，而多个重分布结构RS经配置以布线在上元件裸片110的一中心区内的多个导电垫AP到上元件裸片110的一周围区，且多个电连接件EC贴合到封装基底120的多个导电图案124的最上方的部分。在如此的实施例中，多个导电垫AP与多个重分布结构RS的一些部分(例如多个导电线CL的一些部分)可嵌设在粘贴材料AM2中。在一些实施例中，一拾取及放置工艺用于贴合上元件裸片110到下元件裸片100以及封装基底120。此外，可接着执行一热处理，以接合上元件裸片110到封装基底120。
在其他实施例中，在上元件裸片110接合到下元件裸片100与封装基底120之前，粘贴材料AM2可提供在上元件裸片110的主动侧AS1上。
请参考图2及图3F，执行步骤S21，且下元件裸片100与上元件裸片110被囊封体130所囊封。在一些实施例中，一转移模塑(transfer-molding)工艺、一压缩模塑(compression-molding)工艺或其他可行的模塑工艺可用来形成囊封体130。
请参考图2及图1A，执行步骤S23，以便形成多个封装输入/输出126，并执行一单体化工艺(singulation process)。多个封装输入/输出126形成在封装基底120的下表面处，且电性接触多个导电图案124的下部。在一些实施例中，用于形成多个封装输入/输出126的一方法包括一植球工艺(ball placement process)或其他可行的工艺。执行单体化工艺以形成半导体元件10如同其中一单体化结构，而单体化工艺例如刀片切割工艺(bladesawing process)、一等离子体切割工艺(plasma-dicing process)或其类似工艺。在一些实施例中，多个封装输入/输出126的形成先于单体化工艺。然而，在其他实施例中，单体化工艺随着在多个封装输入/输出126的形成之后。
因此，完成依据一些实施例的半导体封装结构10。
图4为依据本公开一些实施例的一种半导体封装结构10a的剖视示意图。半导体封装结构10a类似于如图1A所示的半导体封装结构10；将仅描述其差异处，且类似或相同的部分在文中不再重复描述。
请参考图4，在一些实施例中，下元件裸片100的多个导电垫AP形成在下元件裸片100的主动的AS2的一周围区内。在如此的实施例中，粘贴材料AM1覆盖下元件裸片100的主动侧AS2的余留部分，形成如同一连续图案，而不是如同多个分开的子图案。类似地，上元件裸片110的多个导电垫AP形成在上元件裸片110的主动侧AS1的一周围区内。结果，可省略如参考图1A及图1B所描述的多个重分布结构RS，且连接上元件裸片110到封装基底120的多个电连接件EC取代多个重分布电RP(如图1A与图1B所示)而接触多个导电垫AP。在一些实施例中，如图4所示，连接到上元件裸片110的多个电连接件EC以及连接到下元件裸片100的多个电连接件EC位于裸片堆叠的相同侧。然而，在其他实施例中，连接到上元件裸片110的多个电连接件EC以及连接到下元件裸片100的多个电连接件EC位于裸片堆叠的不同侧。在一些其他实施例中，上元件裸片110的多个导电垫AP位于如图1A及图1B所示的上元件裸片的一中心部内，且下元件裸片100的多个导电垫AP位于如图4所示的下元件裸片100的周围区内。
如上所述，依据本公开的一些实施例的半导体封装结构具有一下元件裸片以及一上元件裸片，而上元件裸片堆叠在下元件裸片上。下元件裸片与上元件裸片经由多个电连接件而接合到一封装基底，且下元件裸片与上元件裸片的主动侧均面朝封装基底。当相较于位于每一元件裸片面向远离一封装基底并经由多个接合线而电性连接到封装基底处的一主动侧中的一多裸片半导体封装时，本公开的多个电连接件可具有一较小长度。再者，本公开的多个电连接件可具有一较厚的直径，原因是具有多个导电柱，而不是多个接合线。因此，可降低多个电连接件的电阻率以及多个电连接件在高频下的阻抗，并可改善在裸片堆叠(包括下元件裸片100与上元件裸片110)之间的电性连接。
本公开的一实施例提供一种半导体封装结构。该半导体封装结构包括一第一元件裸片，贴合到一封装基底，其中该第一元件裸片的一主动侧面朝该封装基底；多个第一电连接件，连接该第一元件裸片的该主动侧到该封装基底；一第二元件裸片，堆叠到该第一元件裸片上，其中该第二元件裸片的一主动侧面朝该封装基底，且该第二元件裸片的该主动侧的一部分位于一区域，该区域重叠该第一元件裸片；以及多个第二电连接件，连接该第二元件裸片的该主动侧的该部分到该封装基底。
本公开的一实施例提供一种半导体封装结构。该半导体封装结构包括一第一元件裸片，贴合到一封装基底，其中该第一元件裸片的一主动侧面朝该封装基底；多个第一电连接件，连接该第一元件裸片的该主动侧到该封装基底；一第二元件裸片，堆叠在该第一元件裸片上，且在该第二元件裸片的一主动侧处具有多个导电垫以及多个重分布结构，其中该第二元件裸片的该主动侧面朝该封装基底，多个导电垫位于该第二元件裸片的该主动侧重叠该第一元件裸片的一中心区内，且多个重分布结构连接多个导电垫到该第二元件裸片的该主动侧未重叠该第一元件裸片的一周围区；以及多个第二电连接件，连接该封装基底到该重分布结构位于该第二元件裸片的该主动侧的该周围区内的一些部分。
本公开的一实施例提供一种半导体封装结构的制备方法。该制备方法包括贴合一第一元件裸片到一封装基底，其中该贴合的第一元件裸片的一主动侧面朝该封装基底，多个第一电连接件在该第一元件裸片的贴合前，即预先形成在该第一元件裸片的该主动侧上，且多个第一电连接件在该第一元件裸片的贴合之后，即连接该第一元件裸片的该主动侧到该封装基底；以及贴合一第二元件裸片到该第一元件裸片与该封装基底，其中该贴合的第二元件裸片的一主动侧面朝该第一元件裸片与该封装基底，该贴合的第二元件裸片的该主动侧的一部分位于一区域外，该区域重叠该贴合的第一元件裸片，多个第二电连接件在该第二元件裸片的贴合之前，即预先形成在该第二元件裸片的该主动侧的该部分，且多个第二电连接件在该第二元件裸片的贴合之后，即连接该第二元件裸片的该主动侧的该部分到该封装基底。
虽然已详述本公开及其优点，然而应理解可进行各种变化、取代与替代而不脱离权利要求所定义的本公开的精神与范围。例如，可用不同的方法实施上述的许多工艺，并且以其他工艺或其组合替代上述的许多工艺。
再者，本发明的范围并不受限于说明书中所述的工艺、机械、制造、物质组成物、手段、方法与步骤的特定实施例。本领域技术人员可自本公开的公开内容理解可根据本公开而使用与本文所述的对应实施例具有相同功能或是达到实质上相同结果的现存或是未来发展的工艺、机械、制造、物质组成物、手段、方法、或步骤。据此，此等工艺、机械、制造、物质组成物、手段、方法、或步骤包含于本发明的权利要求内。

Claims (20)

1.一种半导体封装结构，包括：
一第一元件裸片，贴合到一封装基底，其中该第一元件裸片的一主动侧面朝该封装基底；
多个第一电连接件，连接该第一元件裸片的该主动侧到该封装基底；
一第二元件裸片，堆叠到该第一元件裸片上，其中该第二元件裸片的一主动侧面朝该封装基底，且该第二元件裸片的该主动侧的一部分位于一区域，该区域重叠该第一元件裸片；以及
多个第二电连接件，连接该第二元件裸片的该主动侧的该部分到该封装基底。
2.如权利要求1所述的半导体封装结构，其中多个所述第二电连接件具有一高度，大于多个所述第一电连接件的一高度。
3.如权利要求1所述的半导体封装结构，还包括：
一第一粘贴材料，设置在该第一元件裸片与该封装基底之间；以及
一第二粘贴材料，设置在该第一元件裸片与该第二元件裸片之间。
4.如权利要求3所述的半导体封装结构，其中该第一元件裸片的一部分并未被该第二粘贴材料所覆盖。
5.如权利要求1所述的半导体封装结构，其中多个所述第一电连接件分别包括一第一导电柱以及一第一焊料接头，该第一焊料接头连接该第一导电柱到该封装基底，而多个所述第二电连接件分别包括一第二导电柱以及一第二焊料接头，该第二焊料接头连接该第二导电柱到该封装基底。
6.如权利要求5所述的半导体封装结构，其中多个所述第二导电柱具有一高度，大于多个所述第一导电柱的一高度。
7.如权利要求1所述的半导体封装结构，其中该封装基底包括多个积层介电层的一堆叠以及多个导电图案的多层，而多个所述导电图案的该多层分别形成在其中一积层介电层的一侧。
8.如权利要求1所述的半导体封装结构，还包括一囊封体，侧向地囊封该第一元件裸片、该第二元件裸片、多个所述第一电连接件以及多个所述第二电连接件。
9.如权利要求8所述的半导体封装结构，其中该囊封体的一侧壁与该封装基底的一侧壁共面。
10.如权利要求1所述的半导体封装结构，还包括多个封装输入/输出，形成在该封装基底面向远离该第一元件裸片与该第二元件裸片的一侧处。
11.一种半导体封装结构，包括：
一第一元件裸片，贴合到一封装基底，其中该第一元件裸片的一主动侧面朝该封装基底；
多个第一电连接件，连接该第一元件裸片的该主动侧到该封装基底；
一第二元件裸片，堆叠在该第一元件裸片上，且在该第二元件裸片的一主动侧处具有多个导电垫以及多个重分布结构，其中该第二元件裸片的该主动侧面朝该封装基底，多个所述导电垫位于该第二元件裸片的该主动侧重叠该第一元件裸片的一中心区内，且多个所述重分布结构连接多个所述导电垫到该第二元件裸片的该主动侧未重叠该第一元件裸片的一周围区；以及
多个第二电连接件，连接该封装基底到该重分布结构位于该第二元件裸片的该主动侧的该周围区内的一些部分。
12.如权利要求11所述的半导体封装结构，其中多个所述重分布结构分别包括：
一重分布垫，位于该第二元件裸片的该主动侧的该周围区内；以及
一导电线，连接该重分布垫到其中一导电垫。
13.如权利要求12所述的半导体封装结构，其中多个所述第二电连接件连接多个所述重分布垫到该封装基底。
14.如权利要求11所述的半导体封装结构，其中该第一元件裸片具有多个导电垫，形成在该第一元件裸片的该主动侧处，且多个所述第一电连接件连接该第一元件裸片的多个所述导电垫到该封装基底。
15.一种半导体封装结构的制备方法，包括：
贴合一第一元件裸片到一封装基底，其中该贴合的第一元件裸片的一主动侧面朝该封装基底，多个第一电连接件在该第一元件裸片的贴合前，即预先形成在该第一元件裸片的该主动侧上，且多个所述第一电连接件在该第一元件裸片的贴合之后，即连接该第一元件裸片的该主动侧到该封装基底；以及
贴合一第二元件裸片到该第一元件裸片与该封装基底，其中该贴合的第二元件裸片的一主动侧面朝该第一元件裸片与该封装基底，该贴合的第二元件裸片的该主动侧的一部分位于一区域外，该区域重叠该贴合的第一元件裸片，多个第二电连接件在该第二元件裸片的贴合之前，即预先形成在该第二元件裸片的该主动侧的该部分，且多个所述第二电连接件在该第二元件裸片的贴合之后，即连接该第二元件裸片的该主动侧的该部分到该封装基底。
16.如权利要求15所述的半导体封装结构的制备方法，还包括在该第一元件裸片的贴合之前，即形成一第一粘贴材料在该封装基底上，其中在该第一元件裸片的贴合之后，该第一粘贴材料设置在该封装基底与该第一元件裸片的该主动侧之间。
17.如权利要求15所述的半导体封装结构的制备方法，还包括在该第二元件裸片的贴合之前，形成一第二粘贴材料在该第一元件裸片上，其中在该第二元件裸片的贴合之后，该第二粘贴材料位于该第一元件裸片与该第二元件裸片的该主动侧之间。
18.如权利要求15所述的半导体封装结构的制备方法，其中该第二元件裸片预先形成有多个导电垫与多个重分布结构在该第二元件裸片的该主动侧处，多个所述导电垫位于该第二元件裸片的该主动侧重叠该第一元件裸片的一中心区内，多个所述重分布结构连接多个所述导电垫到该第二元件裸片的该主动侧位于重叠该第一元件裸片的一区域外的一周围区，且多个所述第二电连接件在该第二元件裸片的贴合之后，即连接多个所述重分布结构到该封装基底。
19.如权利要求15所述的半导体封装结构的制备方法，还包括在该第二元件裸片的贴合之后，通过一囊封体而侧向囊封该第一元件裸片与该第二元件裸片。
20.如权利要求15所述的半导体封装结构的制备方法，还包括形成多个封装输入/输出在该封装基底面向远离该贴合的第一元件裸片与该贴合的第二元件裸片的一侧处。
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