CN103681531A - 集成电路和用于制作集成电路的方法 - Google Patents

集成电路和用于制作集成电路的方法 Download PDF

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Publication number
CN103681531A
CN103681531A CN201310396500.7A CN201310396500A CN103681531A CN 103681531 A CN103681531 A CN 103681531A CN 201310396500 A CN201310396500 A CN 201310396500A CN 103681531 A CN103681531 A CN 103681531A
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chip
integrated circuit
encapsulating material
carrier
jointing
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CN103681531B (zh
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K.霍赛尼
J.马勒
I.尼基廷
L.奥索夫斯基
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Infineon Technologies AG
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Infineon Technologies AG
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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Abstract

集成电路和用于制作集成电路的方法。提供一种集成电路。该集成电路包括：芯片和覆盖该芯片的至少三个面的包封材料，该包封材料由粘合材料形成。该集成电路包括利用该包封材料粘附到该芯片的载体。

Description

集成电路和用于制作集成电路的方法
技术领域
不同实施例总体上涉及集成电路和用于制作集成电路的方法。
背景技术
直到现在，可以通过首先将芯片粘附到载体或者引线框并且然后随后地，通常在进一步加工之后用另外的材料（例如聚合物材料）包封芯片来制作半导体芯片和半导体芯片包封。几个挑战可能与这些制作工艺相关联。可能必须通过脆性硅和软聚合物材料来实施锯切。而且，多个工艺可能有必要相互依靠。可能需要多种材料，例如粘合材料，包封材料和固定材料。用于沉积不同材料的工艺可能需要很好地互相整合。而且，不同材料可能必须适合和/或很好地匹配以供互相使用。
发明内容
不同实施例提供一种集成电路，其包括：芯片；覆盖该芯片的至少三个面的包封材料，其中该包封材料由粘合材料形成；和利用该包封材料粘附到芯片的载体。
附图说明
在附图中，贯穿不同的视图，相似的参考标记一般指的是相同的部分。附图不必要按比例，而是通常将重点放在说明本发明的原理上。在下面的描述中，参照下面的附图来描述本发明的各实施例，其中：
图1示出根据实施例的用于制作集成电路的方法；
图2A至2F示出根据实施例的用于制作集成电路的方法；和
图3示出根据实施例的用于制作集成电路的方法的一部分；
图4示出根据实施例的用于制作集成电路的方法的一部分；
图5示出根据实施例的集成电路；
图6示出根据实施例的集成电路；
图7示出根据实施例的集成电路。
具体实施方式
下面的详细描述参照附图，所述附图借助图示示出其中本发明可以被实施的实施例和具体细节。
词“示例性的”在此被用来表示“充当实例，例子，或者例证”的意思。此处被描述为“示例性的”的任何实施例或者设计不必要解释为比其它实施例或者设计优选或者有利。
关于在侧面或者表面的“上面”形成的沉积材料而使用的词“上面”可以在此被用来表示该沉积材料可以“直接”形成在所暗示的侧面或者表面“上面”，例如与所暗示的侧面或者表面直接接触。关于在侧面或者表面的“上面”形成的沉积材料而使用的词“上面”可以在此被用来表示可以“间接”形成在所暗示的侧面或者表面“上面”，其中一个或者多个附加层被设置在所暗示的侧面或表面和该沉积材料之间。
不同实施例提供一种集成电路，例如芯片布置，其中半导体芯片可以部分地和/或完全地被粘合材料包封或包围，其中该粘合材料可以是导热的和/或导电的。
不同实施例提供一种集成电路芯片布置，其中该粘合材料可以包括导电材料，其可以被用于电接触该芯片和对该芯片重新布线。
不同实施例提供一种集成电路芯片布置，其中该粘合材料可以被用于将芯片粘附或连接到芯片载体，例如引线框材料，并且也用于包封该芯片。
不同实施例提供用于制作被描述的集成电路和芯片布置的方法。
图1示出根据实施例的用于制作集成电路的方法100。方法100可以包括：
由包封材料覆盖芯片的至少三个面，其中该包封材料由粘合材料形成（在110中）；并且
利用该包封材料将载体粘附到该芯片（在120中）。
图2A至2G示出根据实施例的用于制作集成电路的方法200的截面图。
如在图2A的视图210中所示，半导体晶片衬底可以被单体化，例如切割成单体化芯片202，也被称作管芯。
半导体晶片衬底可以包括多种材料，例如半导体材料。晶片衬底可以包括来自下面材料组中的至少一种，所述材料组由下述构成：硅，锗，III-V族材料，聚合物。根据实施例，该晶片衬底可以包括掺杂的或未掺杂的硅。根据另一实施例，该晶片衬底可以包括绝缘体上硅SOI晶片。根据实施例，晶片衬底可以包括半导体复合材料，例如砷化镓（GaAs），磷化铟（InP），氮化镓（GaN），碳化硅（SiC）。根据实施例，该晶片衬底可以包括四元半导体复合材料，例如砷化铟镓（InGaAs）。
芯片202可以均具有从大约150μm变动到大约900μm（例如从大约200μm变动到大约400μm）的厚度tC。因此，包封材料218可具有从大约200μm变动到大约1100μm（例如从大约250μm变动到大约500μm）的厚度tE。
可以根据标准工艺（例如锯切）来实现芯片202的单体化。在该单体化工艺或多个单体化工艺期间，晶片可以被切割载体204（例如切割带或箔）支持。切割载体204可允许该多个单体化芯片202由共同连续载体支持。为了确保芯片侧壁206的电钝化和/或良好的电绝缘强度，可以可选地在芯片侧壁206上面沉积至少一个另外的隔离层207（未示出），例如电绝缘层。另外的隔离层207可以是例如二氧化硅（SiO2）或者氮化硅（Si3N4），并且可以是几微米厚。可以例如通过化学汽相沉积（CVD）来沉积另外的隔离层207。
如在图2B的视图220中所示，该多个单体化芯片202可以暂时被粘附（例如被层压或者粘结）到临时载体208上。单体化芯片202可以以它们的正面212面对临时载体208并且被安装到临时载体208上来被粘附。临时载体208可以包括箔，例如弹性箔，其可以被扩大或拉伸。因此，可以在相邻芯片202之间形成较大间隙214。
在下面的描述中，可以参照在单个芯片上实施的工艺。然而可以理解此处和下文描述的工艺也可以被应用到多个芯片，例如一个，两个，三个，四个等，或者甚至几十，几百或甚至几千个芯片。换句话说，可以实施该多个芯片的批量加工，也被称为并行加工。
如在图2C的视图230中所示，芯片202的至少三个面206，216可以被包封材料218覆盖，其中包封材料218可以由粘合材料218A形成。可以理解根据不同实施例，至少三个面可以包括芯片202的三个，四个，五个，六个或者更多面。芯片202的至少三个面206，216可以包括至少一个芯片背面216和至少一个芯片侧壁206，例如芯片202的侧壁206和芯片202的背面216。芯片202的正面212可以被临时载体208支持并且被布置为面向临时载体208，并且因而可以没有包封材料218。可以理解除了在芯片202的至少一个面上以外，例如除了在芯片202的正面212上以外，包封材料218可以完全包围芯片202。
正面212也可以被称作该芯片的“第一面”，“顶面”或“上面”。术语“顶面”，“第一面”，“正面”或者“上面”可以在下文中被互换使用。背面216也可以被称作该芯片的“第二面”或“底面”。术语“第二面”，“背面”，或者“底面”可以在下文中被互换使用。
如此处关于半导体芯片（例如功率器件和逻辑器件）使用的，术语“顶面”，“第一面”，“正面”或者“上面”可以被理解为指的是该芯片的其中可以形成电部件（例如在芯片中的器件的电有源区域）的面。通常，可以在芯片正面上形成至少一个接触焊盘，其中该至少一个接触焊盘可以是连接到芯片中的器件的有源区域的电极。作为实例，该器件的电有源区域可以包括电源极区域，电漏极区域，电沟道区域和电栅极区域。
术语“第二面”，“背面”或者“底面”可以被理解为指的是芯片的与正面相对的面。在一些半导体芯片中，背面可以没有金属化，例如没有任何接触焊盘，诸如在半导体逻辑芯片的情况下。在其它半导体芯片（例如半导体功率芯片）中，可以在芯片背面上形成背面金属化（例如背面接触焊盘）。因此，半导体功率晶体管可以支持例如在芯片正面上的接触焊盘和在芯片背面上形成的接触焊盘之间的穿过该芯片的垂直电流流动。
芯片202可以包括在芯片正面212上面形成的至少一个接触焊盘226，其可以不被包封材料覆盖。芯片202也可以可选地包括在面（例如被包封材料218覆盖的芯片202的面206，216中的至少一个）上形成的电接触217。根据实施例，可以在芯片202的背面216上形成电接触217。换句话说，电接触217可以包括或者是背面金属化接触。
包封材料218可以包括粘合材料218A或者由粘合材料218A构成。粘合材料218A可以包括来自下面材料组中的至少一种材料，所述材料组由下述构成：聚酰亚胺，环氧树脂，丙烯酸脂，硅树脂，聚对苯二甲酸乙二醇酯（Polyethylene terephthalate），聚砜，聚对苯硫醚（Poly (p-phenylene) sulfide），聚醚酮（Pelyetherketone），聚醚醚酮（Polyetheretherketone）和液晶聚合物。粘合材料218A可以包括导电材料。粘合材料218A可以包括或者具有至少大约1W/mK的热导率。例如，粘合材料218A可以包括或者具有至少大约50W/mK的热导率。
粘合材料218A可以包括导电的、两阶段固化材料。可包括粘合材料218A或者由粘合材料218A构成的包封材料218可以被施加在芯片背面216上方或直接在芯片背面216上，在芯片侧壁206上方或直接在芯片侧壁206上，以及在相邻芯片202之间的间隙214中。这可以通过压力，分配，印刷或者旋涂工艺来实现。
如在图2D的视图240中所示，载体222可以利用包封材料218被粘附到芯片202。载体222可以被设置在包封材料218中和/或在包封材料218上方。粘合材料218A可以被配置为将载体222粘附到芯片202的至少三个面206，216之一。例如，粘合材料218A可以被配置为将载体222粘附到芯片背面216，或者粘附到电接触217。例如，粘合材料218A可以被配置为将载体222粘附到芯片背面216和芯片侧壁206。
包封材料218和多个单体化芯片202可以形成重构晶片224。多个单体化芯片202可以通过包封材料218以衬底的形式被保持在一起。
重构晶片224可以被放置在载体222上方。包封材料218（即粘合材料218A）可以利用B阶段固化被形状配合地粘附到载体222。换句话说，包封材料218（即粘合材料218A）可以仅被部分固化，使得载体222可以被附着。典型的b阶段固化温度可以从大约50℃变动到150℃。
粘合材料218A可以包括导电材料。例如，包封材料可以包括或者是导电管芯附着密封剂。粘合材料218A可以被配置为将芯片背面216和芯片侧壁206中的至少一个电连接到载体222。载体222可以被直接粘附到粘合材料218A。
载体222可以包括引线框材料。例如，载体222可以包括金属。例如，载体222可以包括来自下面材料组中的至少一种材料，元素或者合金，该组由下述构成：铜，铝，银，锡，金，钯，锌，镍，铁。载体222可以是薄片和/或箔的形式。载体222可以被称作芯片外部接触，其可以是在芯片202外部。载体222（即芯片外部接触）可以利用包封材料218被电连接到芯片背面216和/或电接触217。
粘合材料218A可以包括填充粒子221。根据实施例，填充粒子221可以是导电的。根据实施例，填充粒子221可以包括来自下面材料组中的至少一种材料，所述材料组由下述构成：铜，银，碳，氮化硼，绝缘聚合物涂覆的导电银，绝缘聚合物涂覆的导电铜和绝缘聚合物涂覆的导电碳。填充粒子221可以形成粘合材料218A的大约15体积%到大约90体积%，粘合材料218A的其余部分由基质材料（例如聚酰亚胺，环氧树脂，丙烯酸脂或硅树脂中的至少一种）形成。
包封材料218可以覆盖至少一个侧壁206。芯片202的至少一个侧壁206可以例如通过可选地沉积的另外的隔离层207（未示出）来与包封材料218电绝缘。可替代地，至少一个侧壁206可以被电连接到包封材料218。例如，侧壁206和芯片背面216或者侧壁206和芯片背面电接触217可以被电连接（即短路），使得可以对它们施加相同的电压。例如，可以在芯片背面216上面以及在侧壁206上面形成电接触217。
因此，包封材料218也可以起以下作用：电接触芯片202，并且对芯片背面216和可能地甚至对芯片侧壁206重新布线；例如通过对在芯片背面电接触217与载体202和/或芯片侧壁206之间的电流重新定向。而且，包封材料218也可以具有比其热导率通常约为1W/mK的传统注模材料更高的热导率，例如大于1W/mK，例如大于50W/mK。因此从芯片202的热耗散可以被增加。
如在图2E的视图250中所示，在通过包封材料218将载体222粘附到芯片202之后，临时载体208可以被去除，并且可以实施将电接触和电介质施加在芯片正面212上面。电互连可以被电连接和/或物理附着到芯片202。可以用电介质材料包封芯片202并且可以在芯片正面212处形成导电带。
电绝缘材料228可以覆盖芯片202的没有被包封材料218覆盖的面（即芯片正面212）。可以利用电绝缘箔或膜（例如聚酰亚胺膜）来可选性地沉积电绝缘材料228。可替代地，传统沉积方法（例如旋涂，化学汽相沉积，蒸发）可被用于在芯片正面212上面形成电绝缘材料。
可以穿过电绝缘材料228形成至少一个电互连232（例如多个电互连232），使得电互连232可以被电绝缘材料238电绝缘。电互连232可以被布置成使得它们可以与芯片202电连接。例如，每个电互连232可以与在芯片正面212上面形成的一个或多个芯片接触焊盘226电连接。
如在图2F的视图260中所示，可以实现整个部件的单体化。换句话说，也可以被称作集成电路270的单体化器件270可以通过切穿电绝缘材料228，包封材料218和载体222来与其它器件或者集成电路分开。单体化器件可以容易地组装到印刷电路板（PCB）上。
可以理解集成电路270可以包括：
芯片202；
覆盖芯片202的至少三个面206，216的包封材料218，其中包封材料218可以由粘合材料218A形成；和利用包封材料218被粘附到芯片202的载体222。
根据不同实施例，如在图3中所示，代替包封材料218，可以代替地使用包封材料318。除了包封材料318可以是电绝缘的以外，包封材料318可以与包封材料218相同。例如，包封材料318可以由粘合材料318A（类似于粘合材料218A）形成，然而包封材料318可以没有上面描述的任何填充粒子（例如，银粒子，铜粒子和铜粒子）。例如，包封材料318可以是粘合材料318A，其可以包括来自下面材料组中的至少一种材料或者由来自下面材料组中的至少一种材料构成，所述材料组由下述构成：聚酰亚胺，环氧树脂，丙烯酸脂，硅树脂，聚对苯二甲酸乙二醇酯。
根据不同实施例，如在图4中所示，代替包封材料218，可以代替地使用包封材料418。除了包封材料418可以包括填充粒子421而不是填充粒子221以外，包封材料418可以与包封材料218相同。换句话说，代替包括例如上面描述的铜和/或银和/或碳的填充粒子，粘合材料418A可以包括电绝缘填充粒子421。例如，粘合材料418A可以包括填充粒子421，其中填充粒子421可以包括来自下面材料组中的至少一种材料，所述材料组由下述构成：氧化铝，氧化硅，氮化硼，绝缘聚合物涂覆的导电银，绝缘聚合物涂覆的导电铜和绝缘聚合物涂覆的导电碳。
这些电绝缘填充粒子421可以导致热膨胀系数（CTE）的减小，其可以更好地适应于载体222，例如适应于铜，或者适应于芯片202，例如适应于硅。这些电绝缘填充粒子421可以进一步导致湿气吸收的下降。
图5示出芯片正面212的顶视图510，其中导电粘合材料（例如覆盖箔）可以形成至少一种电互连232，并且可以被形成在电绝缘材料228上面，所述电绝缘材料可以包括例如电绝缘箔（诸如聚酰亚胺箔）。
图6和7示出可根据方法100至300中的任何一个来单独地或者组合地制作的集成电路。
图6示出根据实施例的集成电路610的图示。集成电路610可以包括：
芯片202；
覆盖芯片202的至少三个面206，216的包封材料218，其中包封材料218可以由粘合材料218A形成；和
利用包封材料218被粘附到芯片202的载体222。
图7示出根据实施例的集成电路710的图示。集成电路710可以包括：
覆盖芯片202的至少三个面206，216的包封材料218，其中包封材料218可以由导电材料形成。
根据不同实施例，可以通过包封材料218（例如粘合材料218A）将芯片202固定到载体222上，并且使用较高温度工艺，可以由包封材料218包围芯片202，所述包封材料可以包括例如粘合膜。
根据不同实施例，可以不必穿过脆性硅和软胶/聚合物材料来实施锯切。而且，可以实现较好的部件可靠性并且可能需要较少的工艺步骤。粘合材料218A也可以用作包封材料（例如包封材料218）并且反之亦然。包封材料218（即粘合材料218A）可以是导电材料。例如通过将导电和/或导热的包封材料218直接施加到芯片202上，该芯片的直接接触可以是可能的。与使用标准的注模填料相比，可以实现关于薄的和小的芯片的各种改进。
不同实施例提供一种集成电路，其包括：芯片；覆盖该芯片的至少三个面的包封材料，其中该包封材料由粘合材料形成；和利用该包封材料粘附到该芯片的载体。
根据实施例，芯片的至少三个面包括至少一个芯片背面和至少一个芯片侧壁。
根据实施例，该芯片包括形成在该至少一个芯片背面上的至少一个芯片背面金属化层。
根据实施例，该粘合材料包括导电材料。
根据实施例，该粘合材料包括至少约1W/mK的热导率。
根据实施例，该粘合材料包括至少约50W/mK的热导率。
根据实施例，该粘合材料被配置为将载体粘附到芯片的至少三个面中的一个。
根据实施例，粘合材料被配置为将载体粘附到芯片背面。
根据实施例，粘合材料被配置为将芯片背面和芯片侧壁中的至少一个电连接到该载体。
根据实施例，粘合材料包括来自下面材料组中的至少一种材料，所述材料组由下述构成：聚酰亚胺，环氧树脂，丙烯酸脂，硅树脂，聚对苯二甲酸乙二醇酯，聚砜，聚对苯硫醚，聚醚酮，聚醚醚酮和液晶聚合物。
根据实施例，粘合材料包括填充粒子，其中填充粒子包括来自下面材料组中的至少一种材料，所述材料组由下述构成：铜，银，碳，氮化硼，绝缘聚合物涂覆的导电银，绝缘聚合物涂覆的导电铜和绝缘聚合物涂覆的导电碳。
根据实施例，粘合材料包括填充粒子，其中填充粒子包括来自下面材料组中的至少一种材料，所述材料组由下述构成：氧化铝，氧化硅，氮化硼，绝缘聚合物涂覆的导电银，绝缘聚合物涂覆的导电铜和绝缘聚合物涂覆的导电碳。
根据实施例，芯片的没有被包封材料覆盖的面包括芯片正面，其中该芯片包括在芯片正面上形成的至少一个接触焊盘。
根据实施例，载体包括引线框材料。
根据实施例，载体包括金属。
根据实施例，该集成电路进一步包括覆盖芯片的没有被包封材料覆盖的面的电绝缘材料。
根据实施例，集成电路进一步包括穿过电绝缘材料形成的至少一个电互连，其中该至少一个电互连与该芯片电连接。
不同实施例提供一种集成电路，其包括：芯片；覆盖该芯片的至少三个面的包封材料，其中该包封材料由导电材料形成。
根据实施例，该芯片包括在芯片的被包封材料覆盖的面上的电接触。
根据实施例，集成电路进一步包括在该芯片外部的芯片外部接触，其中该芯片外部接触被设置成下述中的至少一种：在该包封材料中和在该包封材料上方。
根据实施例，利用该包封材料将芯片外部接触电耦合到该电接触。
根据实施例，芯片的至少一个侧壁与该包封材料电绝缘。
不同实施例提供一种用于制作集成电路的方法，该方法包括：由包封材料覆盖芯片的至少三个面，其中该包封材料由粘合材料形成；并且利用包封材料将载体粘附到该芯片。
根据实施例，包封材料包括导电材料。
根据实施例，利用包封材料将载体粘附到该芯片进一步包括利用包封材料将该载体电连接到芯片背面并且用包封材料覆盖至少一个侧壁。
虽然已经参照特定实施例具体示出和描述了本发明，但是本领域技术人员应该理解在不脱离如由所附权利要求限定的本发明的精神和范围的情况下，可以在其中作出各种形式和细节上的变化。本发明的范围因而由所附权利要求表明，并且因此在权利要求的等同物的含义和范围内的所有改变旨在被包含。

Claims (25)

1. 一种集成电路，包括：
芯片；
覆盖所述芯片的至少三个面的包封材料，其中所述包封材料由粘合材料形成；
利用该包封材料粘附到该芯片的载体。
2. 根据权利要求1的集成电路，其中该芯片的该至少三个面包括至少一个芯片背面和至少一个芯片侧壁。
3. 根据权利要求2的集成电路，其中该芯片包括在该至少一个芯片背面上形成的至少一个芯片背面金属化层。
4. 根据权利要求1的集成电路，其中该粘合材料包括导电材料。
5. 根据权利要求1的集成电路，其中该粘合材料包括至少大约1W/mK的热导率。
6. 根据权利要求1的集成电路，其中该粘合材料包括至少大约50W/mK的热导率。
7. 根据权利要求1的集成电路，其中该粘合材料被配置为将该载体粘附到该芯片的该至少三个面中的一个。
8. 根据权利要求1的集成电路，其中该粘合材料被配置为将该载体粘附到芯片背面。
9. 根据权利要求1的集成电路，其中该粘合材料被配置为将芯片背面和芯片侧壁中的至少一个电连接到该载体。
10. 根据权利要求1的集成电路，其中该粘合材料包括来自下面材料组中的至少一种材料，所述材料组由下述构成：聚酰亚胺，环氧树脂，丙烯酸脂，硅树脂，聚对苯二甲酸乙二醇酯，聚砜，聚对苯硫醚，聚醚酮，聚醚醚酮，液晶聚合物。
11. 根据权利要求1的集成电路，其中粘合材料包括填充粒子，其中填充粒子包括来自下面材料组中的至少一种材料，所述材料组由下述构成：铜，银，碳，氮化硼，绝缘聚合物涂覆的导电银，绝缘聚合物涂覆的导电铜和绝缘聚合物涂覆的导电碳。
12. 根据权利要求1的集成电路，其中该粘合材料包括填充粒子，其中填充粒子包括来自下面材料组中的至少一种材料，所述材料组由下述构成：氧化铝，氧化硅。
13. 根据权利要求1的集成电路，其中该芯片的未被该包封材料覆盖的面包括芯片正面，其中该芯片包括在该芯片正面上形成的至少一个接触焊盘。
14. 根据权利要求1的集成电路，其中该载体包括引线框材料。
15. 根据权利要求1的集成电路，其中该载体包括金属。
16. 根据权利要求1的集成电路，进一步包括覆盖该芯片的未被该包封材料覆盖的面的电绝缘材料。
17. 根据权利要求16的集成电路，进一步包括穿过该电绝缘材料形成的至少一个电互连，其中该至少一个电互连与该芯片电连接。
18. 一种集成电路，包括：
芯片；
覆盖该芯片的至少三个面的包封材料，其中该包封材料由导电材料形成。
19. 权利要求18的集成电路，其中该芯片包括在该芯片的被该包封材料覆盖的面上的电接触。
20. 权利要求18的集成电路，进一步包括：在该芯片外部的芯片外部接触，其中该芯片外部接触被设置成下述中的至少一种：在该包封材料中和在该包封材料上方。
21. 权利要求20的集成电路，其中利用该包封材料将该芯片外部接触电耦合到该电接触。
22. 权利要求18的集成电路，其中该芯片的至少一个侧壁与该包封材料电绝缘。
23. 一种用于制作集成电路的方法，该方法包括：
利用包封材料覆盖芯片的至少三个面，其中该包封材料由粘合材料形成；并且
利用该包封材料将载体粘附到该芯片。
24. 根据权利要求23的方法，其中该包封材料包括导电材料。
25. 根据权利要求23的方法，其中利用该包封材料将载体粘附到该芯片进一步包括利用该包封材料将该载体电连接到芯片背面并且用该包封材料覆盖至少一个侧壁。
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