CN101393899B - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN101393899B
CN101393899B CN2008102115502A CN200810211550A CN101393899B CN 101393899 B CN101393899 B CN 101393899B CN 2008102115502 A CN2008102115502 A CN 2008102115502A CN 200810211550 A CN200810211550 A CN 200810211550A CN 101393899 B CN101393899 B CN 101393899B
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semiconductor chip
electric insulation
insulation layer
substrate
layer
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CN2008102115502A
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CN101393899A (zh
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约阿希姆·马勒
亨里克·埃韦
曼弗雷德·门格尔
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

本发明披露了一种半导体器件和方法。一个实施例提供了基板和施加在基板上的第一半导体芯片。第一导电层施加在基板和第一半导体芯片上。第一电绝缘层施加在第一导电层上。第二导电层施加在第一电绝缘层上。

Description

半导体器件
技术领域
本发明涉及半导体器件及其装配方法。
背景技术
电子器件可以包含两个或多个彼此电相连或彼此电绝缘的元件。因此，电子器件可以既包含导电装置也包含电绝缘装置，以提供需要的器件布置。
由于这些原因以及其它原因，需要本发明。
发明内容
本发明提供了一种器件，包括：基板；施加在所述基板上方的第一半导体芯片；施加在所述基板和所述第一半导体芯片上方的第一导电层；施加在所述第一导电层上方的第一电绝缘层；施加在所述第一电绝缘层上方的第二导电层。
附图说明
本文包含了附图以提供对实施例的进一步理解，其并入并构成了本说明书的一部分。附图示出了实施例，并和说明一起用于阐述实施例的原理。参考下面的详细说明可以很容易看出其它实施例以及实施例的许多预期的优点，因为其它实施例以及实施例的许多预期的优点将更好理解。附图的元件没有必要相对于彼此成比例。相同的参考数字指的是对应的同一部件。
图1是依据示例性实施例的器件100的示意图。
图2是依据示例性实施例的器件200的示意图；
图3A到图3M是制造器件300的方法的示例性实施例的示意图；
图4是依据示例性实施例的器件400的示意图；
图5是依据示例性实施例的器件500的示意图；
具体实施方式
在下面详细描述中，参考形成本说明书的一部分的附图，其中，以例证的方式示出了可以实施本发明的具体实施例。关于图，诸如“顶”、“底”、“前”、“后”、“前导”、“尾随”等方向性术语参考所描述的附图的方向使用。由于本发明实施例的组件可以在许多不同方向上放置，所以方向术语仅用于说明，而没有任何限制的意思。应该理解的是，可以使用其它实施例，并且在不背离本发明的范围的前提下可以进行结构或逻辑改变。所以，下面详细描述不应被理解为限制性的意思，并且本发明由所附的权利要求限定。
应该理解的是，如果没有其它特别注明，这里描述的不同的示例性实施例的特征可以彼此结合。
下面描述了具有一个或多个施加在基板上方的半导体芯片的器件。基板可以是任何形状、大小或由任何材料制成。在器件的制造过程中，该基板可以以如下方式设置，即，将其它基板布置在其附近，并且其它基板通过连接装置连接到该基板以分离这些基板。基板可以由陶瓷材料制成，或可以是印刷电路板。基板可以是导电的，并且可以由金属或金属合金制成，尤其是铜、铜合金、铝、铝合金、或其它金属。例如，基板可以是引线框架或引线框架的一部分，比如芯片连接盘(die pad)。此外，基板可以包含两个或多个元件，例如芯片连接盘和引线。基板可以具有安装表面。安装表面可以用于将基板安装到另一元件上或可以用于将另一元件安装到基板上。
下面描述的半导体芯片可以是完全不相同的类型，并可以包含有例如集成电路或光电电路。半导体芯片例如可以被配置成功率晶体管、功率二极管、IGBT(绝缘栅双极晶体管)、控制电路、驱动电路、微处理器或微机电元件。特别地，可以包含具有垂直结构的半导体芯片，也就是说半导体芯片可以以这样的方式来制造，使得电流可沿垂直于半导体芯片主表面的方向流动。具有垂直结构的半导体芯片可以尤其在其两个主表面上(即，在其顶面和底面上)有接触垫。特别地，功率晶体管和功率二极管可以具有垂直结构。例如，功率晶体管的源极和栅极以及功率二极管的阳极可以位于一个主表面上，而功率晶体管的漏极和功率二极管的阴极可以布置在另一主表面上。特别地，可以将功率二极管具体化成Schottky二极管。此外，下面描述的器件可以包含集成电路，以控制和/或驱动其它半导体芯片的集成电路，例如，功率晶体管或功率二极管的集成电路。半导体芯片并不需要用特定的半导体材料来制造，并且还可以包含非半导体的无机和/或有机材料，如绝缘体、塑料或金属。此外，半导体芯片可以封装，也可以不封装。
半导体芯片可以有接触垫，允许与半导体芯片形成电接触。这些接触垫由任何期望的导电材料制成，例如金属(如铜、铝或金)、金属合金或导电有机材料。接触垫可以位于半导体芯片的活性表面或者称为主动表面或者半导体芯片的其它表面上。对于功率晶体管来说，接触垫包括漏极、源极和栅极。
下面描述的器件包括外接触垫。外接触垫可以从器件外部接近，并且使得能够从器件外部与半导体芯片形成电接触。此外，外接触垫可以是导热性的，且可以用作驱散由半导体芯片产生的热的散热片。外接触垫可以由任何期望的导电材料制成，例如，金属(如铜、铝或金)、金属合金或导电有机材料。
一个或多个导电层可以施加在基板和/或半导体芯片上。导电层可以用于从器件外部与半导体芯片形成电接触以及在这些器件内形成半导体芯片和无源部之间的电接触。导电层可以以任何期望的几何形状以及期望的材料成份而制成。例如，导电层可以由线状导轨组成，也可以以覆盖某一区域的层的形式。任何期望的导电材料，比如金属(如铜、铝或金)、金属合金或有机导体，都可以被用作材料。导电层不需要是均质的或仅由一种材料制成，也就是说导电层中可以包含各种成份和浓度的材料。此外，导电层可以布置在电绝缘层的上方或下方或之间。
器件还可以包括一个或多个电绝缘层。电绝缘层可以覆盖器件中元件的任意多个表面的任意部分。术语“电绝缘”指的是相对于器件中导电层，电绝缘层的特性至多只是稍微(marginally)导电。电绝缘层可以起到多方面的作用，例如，它们可以用于将器件中元件彼此电绝缘，也可以用作安装其它元件(如半导体芯片)的平台。
器件可以包括覆盖了器件中至少一部分元件的模塑料或者称为模制材料。这个模塑料可以是任何合适的热塑性或热固性材料。可以使用比如压模法或喷射模塑法等不同的技术来用模塑料覆盖元件。
图1是作为示例性实施例的器件100的剖面示意图。器件100包括基板10和安装在基板10上的第一半导体芯片11。第一导电层12施加在基板10和第一半导体芯片11的上方。第一电绝缘层13施加在第一导电层12的上方，并且第二导电层14施加在第一电绝缘层13的上方。
器件100还包括与第二导电层14电相连的第二半导体芯片。此外，第一导电层12可以包括至少两个部分15和16。部分15或至少部分15的下表面可以与第一导电层12的部分16或部分16的下表面共面。第一导电层12的部分15和16可以分别附着至基板10和第一半导体芯片11。
图2是作为另一个实施例的器件200的剖面示意图。器件200包括基板10和安装在基板10上的第一半导体芯片11。第一电绝缘层13施加在基板10和第一半导体芯片11的上方。第一电绝缘层13可以延伸到第一半导体芯片11之外，并且可以至少部分地布置在由第一半导体芯片11的轮廓确定的区域之外。由第一半导体芯片11的轮廓确定的区域以标有参考标号17的虚线显示在图2中。第二半导体芯片18安装在第一电绝缘层13上。第二半导体芯片18至少部分地布置在由第一半导体芯片11的轮廓确定的区域17之外。第二半导体芯片18也可以完全布置在区域17之外。此外，其它半导体芯片或无源部可以施加至第一电绝缘层13，并且它们可以布置在区域17之内或者部分地或完全地布置在区域17之外。
在图3A到图3M中，示例性地示出了图3M中所示的器件300的制造过程的不同阶段。器件300是图1所示的器件100和图2所示的器件200的实施方式。因此，下面描述的制造方法的细节以及器件300的特征可以同样地应用于器件100和200。
首先提供基板10，如图3A的剖面图所示。例如，基板10可以是引线框架，它是引线框架带的一部分。引线框架带可以由导电材料制成，例如铜、或另一种金属或金属合金。在引线框架带的每个器件位置处，提供芯片连接盘20和多个引线，其中引线21、22和23显示在图3A中。引线21至23排开在距离芯片连接盘20一定距离处。
半导体芯片11安装在芯片连接盘20的上表面上(见图3B)。在本实施例中，半导体芯片11是垂直功率晶体管，例如MOSFET，并且在其下表面上包括漏极24，在其上表面上包括源极25和栅极26。漏极24可以电连接至芯片连接盘20的上表面。
功率晶体管11的漏极24和芯片连接盘20之间的电连接例如可以通过如回流焊接、真空焊接、扩散焊接或利用导电性胶粘剂粘合等方式来实现。
如果以扩散焊接作为连接技术，则有可能使用这样的焊料，该焊料使得，在焊接操作结束后，由于界面扩散工艺，在芯片连接盘20和功率晶体管11的接触面上产生金属间相。在这种情况下，可以想到用AuSn、AgSn、CuSn、AgIn、AuIn或CuIn作为例如铜或铁镍合金引线框架10的焊料。如果功率晶体管11通过胶粘剂结合在芯片连接盘20上，则可以采用基于环氧树脂并富含金、银、镍或铜的导电粘合剂，以产生导电性。
然后将第二电绝缘层27沉积到功率晶体管11的上表面和侧表面、芯片连接盘20暴露的上表面以及引线21至23的上表面上(见图3C)。电绝缘层27可以是自支撑的具有足够机械强度以自支撑的介电层。自支撑层的实例是箔或薄片，例如，由聚合物或其它合适的塑料材料或合成材料制成。它的机械强度使介电层27能够在引线21至23和芯片连接盘20之间的空隙上架起桥，以在空隙区域上自支撑。
通过施加一段可将电绝缘层27附着至功率晶体管11和引线框架10的适当时间的真空以及热和压力，可以将电绝缘层27层压至功率晶体管11的上表面和侧表面、芯片连接盘20的上表面以及引线21至23的上表面上。
在沉积电绝缘层27之前，还可以在芯片连接盘20和引线21至23之间的间隔中填充材料28(见图3D)。在这种情况下，其它介电元件而非箔或薄片可以被用于制造电绝缘层27。例如，电绝缘层27可以由溶液或气相沉积，并且可以以层叠方式组合至期望的厚度。能用于这种沉积的技术是例如物理或化学气相沉积、旋涂、分配或浸渍(dipping)。聚合物(如聚对二甲苯)、或无机、陶瓷类似材料(如硅碳化合物或CVD金刚石)可以用作材料。材料28可以在沉积电绝缘层27后去除，但也可以留在空隙中。在后者的情况下，材料28应是电绝缘的。
作为填充芯片连接盘20和引线21至23之间空隙的材料28的另一选择，可变形支撑层29可以沉积在引线框架10的下表面上。在层压工艺或由溶液或气相沉积过程中，可变形支撑层29可以被压进芯片连接盘20和引线21至23之间的空隙中。可变形支撑层29可以占用芯片连接盘20和引线21至23之间的至少一些空隙或体积，使得电绝缘层27不能占用这个空隙。
可变形支撑层29可以由硅树脂箔制成，并且足够柔软，能被推入芯片连接盘20和引线21至23之间的空隙中。可变形支撑层29提供了防止电绝缘层27的横跨过芯片连接盘20和引脚21至23之间空隙延伸的区域过度下陷到这些空隙中的结构。
这个布置使电绝缘层27能够在去除可变形支持层29之后自支撑，即使已经由溶液或气相沉积了电绝缘层27。结果，电绝缘层27的下表面与引线框架10的上表面充分共面。因此，电绝缘层27的上表面免于由于电绝缘层27下陷到空隙中而引起的下陷。
电绝缘层27的厚度可以在1到200μm的范围内，也可以更厚。
然后可以结构化电绝缘层27，如图3F所示。在电绝缘层27内形成多个切口或通孔，以暴露功率晶体管11的至少一部分源极25和栅极26以及引线21至23的上表面，使得这些暴露区域形成电连接。例如，电绝缘层27可以通过冲压工艺、激光烧蚀、蚀刻、光刻结构化或其它合适的本领域技术人员熟知的工艺而结构化。
在另一个实施例中(未显示在图中)，电绝缘层27在层压至功率晶体管11和引线框架10之前，可以被提供为具有多个切口或通孔的聚合物箔或薄片。切口或通孔可以通过冲压聚合物箔或薄片的区域生成。这些区域的大小和布置与引线框架10和功率晶体管11的元件的表面布置一致，这些区域是需要暴露的。
通过在电绝缘层27及其开口上沉积导电层12并结构化该层来生成源极25和引线22之间以及栅极26和引线23之间的电连接。完全重新布线的结构显示在图3G中。电绝缘层27用作沉积导电层12的平台，它使导电层12能够在芯片连接盘20和引线21至23之间的空隙上架起桥。此外，电绝缘层27将导电层12与下层结构(如果需要的话，如引线框架10)电绝缘。
导电层12可以通过非电镀(electroless)/或电镀(galvanicplating)工艺生成。因此，首先在电绝缘层27的上表面和引线框架10和功率晶体管11的暴露区域上沉积一层晶籽层。比如钯或钛的材料都可以用于晶籽层，晶籽层的厚度通常小于1μm。
通过在晶籽层上沉积另一导电材料层，可以增加晶籽层的厚度。例如，可以在晶籽层上非电镀沉积一层铜。这个铜层的厚度可以小于1μm。然后可以再电镀沉积另一层铜，该另一层铜的厚度可以大于5μm。非电镀铜沉积也可以省略。
可以通过真空沉积工艺(比如溅射)沉积晶籽层。例如，首先溅射具有例如约50nm的厚度的钛层，然后再溅射具有例如约200nm的铜层。然后铜层可以用作晶籽层，以电镀沉积厚度大于5μm的另一铜层。
也可以使用其它沉积方法，比如物理气相沉积、化学气相沉积、旋涂工艺、喷涂工艺或喷墨印刷术。铜、铁、镍或其它金属或金属合金都可以用作材料。导电层12的厚度可以在5μm到1mm的范围内，尤其是在50μm到300μm的范围内。
导电层12可以在完成其所有层的沉积之后或在沉积晶籽层之后被结构化。结构化在功率晶体管11的电极25、26和引线22、23之间产生了实体上分开的导体轨道，如图3G所示。横向(lateral)区域和/或导体轨道的厚度可以根据对于相应的导体轨道所期望的电流负荷量(current carrying capacity)来选择。例如将栅极26电连接到引线23的导体轨道可以在横向方向和/或垂直方向小于将源极25电连接到引线22的导体轨道。
如果期望提供不同厚度的导体轨道，可以通过在选择的导体轨道上沉积另外的金属层而生成。可以在已经形成并结构化过的导体轨道上沉积光刻胶层，以暴露期望其厚度增加的导体轨道。然后可以通过选择性的沉积工艺或通过沉积及沉积金属层的进一步结构化而沉积另外的一层或多层金属层，以增加选择的导体轨道的厚度。
如图3G所示，用于产生导电层12的沉积方法导致导电层12的共面部分。在图3J中两个共面部分标为参考标号15和16。由于所使用的沉积方法，导电层12可以充分地遵循下层结构的拓扑学(topology)。这适用于导电层12的下表面，并且如果导电层12的厚度足够小，也适用于它的上表面。
在通过导体轨道的沉积在功率晶体管11和引线22、23之间形成电连接之后，在导电层12和其它暴露表面上沉积电绝缘层13，如图3H所示。电绝缘层13可以在它的上表面设置平面部分，与引线框架10的上表面共面。这些平面部分可以用于安装其它元件，如半导体芯片或无源部。
电绝缘层13可以是可以层压在下层结构的暴露表面上的电介质薄膜、箔或薄片。可以施加一段适当时间的真空、热和压力以附着电绝缘层13。电绝缘层13可以由溶液或气相沉积并且可以以层叠方式组合至期望的厚度。可以用于这种沉积的技术是例如物理或化学气相沉积、旋涂、分配或浸渍。在这种情况下，聚合物(如聚对二甲苯)、或无机、仿瓷材料(如硅碳化合物或CVD金刚石)可以用作材料。电绝缘层13可以具有任何期望的厚度。例如，电绝缘层13的厚度可以大于1μm或大于100μm或大于几百个μm。如果电绝缘层13的厚度较小，电绝缘层13就可以充分地遵循下层结构的拓扑学。如果电绝缘层13的厚度较大，就在它的上表面上形成可以用于将元件安装在其上的平面部分。
电绝缘层13可以作为薄膜、箔或薄片或由液体或气相沉积，并且通过在例如约100℃或其它合适温度下的热处理而部分硬化。然后在电绝缘层13上安装第二半导体芯片18和第三半导体芯片30，电绝缘层13在仅部分硬化时显示出了粘合特性(见图3I)。然后电绝缘层13在适当温度下完全硬化，该温度可能高于200℃。当电绝缘层13完全硬化时，半导体芯片18和30就牢固地附着在电绝缘层13上。
在没有完全硬化时具有粘合特性并可以用于上述方法的材料可以包括聚酰亚胺、环氧化物、丙烯酸盐和/或这些物质的混合物。如果电绝缘层13由气相沉积，那么聚对二甲苯(parylenes)可以用作基本材料。聚对二甲苯在约300℃的温度会***，并因此能够将半导体芯片18和30牢固地附着至电绝缘层13。
在另一个实施例中(未显示在图中)，电绝缘层13没有显示出粘合特性。在这种情况下，在电绝缘层27的顶部沉积附加的粘合层，以附着半导体芯片18和30。
半导体芯片18和30可以以它们的活性主表面背向电绝缘层13的方式安装在电绝缘层13上。在图3I中，描述了半导体芯片18的接触垫31及32和半导体芯片30的接触垫33及34。半导体芯片18和30还可以具有另外的接触垫。
如图3I所示，电绝缘层13使半导体芯片18不直接堆叠在功率晶体管11上成为可能，但是横向偏离并且稍微部分地布置在由功率晶体管11的轮廓限定的区域17之外。电绝缘层13的上表面没有必要如图3I所示的那样完全平坦。但是电绝缘层13的上表面的一些部分可以是平坦的。
可以用第三电绝缘层35覆盖半导体芯片18和30以及电绝缘层13(如图3J所示)。电绝缘层35的特性和制造方法可以与上述电绝缘层13和/或27的特性和制造方法类似。
然后可以同时结构化电绝缘层13和35(如图3K)。电绝缘层13可以在沉积电绝缘层35之前被结构化。在电绝缘层13和35内形成多个切口或通孔，以暴露半导体芯片18和30的接触垫31至34的一部分、引线21以及与功率晶体管11的栅极26连接的导体轨道。例如，电绝缘层13和35可以通过冲压工艺、激光烧蚀、蚀刻、光刻结构化或其它合适的本领域技术人员熟知的工艺而结构化。
然后通过在电绝缘层35及其开口上沉积导电层14并结构化导电层14，在引线21和接触垫31之间、接触垫32和接触垫33之间以及接触垫34和栅极26之间产生电连接。完全重新布线的结构显示在图3L中。导电层14的制造方法与上述导电层12的制造方法类似。
在形成电连接之后，可以执行模传送工艺(mold transferprocess)以用模塑料36封装布置在引线框架10上的元件(见图3M)。模塑料36可以封装器件300的任何部分，而留着芯片连接盘20和引线21至23的下表面未被覆盖。模塑料36也可以填充在芯片连接盘20和引线21至23之间的空隙中。填充在这些空隙中的模塑料36的下表面可以与芯片连接盘20和引线21至23的下表面大体上共面。
模塑料36可以由任何合适的热塑性或热固性材料构成，尤其是其可以由一般用于当前半导体封装技术的材料构成。可以使用比如压模法或喷模法等不同的技术将模塑料36覆盖在器件300的元件上。
如图3M所示，器件300是无引线封装。在封装工艺之后，引线21至23和芯片连接盘20的暴露表面提供了功率晶体管11的漏极24、源极25和栅极26的外接触垫以及半导体芯片18的接触垫31。外接触垫可以被清洁并镀上锡。然后将单个的器件300从引线框架带上分离。
半导体新品18和30可以是逻辑芯片。例如，半导体芯片18可以包括控制功率晶体管11的控制电路。半导体芯片30可以包括产生信号以驱动功率晶体管11的栅极26的驱动电路。
图4是作为另一个示例性实施例的器件400的剖面示意图。器件400在许多方面与器件300相似。然而，器件400的半导体芯片18和30以倒晶封装方式布置，意味着半导体芯片18和30的接触垫31至34面向引线框架10。如图4中所示，因此导电层14布置在电绝缘层13和半导体芯片18和30之间。
图5是作为另一个示例性实施例的器件500的俯视示意图。器件500是器件300的实施方式。图3A到图3M中所示的相似的元件在图5中以相同的参考标号标出。图5显示了半导体芯片11安装在芯片连接盘20上，并且电绝缘层13布置在半导体芯片11和器件500的其它元件的上方。电绝缘层13提供了附着例如半导体芯片18和30等其它芯片或无源部的平台。电绝缘层13使这些半导体芯片与半导体芯片11绝缘。由于电绝缘层13，这些半导体芯片没有必要直接布置在半导体芯片11上，但可以横向偏离，例如半导体芯片18。此外，图5中显示了导体轨道，它将半导体芯片11、18和30的上表面上的接触垫和电极彼此之间电连接和/或将它们电连接至引线。
另外，尽管仅相对于多种实施方式中的一种公开了本发明的实施例的特定特征或方面，但是如任何给定或特定应用所要求的，这些特征或方面可以与其它实施方式的一个或多个其它特征或方面进行结合。此外，就具体实施方式或权利要求中所使用的术语“包括(include)”、“具有(have)”、“带有(with)”、以及它们的其它变体，这些术语旨在以类似于术语“包含(comprise)”的方式被包含。可能使用了术语“相连或耦合(couple)”、“连接(connected)”以及它们的衍生词。应该理解，这些术语可以被用于表示两个元件彼此合作或相互作用，而不论它们是直接的物理或电性接触，还是彼此非直接接触。此外，应该理解，本发明的实施例可以由分离电路、部分集成电路、完全集成电路或编程装置实现。而且，术语“实例性的”仅意味着作为实施例，而不是最优的或最佳的。还应该明白的是，为了简单和容易理解，此处描述的特征和/或元件都是以相对于彼此的特定尺寸示出的，并且它们的实际尺寸可能很大程度的不同于此处所示出的。
尽管在此示出并描述了具体实施例，但是本领域普通技术人员应该理解的是，在不背离本发明的范围的前提下，各种可选和/或等同的实施方式可以代替所描述和示出的具体实施例。本申请旨在覆盖本文中所讨论的具体实施例的任何修改或变形。所以，本发明旨在仅由权利要求及其等同物限定。

Claims (16)

1.一种半导体器件，包括：
基板；
施加在所述基板上方的第一半导体芯片；
第一导电层，所述第一导电层包括第一部分和第二部分，第一部分施加到第一半导体芯片，而第二部分设置在由第一半导体芯片的轮廓确定的区域之外并且施加到所述基板上；所述第一部分和所述第二部分是共面的并且在垂直于所述基板的主表面的方向上彼此偏移；
施加在所述第一半导体芯片和所述基板以及第一导电层上的第一电绝缘层，第一电绝缘层具有与所述基板和所述第一半导体芯片相对的上表面，其中所述上表面形成平台；
施加在所述第一电绝缘层上方的第二半导体芯片，其中所述第二半导体芯片至少部分地布置在由所述第一半导体芯片的轮廓限定的区域之外；所述第二半导体芯片具有下表面和与所述下表面相对的上表面，其中所述第二半导体芯片的整个下表面直接施加到由所述第一电绝缘层的上表面所形成的平台上，并且接触垫设置在所述第二半导体芯片的上表面上。
2.根据权利要求1所述的器件，包括其中第一导电层施加在所述基板和所述第一半导体芯片的上方。
3.根据权利要求1所述的器件，包括其中第二导电层施加在所述第一电绝缘层的上方。 
4.根据权利要求2所述的器件，包括其中第二电绝缘层布置在所述基板和所述第一导电层之间。
5.根据权利要求4所述的器件，其中所述基板包括至少两个以一定间隔排开的元件，并且第二电绝缘层施加在所述基板的至少两个元件的至少一部分的上方。
6.根据权利要求1所述的器件，包括其中所述第一半导体芯片在第一主表面上有第一接触垫，并且在第二主表面上有第二接触垫。
7.一种装配半导体器件的方法，包括：
提供基板；
在所述基板上安装第一半导体芯片；
在所述基板和所述第一半导体芯片上沉积第一导电层；
在所述第一导电层上沉积第一电绝缘层；所述第一电绝缘层具有与所述基板和所述第一半导体芯片相对的上表面，所述上表面形成平台；
将具有下表面的第二半导体芯片安装到所述第一电绝缘层上，其中整个下表面施加到由所述第一电绝缘层的上表面形成的平台上并且其中所述第二半导体芯片至少部分地安装到由第一半导体芯片的轮廓确定的区域之外，其中所述第二半导体芯片的整个下表面直接施加到由所述第一电绝缘层的上表面所形成的平台上；第二半导体芯片具有与所述下表面相对的上表面，并且接触垫设置在所述第二半导体芯片的上表面上；
在所述第一电绝缘层上沉积第二导电层，其中在所述第二半导体芯片安装到所述第一电绝缘层上之后沉积所述第二导电层。 
8.根据权利要求7所述的方法，包括由溶液或气相沉积所述第一导电层。
9.根据权利要求7所述的方法，包括由溶液或气相或作为箔沉积所述第一电绝缘层。
10.根据权利要求7所述的方法，包括将第二半导体芯片附着至所述第一电绝缘层，并且所述第一电绝缘层在所述第二半导体芯片的沉积过程中具有粘合特性。
11.根据权利要求10所述的方法，包括在沉积了所述第二半导体芯片之后硬化所述第一电绝缘层。
12.一种装配半导体器件的方法，包括：
提供基板；
在所述基板上安装第一半导体芯片；
在所述基板和所述第一半导体芯片上沉积第一电绝缘层；所述第一电绝缘层具有与所述基板和所述第一半导体芯片相对的上表面，所述上表面形成平台；
在所述第一电绝缘层上安装具有下表面的第二半导体芯片，其中整个下表面施加到由所述第一电绝缘层的上表面形成的平台上并且使得所述第二半导体芯片至少部分地安装在由所述第一半导体芯片轮廓限定的区域之外；其中所述第二半导体芯片的整个下表面直接施加到由所述第一电绝缘层的上表面所形成的平台上；第二半导体芯片具有与所述下表面相对的上表面，并且接触垫设置在所述第二半导体芯片的上表面上；以及
在将第二半导体芯片安装到第一电绝缘层上之后将模塑料沉积到第二半导体芯片上。 
13.根据权利要求12所述的方法，包括在所述基板和所述第一半导体芯片上由溶液或气相沉积第一导电层。
14.根据权利要求12所述的方法，包括由溶液或气相或作为箔沉积所述第一电绝缘层。
15.根据权利要求12所述的方法，包括其中所述第一电绝缘层在所述第二半导体芯片的沉积过程中具有粘合特性。
16.根据权利要求15所述的方法，包括在沉积了所述第二半导体芯片之后硬化所述第一电绝缘层。 
CN2008102115502A 2007-09-19 2008-09-19 半导体器件 Expired - Fee Related CN101393899B (zh)

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