CN101783390B - 具有改善结构稳定性的存储单元及其制造方法 - Google Patents
具有改善结构稳定性的存储单元及其制造方法 Download PDFInfo
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- CN101783390B CN101783390B CN2009101325688A CN200910132568A CN101783390B CN 101783390 B CN101783390 B CN 101783390B CN 2009101325688 A CN2009101325688 A CN 2009101325688A CN 200910132568 A CN200910132568 A CN 200910132568A CN 101783390 B CN101783390 B CN 101783390B
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- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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Abstract
本发明公开了一种具有改善结构稳定性的存储单元及其制造方法。此处所描述的存储单元包含一底电极包含一衬底部份及一柱状部份于该衬底部份之上,该柱状部份及该衬底部分具有各自的外表面且该柱状部分具有一宽度小于该衬底部份的宽度。一存储元件于该底电极的该柱状部分的一上表面之上以及一顶电极于该存储元件之上。一介电间隔物与该柱状部分的该外表面连接,该底电极的该衬底部分的该外表面与该介电间隔物的一外表面自动对准。
Description
技术领域
本发明是关于基于可编程电阻材料为基础的高密度存储器装置,其包含如硫属化物(chalcogenide)等相变化材料,以及制造该装置的方法。
背景技术
如硫属化物及类似材料的此等相变化存储材料,可通过施加其幅度适用于集成电路中的电流,而致使晶相变化。这种特性则引发使用可编程电阻材料以形成非易失性存储器电路等兴趣。此通常为非晶相状态其特性为具有较通常为结晶相状态高的电阻率;此电阻值的差异可以感测作为用来指示数据。这些特性吸引了大家的注意想使用可编程电阻材料以形成非易失存储电路,其可随机存取以读取及写入。
从非晶至结晶状态的改变通常是一较低电流的操作。从结晶至非晶状态的改变,在此表示为复位(reset),通常是一较高电流的操作,其包含一短的高电流密度脉冲以融化或分解该结晶结构,之后该相变化材料快速的冷却,抑制该相变化的过程,允许至少一部份的相变化结构稳定在该非晶状态。而吾人希望减少被用于导致相变化材料的转变从该结晶状态至非晶状态的复位电流的大小。此使用相变化材料的存储单元包含一主动区域于此存储单元的相变化材料区域内,其是相变化转换真正发生的地方。减少主动区域面积的技术被开发,如此减少了诱发相变化所需要的电流大小。此外,也使用用来热隔离在此相变化存储单元主动区域的技术,如此可将诱发相变化所需要的电阻加热效应局限在主动区域之中。
用以复位的复位电流大小,可以通过减少在单元中该相变化材料元件的大小和减少介于电极及/或该相变化材料间的接点面积,使得较高的电流密度可以通过较小绝对电流值经由该相变化材料元件来达成。
此领域发展的一种方向是致力使用微量的可编程电阻材料,特别是用来填充微小孔洞。致力于此等微小孔洞的专利包括:于1997年11月11 日公告的美国专利第5,687,112号“Multibit Single Cell Memory ElementHaving Tapered Contact”、发明人为Ovshinky;于1998年8月4日公告的美国专利第5,789,277号“Method of Making Chalogenide[sic]MemoryDevice”、发明人为Zahorik等;于2000年11月21日公告的美国专利第6,150,253号“Controllable Ovonic Phase-Change Semiconductor MemoryDevice and Methods of Fabricating the Same”、发明人为Doan等。
一种用以在相变化单元中控制主动区域尺寸的方式,是设计非常小的电极以将电流传送至一相变化材料体中。此微小电极结构将在相变化材料的类似伞状小区域中诱发相变化,亦即接点部位。请参照2002/8/22发证给Wicker的美国专利6,429,064号“Reduced Contact Areas of SidewallConductor”、2002/10/8发证给Gilgen的美国专利6,462,353“Method forFabricating a Small Area of Contact Between Electrodes”、2002/12/31发证给Lowrey的美国专利6,501,111号“Three-Dimensional(3D)ProgrammableDevice”、以及2003/7/1发证给Harshfield的美国专利6,563,156号“MemoryElements and Methods for Making same”。
与制造此种具有一个非常小电极装置相关的一个问题是因为此非常小的电极会有较差的附着性,如此会导致底电极于制造过程中脱落。
于是一种具有倒T形状的底电极被提出,请参照2008/1/18所申请的美国专利12/016,840号“Memory cell with Memory Element Contacting anInverted T-Shaped Bottom Electrode”,其具有一个小的接点区域于底电极与存储材料之间,导致一个小的主动区域以及减少了复位存储单元所需的能量大小。此倒T形状的底电极也改善了在制造过程中此底电极的结构稳定性,因此改善了此等装置的工艺良率。
因此必须提出一种制造此等存储单元结构的可靠工艺方法,其具有控制底电极临界尺寸的良好能力,也可以在高密度集成电路装置中解决非常小的电极的结构稳定性问题。
发明内容
本发明所揭露的一种存储单元包含一底电极包含一衬底部份及一柱状部份于该衬底部份之上,该柱状部份及该衬底部分具有各自的外表面且 该柱状部分具有一宽度小于该衬底部份的宽度。一存储元件于该底电极的该柱状部分的一上表面之上以及一顶电极于该存储元件之上。一介电间隔物与该柱状部分的该外表面连接,该底电极的该衬底部分的该外表面与该介电间隔物的一外表面自动对准。
本发明亦揭露一种存储单元的制造方法,其包含形成一存储器核心,包含一底电极包含一衬底部份及一柱状部份于该衬底部份之上,该柱状部份及该衬底部分具有各自的外表面且该柱状部分具有一宽度小于该衬底部份的宽度。此存储器核心也包含一存储元件于该底电极的该柱状部分的一上表面之上,以及一顶电极于该存储元件之上。此方法也包含形成一介电间隔物与该柱状部分的该外表面连接,该底电极的该衬底部分的该外表面与该介电间隔物的一外表面自动对准。
此处所描述的一种制造一存储单元的方法,包含提供一存储器存取层,其具有一顶表面,该存储器存取层包括一导电栓塞延伸至该存储器存取层的该顶表面。形成一底电极材料层于该存储器存取层的该顶表面层之上,形成一存储材料层于该底电极之上,形成一顶电极材料层于该存储材料层之上,以及形成一刻蚀掩模于该顶电极材料层之上。使用该刻蚀掩模以刻蚀通过该底电极材料层的一部份,因此形成一包括底电极材料柱状物的部分刻蚀层以及一多层叠层于该底电极材料柱状物之上。该多层叠层包含一存储元件其包含存储材料于该底电极材料柱状物之上及一顶电极其包含顶电极材料于该存储元件之上。形成一介电间隔物材料层于该部分刻蚀层及该多层叠层之上。非等向性刻蚀该介电间隔物材料层以形成一介电间隔物与该底电极柱状物的一外表面以及该多层叠层的一外表面连接。使用该介电间隔物作为一刻蚀掩模来刻蚀该部分刻蚀层,因此形成一底电极其包含一衬底部份及一柱状部份于该衬底部份之上。
此处所描述的底电极衬底部分的较大宽度可以提供底电极较佳的附着性且减少底电极于制造过程中脱落的风险。此外,此种设计也会将弱点的位置(即,此底电极终端平面最狭窄之处)自底电极与底层结构的接口处移到底电极材料层之中。
本发明的其它特征、目的和优点,会参考下列图式、发明详细说明及申请专利范围来描述。
附图说明
图1绘示先前技术具有一「伞状」存储单元的剖面图
图2绘示一先前技术「柱状」存储单元的一剖面图。
图3是绘示依据本发明一实施例的一存储单元的剖面图,相较于图1中的结构,其可以改善结构的结构稳定性。
图4是绘示依据本发明另一实施例的一存储单元的剖面图,相较于图2中的结构,其可以改善结构的结构稳定性。
图5至图13是图3所示的存储单元的工艺步骤序列示意图。
图14至图19是图4所示的存储单元的工艺步骤序列示意图。
图20为依据本发明的一集成电路装置的区块示意图。
图21是一代表性存储阵列的部分示意图。
【主要元件符号说明】
10:集成电路
12:存储阵列
14:字线译码器/驱动器
16:字线
18:位线译码器
20:位线
22:总线
24:感应放大器以及数据输入结构
26:数据总线
28:数据输入线
30:其它电路
32:数据输出线
34:控制器
36:偏压调整供应电压
38、40、42、44:存取晶体管
46、48、50、52:相变化元件
47、49、51、53:倒T型底电极
54:源极线
55:源极线终端
56、58:字线
60、62:位线
100:存储单元
120:底电极
125:底电极宽度
130:存储材料层
140:顶电极
145:顶电极宽度
150:主动区域
160、170:介电层
180:导电栓塞
190:介电层
200:存储单元
220:底电极
230:柱状存储材料
240:顶电极
245:电极宽度
250:主动区域
260、270:介电层
280:导电栓塞
300:存储单元
308:介电间隔物
309:介电间隔物外表面
320:底电极
322:底部部份
323:第一宽度
324:柱状部份
325:第二宽度
326:柱状部份外表面
330:存储元件
332:存储元件厚度
334:存储元件宽度
340:顶电极
350:主动区域
310、360、370:介电层
380:导电栓塞
400:存储单元
408:介电间隔物
409:介电间隔物外表面
420:倒T型底电极
421:底电极外表面
422:底部部份
423:第一宽度
424:柱状部份
425:第二宽度
426:柱状部份外表面
430:存储元件
432:存储元件厚度
440:顶电极
450:主动区域
500:存储器存取层
502:上表面
620:底电极材料层
630:掩模元件
632:亚光刻宽度
700:部份刻蚀层
710:柱状物
711:侧壁
712:高度
720:厚度
800:顺形层
810:厚度
1100:存储材料层
1110:上表面
1400:底电极材料层
1410:存储材料层
1420:顶电极材料层
1430:掩模元件
1432:亚光刻宽度
1500:部份刻蚀层
1510:柱状物
1520:厚度
1530:多层叠层
1600:顺形层
1610:厚度
1900:上表面
具体实施方式
以下的发明说明将参照至特定结构实施例与方法。可以理解的是,本发明的范畴并非限制于特定所揭露的实施例,且本发明可利用其它特征、元件、方法与实施例进行实施。较佳实施例是被描述以了解本发明,而非用以限制本发明的范畴,本发明的范畴是以权利要求范围所定义。熟习该项技艺者可以根据后续的叙述而了解本发明的均等变化。在各实施例中的类似元件将以类似标号进行指定。
后续的发明说明将参照至图1至图21。
图1绘示先前技术具有一「伞状」存储单元100的剖面图,此存储单元100具有一存储材料层130于一底电极120与一顶电极140之间。一导 电栓塞180延伸通过一介电层170与此存储单元100的底层存取电路(未示)连接。一介电层190围绕在底电极120之间,且另一介电层160围绕在顶电极140及存储材料层130之间。此底电极120具有一宽度125小于该顶电极140和及存储材料层130的该宽度145。
在操作中,在栓塞180与顶电极140之上的电压可以诱发电流自栓塞180经过底电极120和存储材料130流至顶电极140,或反之亦然。
由于宽度125及宽度145的差异,在操作上在邻接于该底电极120的该存储材料层130的区域中,该电流密度将会为最大,使得该相变化材料130的该主动区域150具有一「伞状」,如图1中所示。
希望最好能减少底电极120的宽度125(其在某些实施例中是一直径)如此可以在较小电流绝对值流经此存储材料130的情况下达到较高的电流密度。
然而,尝试减少宽度125会因为在底电极120与栓塞180接口之间较小的接点面积而引起电性及结构可靠性方面的问题。
图2绘示一先前技术「柱状」存储单元200的一剖面图。该柱状存储单元200包含一多层存储柱290,其包含一底电极220、一存储材料柱230位于该底电极220之上、一顶电极240位于该存储材料柱230之上。一介电层260围绕该存储材料柱230。一导电栓塞280延伸通过一介电层270与此存储单元200的底层存取电路(未示)连接。
如在图2中可见,该顶电极240及该底电极220具有相同的宽度245,亦与该存储材料柱230相同。因此该主动区域250可位于远离该顶电极240与底电极220之间的区域。
此外,可以通过依序形成一底电极材料、一存储材料于底电极材料的上、一顶电极材料于存储材料的上、以及顺序刻蚀来形成该多层存储柱290。然而在制造此等具有较小宽度245及较大宽深比的装置会因为侧削刻蚀或过度刻蚀所引发一些问题。此外,尝试减少宽度245仍会因为在底电极220与栓塞280接口之间较小的接点面积而引起电性及结构可靠性方面的问题。
图3是绘示依据本发明一实施例的一存储单元300的剖面图,相较于图1中的结构,其可以解决上述的问题而改善结构的结构稳定性。该存储 单元300具有一倒T形的底电极320,其具有一衬底部分322及一柱状部份324于衬底部分322之上。此衬底部分322具有一第一宽度323(其在某些实施例中是一直径)以及此柱状部份324具有一小于第一宽度323的第二宽度325(其在某些实施例中是一直径)。此底电极320衬底部分322的较大第一宽度323提供了此底电极320的较佳结构稳定性。
此柱状部份324的顶表面与一存储元件330连接、此底电极320将存储元件330与导电拴塞380耦接。此底电极320可以是,例如氮化钛,或氮化钽。在存储元件330包含GST的实施例中(以下所描述),最佳电极材料是氮化钛,因为其与GST具有较佳的接触特性,且其是半导体工艺中所常用的材料,并在GST转换的高温下,通常是600~700℃范围,提供良好的扩散势垒特性。替代地,此底电极320可以是TiAlN,或TaAlN,或包含,例如,一或多个元素选自于由钛,钨,钼,铝,钽,铜,铂,铱,镧,镍,氮,氧,钌,以及其组合所组成的群组。
此导电栓塞380延伸通过一介电层370至底下的存取电路(未示),此导电栓塞380在此实施例中包含一个如钨等坚固金属。其它的金属如钛,钼,铝,钽,铜,铂,铱,镧,镍,钌也可以被使用。其它的栓塞结构或材料也可以被使用。
一顶电极340与该存储元件330连接,此顶电极340包含如之前所述的底电极320材料的一种或多种导电材料。此顶电极340可以包含位线的一部份。替代地,一导电介层孔(未示)可以将顶电极340与位线耦接。此顶电极340、存储元件330及底电极320构成此存储单元300的一存储器核心。
一介电间隔物308与此柱状部分324的外表面326连接且环绕于此柱状部分324。在形成底电极320之时,此介电间隔物308保护底电极320的衬底部分322不会受到刻蚀。因此,衬底部分322的外表面321与该介电间隔物308的一外表面309自动对准。
介电层310环绕于此介电间隔物308与底电极320的衬底部分322。此介电间隔物308与介电层310最好分别包含阻挡存储元件330的相变化材料扩散的材料,且在某些实施例中,此介电间隔物308与介电层310包含相同的材料。替代地,此介电间隔物308的材料可以选取,举例而言, 具有较低的热导系数(以下将会进一步详细描述)及/或在形成底电极320之时(以下将会进一步搭配图5到图13详细描述)作为具有选择性的工艺。
此介电间隔物308可以包含一电性绝缘材料其包括一或多个元素选自于由硅,钛,铝,钽,氮,氧,碳所组成的群组。在较佳装置的实施例中,介电材料具有一较低的导热率,低于0.014J/cm×K×sec。在其它较佳实施例中,当存储元件330是相变化材料时,此介电间隔物308的导热率可以低于非晶态的相变化材料,或就包含GST的相变化材料而言,低于大约0.003J/cm×K×sec。绝热材料的代表包含由Si、C、O、F、与H等元素所选出的一组合。举例而言,可作为绝热介电间隔物308的材料包括SiO2、SiCOH、聚亚酰胺(polyimide)、聚酰胺(polyamide)、以及氟碳聚合物。至于其它可作为绝热介电间隔物材料范例则为氟化SiO2、硅酸盐、芳香醚、聚对二甲苯(parylene)、聚合氟化物、非晶质氟化碳、钻石结构碳、多孔二氧化硅、中孔二氧化硅(mesoporous silica)、多孔硅酸盐、多孔聚亚酰胺、与多孔芳香醚。在其它实施例中,此绝热结构包含以气体填充的空孔作为绝热之用。单层结构或多层结构的组合,均可提供绝热功能。在以下图5到图13所描述的工艺中,此介电间隔物308亦可以作为一刻蚀掩模,且因此也可以因为其刻蚀选择性而被选取。
一介电层360环绕于此存储元件330,且在某些实施例中,此介电层360包含与介电层310相同的材料。
在操作中,栓塞380与顶电极340之上的电压可以诱发电流自栓塞380经过底电极320和存储元件330流至顶电极340,或反之亦然。
主动区域350是该存储元件330中的存储材料引起至少两种固相状态之间转换的区域。可察知地,该主动区域350该绘示结构中可以被制造地特别的小,因此降低引起一相变化所需要的电流大小。此存储元件330中存储材料的厚度332可以通过一薄膜沉积技术在底电极320之上形成一存储材料而达到。在某些实施例中,此厚度332是小于或等于100纳米,举例而言,介于10到100纳米之间。更者,此底电极320中柱状部分324的宽度或直径325小于该存储元件330的宽度或直径334,同时较佳地小于一般用来形成该存储单元300的一光刻工艺的一最小特征尺寸。此较小的底电极320柱状部分324使得电流密度集中于存储元件330靠近此底电 极320处,因此降低在该主动区域350中引起一相变化所需要的电流大小。此外,此介电间隔物308最好可以对该主动区域350提供热隔离,这样也可以帮助降低引起一相变化所需的电流大小。
此具有倒T形的底电极320可以在两方面改善结构的结构稳定性。第一,在底电极320与栓塞380之间所增加的面积同时也增加了整体单元的强度。第二,此设计将弱点的位置(即,此底电极320终端平面最狭窄之处)自底电极320与栓塞380的界面处移到一单石材料层(底电极320)中。此外,在底电极320与其底层栓塞380之间电阻值亦会因为接点面积的增加而减少。
图4是绘示依据本发明一实施例的一第二存储单元400的剖面图,相较于图2中的结构,其可以解决上述的问题而改善结构的结构稳定性。该存储单元400具有一倒T形的底电极420,其具有一衬底部分422及一柱状部份424于衬底部分422之上。此衬底部分422具有一第一宽度423(其在某些实施例中是一直径)以及此柱状部份424具有一小于第一宽度423的第二宽度425(其在某些实施例中是一直径)。此底电极420衬底部分422的较大第一宽度423提供了此底电极420的较佳结构稳定性。
此柱状部份424的顶表面与一存储元件430连接、此底电极420将存储元件430与导电拴塞380耦接。此底电极420,可以是,例如于图3中所讨论过的任何一种底电极320的材料。
如图4中所示,此柱状存储元件430的宽度以及此顶电极440的宽度是大致与此底电极420柱状部份424的宽度425相等。在此处所用的”大致”名词是用来符合工艺容忍度之用。因此,柱状存储元件430具有一主动区域450其可以与底电极420和顶电极440两者分离。此顶电极440可以包含例如,于图3中所讨论过的任何一种顶电极320的材料。此顶电极440、存储元件430及底电极420构成此存储单元400的一存储器核心。
一介电间隔物408与此柱状部分424的外表面426连接且环绕于此柱状部分424。在形成底电极420的衬底部分422之时,此介电间隔物408可以保护底电极420的衬底部分422不会受到刻蚀。因此,底电极420衬底部分422的外表面421与该介电间隔物408的一外表面409自动对准。
此介电间隔物408可以包含例如,于图3中所讨论过的任何一种介电 间隔物308的材料。此介电间隔物408最好包含阻挡存储元件430的相变化材料扩散的材料。在以下图14到图19所描述的工艺中,此介电间隔物408作为在形成底电极420之时的刻蚀掩模,因此最好包含具有选择性的材料。
一介电层410环绕于此介电间隔物408及底电极420的衬底部分422。在某些实施例中,此介电间隔物408及介电层410包含相同的材料。替代地,此介电间隔物408的材料可以选取,举例而言,具有较低的热导系数(以下将会进一步详细描述)及/或在形成存储单元400之时(以下将会进一步搭配图14到图19详细描述)作为具有选择性的工艺(例如选择性刻蚀)。
在操作中,栓塞380与顶电极440之上的电压可以诱发电流自栓塞380经过底电极420和存储元件430流至顶电极440,或反之亦然。
主动区域450是该存储元件430中的存储材料引起至少两种固相状态之间转换的区域。可察知地,该主动区域450该绘示结构中可以被制造地特别的小,因此降低引起一相变化所需要的电流大小。此存储元件430中存储材料的厚度432可以通过一薄膜沉积技术在底电极420之上形成一存储材料而达到。在某些实施例中,此厚度432是小于或等于100纳米,举例而言,介于10到100纳米之间。更者,此底电极420中柱状部分424的宽度或直径425等于该存储元件430及顶电极440的宽度或直径。因此,此主动区域450其可以与底电极420和顶电极440两者分离,且存储元件430的其余部份可以对该主动区域450提供热隔离。更者,此宽度425最好是小于一般用来形成该存储单元400的一光刻工艺的一最小特征尺寸。此外,此介电间隔物408最好是包含一材料可以对该主动区域450提供热隔离,这样也可以帮助降低引起一相变化所需的电流大小。
如同之前在图3中所描述的相同原因,此底电极420可以在两者之间提供额外的结构稳定性以及改善了在底电极420与其栓塞380之间接口的表现。
存储单元300、400的实施例包含相变化为基础的存储器材料,包含硫属化物为基础的材料以及其它材料,分别作为存储元件330、430。硫族元素(Chalcogens)包含任何四个元素的一氧(oxygen,O),硫(sulfur,S),硒(selenium,Se),以及碲(tellurium,Te),形成周期表的第VIA族的部分。硫 属化物包含一硫族元素与一更为正电性的元素或自由基的化合物。硫属化物合金包含硫属化物与其它材料如过渡金属的结合。一硫属化物合金通常包含一或多个选自元素周期表第IVA族的元素,例如锗(Ge)以及锡(Sn)。通常,硫属化物合金包含组合一或多个锑(Sb)、镓(Ga)、铟(In)、以及银(Ag)。许多相变化为基础的存储材料已经被描述于技术文件中,包括下列合金:镓/锑、铟/锑、铟/硒、锑/碲、锗/碲、锗/锑/碲、铟/锑/碲、镓/硒/碲、锡/锑/碲、铟/锑/锗、银/铟/锑/碲、锗/锡/锑/碲、锗/锑/硒/碲、以及碲/锗/锑/硫。在锗/锑/碲合金家族中,一大范围的合金合成物是可行的。该合成物可以表式为TeaGebSb100-(a+b)。一位研究员描述了最有用的合金为,在沉积材料中所包含的平均碲浓度是远低于70%,典型地是低于60%,并在一般型态合金中的碲含量范围从最低23%至最高58%,且最佳是介于48%至58%的碲含量。锗的浓度是高于约5%,且其在材料中的平均范围是从最低8%至最高30%,一般是低于50%。最佳地,锗的浓度范围是介于8%至40%。在此合成物中所剩下的主要组成元素为锑。上述百分比为原子百分比,其为所有组成元素加总为100%。(Ovshinsky‘112专利,栏10-11)由另一研究者所评估的特殊合金包括Ge2Sb2Te5、GeSb2Te4、以及GeSb4Te7。(Noboru Yamada,“Potential of Ge-Sb-Te Phase-change OpticalDisks for High-Data-Rate Recording”,SPIE v.3109,pp.28-37(1997))更一般地,一过渡金属如铬(Cr)、铁(Fe)、镍(Ni)、铌(Nb)、钯(Pd)、铂(Pt)、以及上述的混合物或合金,可与锗/锑/碲结合以形成一相变化合金其具有可编程的电阻特性。有用的存储材料的特殊范例,例如Ovshinsky‘112专利中栏11~13所述,其范例在此被列入参考。
在某些实施例中,可在硫属化物及其它相变化材料中掺杂物质以改善使用掺杂硫属化物作为存储元件的导电性、转换温度、熔化温度及其它等性质。代表性的掺杂物质为:氮、硅、氧、二氧化硅、氮化硅、铜、银、金、铝、氧化铝、钽、氧化钽、氮化钽、钛、与氧化钛。可参见美国专利第6,800,504号与美国专利申请US 2005/0029502号。
相变化合金可于一第一结构态与第二结构态之间切换,其中第一结构态是指此材料大体上为非晶固相,而第二结构态是指此材料大体上为结晶固相。这些合金系至少为双稳定的(bistable)。此词汇「非晶」是用以指称 一相对较无次序的结构,其较之一单晶更无次序性,而带有可检测的特征如比结晶态更高的电阻值。此词汇「结晶」是用以指称一相对较有次序的结构,其较之非晶态更有次序,因此包括有可检测的特征例如比非晶态更低的电阻值。典型地,相变化材料可电切换至完全结晶态与完全非晶态之间所有可检测的不同状态。其它受到非晶态与结晶态的改变而影响的材料特性中包括,原子次序、自由电子密度、以及活化能。此材料可切换成为不同的固态、或可切换成为由两种以上固态所形成的混合物,提供从非晶态至结晶态之间的灰阶部分。此材料中的电性质亦可能随之改变。
相变化材料可利用电脉冲由一相态改变至另一相态。就过去的观察,得知时间较短、振幅较大的脉冲,较倾向将相变化材料转为通常的非晶态;而时间长、振幅较低的脉冲,则易将相变化材料转为通常的结晶态。时间短且振幅高的脉冲,能量较高,足以破坏结晶态的键能,同时缩短时间可防止原子重新排列为结晶态。无须大量实验,即可获得适当的脉冲参数,以应用于特定的相变化材料与装置结构。于此揭露者,相变化或是其它存储材料通常是指GST,但亦可采用其它种类的相变化材料。此处揭露一种可作为相变化只读存储装置(PCRAM)的材料为Ge2Sb2Te5。
其它可编程材料,可作为本发明其它实施例的存储器材料,包括注入N2的GST、GexSby、或其它利用晶相变化决定电阻的;亦可采用PrxCayMnO3、PrSrMnO、ZrOx、或其它以电脉冲改变电阻的材料;7,7,8,8-tetracyanoquinodimethane(TCNQ)、methanofullerene 6,、6-phenylC61-butyric acid methyl ester(PCBM)、TCNQ-PCBM、Cu-TCNQ、Ag-TCNQ、C60-TCNQ、TCNQ注入其它金属、或其它具有双重或多种稳定电阻状态并可由电脉冲控制的高分子材料。
用来形成硫属化物材料的示范方法,是利用PVD溅射或磁电管溅射方式,其反应气体为氩气、氮气、及/或氦气等以及硫属化物,在压力为1mTorr至100mTorr。此沉积步骤一般是于室温下进行。一长宽比为1~5的准直器可用以改良其注入表现。为了改善其注入表现,亦可使用数十至数百伏特的直流偏压。另一方面,同时合并使用直流偏压以及准直器亦是可行的。
有时需要在真空中或氮气环境中进行一沉积后退火处理,以改良硫属 化物材料的结晶态。此退火处理的温度典型地是介于100℃至400℃,而退火时间则少于30分钟。
硫属化物材料的厚度,将依据存储单元结构的厚度设计而改变。通常而言,硫属化物材料的厚度约大于1.5nm,即可呈现两个稳定态,而展现相变化的特征。
图5至图13根据本发明实施例来制造图3中所描述的存储单元的工艺步骤序列示意图。
图5显示此工艺第一步骤完成结构的剖面示意图,是提供一具有一上表面502及包含导电栓塞380延伸通过介电层370而至此上表面502的存储器存取层500。此存储器存取层500可以利用业界所熟知的任何方式形成,且此存储器存取层500的组态是取决于此处所描述的存储单元实际应用的阵列组态。一般而言,此存储器存取层500可以包含例如晶体管、字线及源极线、导电栓塞和衬底中的掺杂区域等存取元件
之后,一底电极材料层620形成于存储器存取层500的上表面502之上,且一包含一掩模元件630的刻蚀掩模形成于底电极材料层620之上而构成图6中所示的结构。此底电极材料层620可以包含如图3中所讨论的底电极320的一种或多种材料。
此掩模元件630可以通过使用光刻工艺来图案化形成于底电极材料层620之上的一光刻胶层,然后将此图案化的光刻胶层进行修剪以形成具有亚光刻宽度632的掩模元件630,举例而言,在某些实施例中小于50微米。光刻胶修剪可以使用像是氧气等离子体来进行以等向性刻蚀光刻胶层,并同时在水平及垂直方向上减少光刻胶层的尺寸。在一替代实施例中,一个如低温沉积的氮化硅或二氧化硅的硬式掩模可以使用光刻技术来图案化,之后再使用等向性湿法刻蚀来修剪,例如使用稀释的氢氟酸来刻蚀二氧化硅或是使用热磷酸来刻蚀氮化硅,或是使用等向性的氟化或是溴化氢基础的反应式离子刻蚀。
之后,使用掩模元件630作为刻蚀掩模进行利用时间模式的非等向性刻蚀于底电极材料层620,因此形成包含剩余底电极材料层620的部份刻蚀层700。然后除去此掩模元件630,而形成如图7所绘示的结构。此层700包含一具有侧壁711及掩模元件630下方的柱状物710,其并不延伸 通过层700。在一范例中,此柱状物具有一约为40到120微米的高度712,举例而言,可以是60微米。层700的剩余部份具有一足以提供如上所讨论的结构强度的厚度720。
此时间模式的非等向性刻蚀可以使用例如氯化物或是氟化物为基础的反应式离子刻蚀。在一实施例中,氮化钛可以使用氯化物为基础的反应式离子刻蚀进行非等向性刻蚀,而在另一实施例中,氮化钽可以使用一相似地氯化物为基础的刻蚀工艺。
之后,一介电间隔物的顺形层800被形成于图7的结构上,其具有厚度810而形成如图8所绘示的结构。在此例示的实施例中,层800包含二氧化硅且使用化学气相沉积所形成。其它的材料只要其刻蚀选择性适合及具有可以顺形地形成在高深宽比结构中的能力也可以作为层800。此外,其它的工艺,例如原子层沉积、物理层沉积、低压化学气相沉积或是高密度等离子体化学气相沉积均可以用来形成层800,取决于相关的材料及几何形状。
之后,进行非均向性刻蚀于如图8所绘示的层700及800,而形成如图9所绘示的结构,其具有一倒T型底电极320及一介电间隔物308。
在图9所绘示的结构中,此介电间隔物308及倒T型底电极320具有大致相等共平面的顶表面,但是可以理解的是此介电间隔物308及倒T型底电极320在非等向性刻蚀之后可以具有其它替代地不是共平面的顶表面。此介电间隔物308及倒T型底电极320的顶表面相对位置是取决于许多因素包含厚度720和810,层700和800的材料,及所使用的刻蚀配方等。
在非等向性刻蚀时,此介电间隔物308保护此底电极320的底部部分322,则因此此底电极320的底部部分322具有一外表面321会与介电间隔物308的外表面309自动对准。
此非等向性刻蚀过程可以是单一刻蚀同时刻蚀层700和800。或是替代地可以是两步骤刻蚀,先利用第一刻蚀化学配方非等向性刻蚀层800以形成介电间隔物308,再使用介电间隔物308作为刻蚀掩模来利用第二刻蚀化学配方刻蚀层700以形成底电极320。
之后,一介电材料层310形成于图9所绘示的结构之上再进行平坦化, 而形成如图10所绘示的结构,其具有一上表面1000。在一工艺实施例中,此介电材料层310是利用高密度等离子体化学气相沉积法(HDP CVD)形成,之后再进行化学机械抛光以裸露此底电极320。在一实施例中,此介电层310可以包括二氧化硅利用化学气相沉积法使用硅甲烷和氧气在400到450℃生成。在此介电材料层310为氮化硅的实施例中,利用一个类似的工艺使用硅甲烷和氨水所生成。在此介电材料层310为氮氧化硅的实施例中,是利用硅甲烷、氧气和氨水所生成。此介电材料层310可以包含二氧化硅、氮化硅或是其它绝缘材料,最好是具有良好的热绝缘以及电绝缘特性。
一存储材料层1100然后形成在此上表面1000之上,且一顶电极材料层1110然后形成在此存储材料层1100之上,而形成如图11所绘示的结构。此存储材料层1100和顶电极材料层1110的厚度可以各自是小于或等于100纳米,举例而言,介于10到100纳米之间。
之后,此存储材料层1100和顶电极材料层1110被图案化以形成多层叠层,其包含一存储元件330和一顶电极340,而形成如图12所绘示的结构。替代地,此存储材料层1100和顶电极材料层1110也可以被图案化由顶电极层1110形成位线。此底电极320、存储元件330和一顶电极340构成一存储器核心。
之后,另一介电层360形成于图12所绘示的结构之上再进行平坦化,而形成如图13所绘示的结构。
图4至图19根据本发明实施例来制造图4中所描述的存储单元的工艺步骤序列示意图。
图14显示此工艺部分完成结构的剖面示意图,是形成一底电极材料层1400于图5中的存储器存取层500的上表面502之上,及形成一存储层1410于底电极材料层1400之上,和及形成一顶电极材料层1420于存储层1410之上,然后形成一包含一掩模元件1430的刻蚀掩模于顶电极材料层1420之上。此底电极材料层1400可以包含如图3中所讨论的底电极320的一种或多种材料。
此掩模元件1430可以通过使用光刻工艺来图案化形成于顶电极材料层1420之上的一光刻胶层,然后将此图案化的光刻胶层进行修剪以形成 具有亚光刻宽度1432的掩模元件1430,举例而言,在某些实施例中小于50微米。光刻胶修剪可以使用像是氧气等离子体来进行以等向性刻蚀光刻胶层,并同时在水平及垂直方向上减少光刻胶层的尺寸。在一替代实施例中,一个如低温沉积的氮化硅或二氧化硅的硬式掩模可以使用光刻技术来图案化,之后再使用等向性湿法刻蚀来修剪,例如使用稀释的氢氟酸来刻蚀二氧化硅或是使用热磷酸来刻蚀氮化硅,或是使用等向性的氟化或是溴化氢基础的反应式离子刻蚀。
之后,使用掩模元件1430作为刻蚀掩模进行利用时间模式的非等向性刻蚀,因此形成包含剩余底电极材料层1400的部份刻蚀层1500,以及包含底电极材料层1400的柱状物1510和形成一多层叠层1530于柱状物1510之上。此多层叠层1530包含存储元件430于柱状物1510之上,及顶电极440于存储元件430之上。然后除去此掩模元件1430,而形成如图15所绘示的结构。此层1500包含一柱状物1510,其并不延伸完全通过层1500。此多层叠层1530具有一大致与柱状物1510相等的宽度。层1500的剩余部份具有一足以提供如上所讨论的结构强度的厚度1520。
此时间模式的非等向性刻蚀可以使用例如氯化物或是氟化物为基础的反应式离子刻蚀。在一实施例中,氮化钛可以使用氯化物为基础的反应式离子刻蚀进行非等向性刻蚀,而在另一实施例中,氮化钽可以使用一相似地氯化物为基础的刻蚀工艺。
之后,一介电间隔物的顺形层1600被形成于图15的结构上,其具有厚度1610而形成如图16所绘示的结构。在此例示的实施例中,层1600包含二氧化硅且使用化学气相沉积所形成。其它的材料只要其刻蚀选择性适合及具有可以顺形地形成在高深宽比结构中的能力也可以作为层1600。此外,其它的工艺,例如原子层沉积、物理层沉积、低压化学气相沉积或是高密度等离子体化学气相沉积均可以用来形成层1600,取决于相关的材料及几何形状。
之后,进行非均向性刻蚀于如图16所绘示的层1600以形成介电间隔物408,而形成如图17所绘示的结构。
之后,使用介电间隔物408作为刻蚀掩模来刻蚀层1400,生成如图18所绘示的结构,其具有包含底部部分422和柱状部份424于底部部分 422之上的倒T型底电极420。此底电极420、存储元件430和顶电极440构成一存储器核心。
因为在刻蚀层1400时,是利用介电间隔物408作为刻蚀掩模,因此底电极420的底部部分422具有一外表面421会与介电间隔物408的外表面409自动对准。
在图18中,底电极420包含一材料其可以与顶电极440的材料具有刻蚀选择性,且因此顶电极440亦可以在刻蚀层1400时作为刻蚀掩模。或是替代地顶电极440也可以被刻蚀。
在一替代实施例中,一个合适的硬式掩模可以沉积于图14中的顶电极材料层1420之上,且此掩模元件1430形成于此硬式掩模之上,再利用后续的图15中的刻蚀步骤导致一部份的硬式掩模层仍保留在多层叠层1530之上。此剩余部份的硬式掩模层会在刻蚀层1400时保护顶电极440。
之后,一介电材料层410形成于图18所绘示的结构之上再进行平坦化,而形成如图19所绘示的结构,其具有一上表面1900。在一工艺实施例中,此介电材料层410是利用高密度等离子体化学气相沉积法(HDPCVD)形成,之后再进行化学机械抛光以裸露此顶电极440。在一实施例中,此介电材料层410可以包括二氧化硅利用化学气相沉积法使用硅甲烷和氧气在400到450℃生成。在此介电材料层410为氮化硅的实施例中,利用一个类似的工艺使用硅甲烷和氨水所生成。在此介电材料层410为氮氧化硅的实施例中,是利用硅甲烷、氧气和氨水所生成。此介电材料层410可以包含二氧化硅、氮化硅或是其它绝缘材料,最好是具有良好的热绝缘以及电绝缘特性。
之后,可以进行后续的工艺例如形成一位线其与此存储单元耦接。
图20显示应用本发明的集成电路10的简易方块示意图。该集成电路10包含一存储阵列12其使用如图3及图4所描述的存储单元。一字线译码器14电性连接至许多的字线16。一位线(行)译码器18电性连接至许多的位线20,以读取和写入存储器阵列12中相变化存储单元(未示)的数据。地址经由总线22提供给字线译码器及驱动器14和位线译码器18。在区块24中,感应放大器和数据输入结构,经由数据总线26连接至位线译码器18。数据是经由该数据输入线28,从该集成电路10的输入/输出端,或从 其它内部或外部的数据来源,至在区块24中的数据输入结构。其它电路30是被包含于该集成电路10中,例如一通用目的处理器或特殊目的应用电路,或是一模块的组合,提供由阵列12所支持的单芯片***功能。数据是经由该数据输出线32,从在区块24中的感应放大器,至集成电路10的输入/输出端,或至其它集成电路10内部或外部数据目的地。
在此范例所实施的一控制器电路34,使用偏压调整状态机构控制偏压调整供应电压36的应用,例如读取,编程,擦除,擦除验证,以及编程验证电压。该控制器34可以使用业界所熟知的技术,如特殊目的逻辑电路来实施。在另一实施例中,该控制器34包含一通用目的处理器,其可以实施在相同集成电路上,其执行一计算机程序以控制该装置的操作。在另一实施例中,特殊目的逻辑电路和一通用目的处理器的组合可以被用来实施该控制器34。
如图21所示,阵列12中的每个存储单元包括了一个存取晶体管(或其它存取装置,例如二极管)、以及相变化元件,其中四个存取晶体管在图中是以标号38、40、42、44显示的,而四个相变化元件在图中是以标号46、48、50、52显示的,以及四个倒T型底电极在图中是以标号47、49、51、53显示的。每个存取晶体管38、40、42、44的源极是共同连接至一源极线54,源极线54是在一源极线终端55结束。在另一实施例中,这些存取元件的源极线并未电性连接,而是可独立控制的。多条字线包括字线56与58是沿着第一方向平行地延伸。字线56、58是与字线译码器14进行电***换信息。存取晶体管38、42的栅极是连接至一共同字线,例如字线56,而存取晶体管40、44的栅极是共同连接至字线58。多条位线20包括位线60、62是连接到相变化元件46、48的一端,其是连接至位线60。特别地,相变化元件46是连接于存取晶体管38的漏极与位线60之间,而相变化元件48是连接于存取晶体管40的漏极与位线60之间。相似地,相变化元件50是连接于存取晶体管42的漏极与位线62之间,而相变化元件52是连接于存取晶体管44与位线62之间。需要注意的是,在图中为了方便起见,仅绘示四个存储单元,在实际应用中,阵列12可包括上千个至上百万个此种存储单元。同时,亦可使用其它阵列结构,例如将相变化存储元件连接到存取晶体管的源极。此外,除了金属氧化物半 导体场效晶体管之外,双极晶体管或是二极管也可以用来作为存取元件。
本发明虽然是描述相变化材料,然而,其它的存储器材料,有时称为可编程材料也可以被使用。应用在此用途时,存储材料是具有可以通过能量改变电性,如电阻,的特性的材料;此改变可以为步进或是连续的改变或是其组合。
本发明的揭露是通过参照以上所描述的最佳实施例和范例,可以了解的是,这些范例仅只是用于描述而非限制本发明。可以了解的是,修改和组合将会发生在熟习此项技术的人士,其修改和组合将会落入本发明的精神以及权利要求范围内。
Claims (9)
1.一种存储单元,其特征在于,包含:
一底电极包含一衬底部份及一柱状部份于该衬底部份之上,该柱状部份及该衬底部分具有各自的外表面且该柱状部分具有一宽度小于该衬底部份的宽度;
一存储元件于该底电极的该柱状部分的一上表面之上,该存储元件的宽度与该柱状部份的宽度相同;
一顶电极于该存储元件之上,该顶电极与该存储元件的宽度相同;以及
一介电间隔物与该柱状部分、该存储元件、以及该顶电极的该外表面连接,该底电极的该衬底部分的该外表面与该介电间隔物的一外表面自动对准。
2.根据权利要求1所述的存储单元,其特征在于,该介电间隔物环绕该底电极的该柱状部分与该存储元件。
3.根据权利要求1所述的存储单元,其特征在于,该介电间隔物具有一热导系数低于该存储元件。
4.一种制造一存储单元的方法,其特征在于,该方法包含:
形成一存储器核心,包含:
一底电极包含一衬底部份及一柱状部份于该衬底部份之上,该柱状部份及该衬底部分具有各自的外表面且该柱状部分具有一宽度小于该衬底部份的宽度;
一存储元件于该底电极的该柱状部分的一上表面之上,该存储元件的宽度与该柱状部份的宽度相同;
一顶电极于该存储元件之上,该顶电极与该存储元件的宽度相同;以及
形成一介电间隔物与该柱状部分、该存储元件、以及该顶电极的该外表面连接,该底电极的该衬底部分的该外表面与该介电间隔物的一外表面自动对准。
5.根据权利要求4所述的方法,其特征在于,形成一存储器核心的步骤,包含:
形成一存储材料层于该底电极之上;
形成一顶电极材料层于该存储材料层之上;以及
图案化该存储材料层及该顶电极材料层以形成包含该存储元件及该顶电极的多层叠层。
6.根据权利要求4所述的方法,其特征在于,形成一存储器核心以及形成一介电间隔物的步骤,包含:
提供一存储器存取层,其具有一顶表面,该存储器存取层包括一导电栓塞延伸至该存储器存取层的该顶表面;
形成一底电极材料层于该存储器存取层的该顶表面层之上;
形成一刻蚀掩模于该底电极材料层之上;
使用该刻蚀掩模以刻蚀通过该底电极材料层的一部份,因此形成一包括底电极材料柱状物的部分刻蚀层;
形成一介电间隔物材料层于该部分刻蚀层之上;以及
刻蚀该介电间隔物材料层及该部分刻蚀层以形成该介电间隔物及该底电极。
7.根据权利要求6所述的方法,其特征在于,刻蚀该介电间隔物材料层及该部分刻蚀层的步骤,包含:
非等向性刻蚀该介电间隔物材料层以形成该介电间隔物;以及
使用该介电间隔物作为一刻蚀掩模来刻蚀该部分刻蚀层,因此形成该底电极。
8.根据权利要求4所述的方法,其特征在于,形成一存储器核心的步骤,包含:
提供一存储器存取层,其具有一顶表面,该存储器存取层包括一导电栓塞延伸至该存储器存取层的该顶表面;
形成一底电极材料层于该存储器存取层的该顶表面层之上;
形成一存储材料层于该底电极之上;
形成一顶电极材料层于该存储材料层之上;
形成一刻蚀掩模于该顶电极材料层之上;以及
使用该刻蚀掩模以刻蚀通过该底电极材料层的一部份,因此形成一包括底电极材料柱状物的部分刻蚀层以及一多层叠层于该底电极材料柱状物之上,该多层叠层包含一存储元件其包含存储材料于该底电极材料柱状物之上及一顶电极其包含顶电极材料于该存储元件之上。
9.一种制造一存储单元的方法,其特征在于,该方法包含:
提供一存储器存取层,其具有一顶表面,该存储器存取层包括一导电栓塞延伸至该存储器存取层的该顶表面;
形成一底电极材料层于该存储器存取层的该顶表面层之上;
形成一存储材料层于该底电极之上;
形成一顶电极材料层于该存储材料层之上;
形成一刻蚀掩模于该顶电极材料层之上;
使用该刻蚀掩模以刻蚀通过该底电极材料层的一部份,因此形成一包括底电极材料柱状物的部分刻蚀层以及一多层叠层于该底电极材料柱状物之上,该多层叠层包含一存储元件其包含存储材料于该底电极材料柱状物之上及一顶电极其包含顶电极材料于该存储元件之上;
形成一介电间隔物材料层于该部分刻蚀层及该多层叠层之上;
非等向性刻蚀该介电间隔物材料层以形成一介电间隔物与该底电极柱状物的一外表面以及该多层叠层的一外表面连接;以及
使用该介电间隔物作为一刻蚀掩模来刻蚀该部分刻蚀层,因此形成一底电极其包含一衬底部份及一柱状部份于该衬底部份之上。
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