CN1893104A - 相变存储器件及其制造方法 - Google Patents
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Abstract
本发明公开了一种相变存储器件及其制造方法。所述相变存储器件包括:下电极,电连接到形成于半导体衬底上的晶体管;第一绝缘层,覆盖所述下电极和所述衬底且具有暴露所述下电极的第一孔;导电接触,形成于所述第一孔中;第二绝缘层,形成于所述第一绝缘层上,具有对应于所述导电接触的第二孔;相变材料层,填充所述第二孔;和上电极,覆盖形成的所述相变材料层的上表面,其中,所述相变材料层和上电极基本对准,且所述上电极的宽度大于所述相变材料层的宽度。
Description
技术领域
本发明涉及一种相变存储器件及其制造方法。更具体而言,本发明涉及一种相变存储器件及其制造方法,其中防止在蚀刻时对其中的相变材料的损伤。
背景技术
相变存储器件(phase change memory device)由相变材料形成。相变材料根据提供到相变材料的电流的大小即焦耳能量成为晶态或非晶态,由此可以改变其导电率。通过对相变材料施加具有所需大小的电流而改变相变材料的相态,可以在由相变材料组成的存储单元中存储例如“0”和“1”的逻辑信息,且通过探测存储单元的电阻可以读出存储于存储单元中的例如“0”和“1”的逻辑信息。
图1是常规相变存储器件的横截面图。参考图1,常规相变存储器件包括下电极10、上电极18、夹置在下和上电极10和18之间的薄相变材料层16,以及电接触下电极10和相变材料层16的导电接触14。
下电极10和导电接触14的侧面部分接触绝缘层12的内壁,且下电极10电接触开关器件(未示出),例如,晶体管(未示出)。
为了在导电接触14上形成相变材料层16和上电极18,在绝缘层12上堆叠相变材料和导电层且执行蚀刻。
在蚀刻期间可能损伤相变材料层16的暴露的表面,由此降低存储器件的相变特性。具体而言,在小尺寸相变存储器件中,由蚀刻导致的损伤随着相变材料层16的宽度减小而增加。
发明内容
本发明提供了一种相变存储器件及其制造方法,其中当蚀刻上电极时,未暴露相变材料。
根据本发明的一方面,提供有一种相变存储器件,包括:下电极,电连接到形成于半导体衬底上的晶体管;第一绝缘层,覆盖下电极和衬底且具有暴露下电极的第一孔;导电接触,形成于第一孔中;第二绝缘层,形成于第一绝缘层上,具有对应于导电接触的第二孔;相变材料层,填充第二孔;和上电极,覆盖形成的相变材料层的上表面,其中,相变材料层和上电极基本对准,且上电极的宽度大于相变材料层的宽度。
上电极的宽度是相变材料层的宽度的4/3到3倍。
相变材料层可以由选自由碲(Te)、硒(Se)和硫(S)构成的组的至少一种硫属化物材料形成。
根据本发明的另一方面,提供有一种相变存储器件的制造方法,包括:在半导体衬底上形成下电极,所述下电极电连接到半导体衬底中的晶体管;在衬底上形成第一绝缘层,所述第一绝缘层覆盖下电极;在第一绝缘层上形成导电接触,所述导电接触电接触下电极;在第一绝缘层上形成第二绝缘层,所述第二绝缘层具有对应于导电接触的第一孔;沉积相变材料来填充第二绝缘层上的第一孔;平面化第二绝缘层和相变材料;以及在第二绝缘层和相变材料层上形成上电极,使得上电极覆盖相变材料层的上表面。
形成第二绝缘层可以包括形成具有第一宽度的第一孔,且形成上电极可以包括形成具有第二宽度的上电极,第二宽度大于第一宽度。
利用物理气相沉积(PVD)来执行沉积相变材料来填充孔。
附图说明
参考附图,通过详细描述其实施例,本发明的以上和其他特征和优点将变得更加显见,在附图中:
图1是常规相变存储器件的横截面图;
图2是根据本发明的实施例的相变存储器件的横截面图;和
图3A到3G是示出根据本发明的实施例的相变存储器件的制造方法的阶段的横截面图。
具体实施方式
以下将参考附图更加全面地描述本发明,在附图中示出了本发明的优选实施例。在附图中,相似的参考标号指示相似的元件。为了清晰,夸大了层和区域的尺寸和厚度。
图2是根据本发明的实施例的相变存储器件的横截面图。参考图2,相变存储器件100包括:下电极110,电连接到开关器件(未显示),例如晶体管的源电极或漏电极。下电极110形成于半导体衬底102上,且覆盖下电极110的第一绝缘层120形成于衬底102上。暴露下电极110的接触孔122形成于第一绝缘层120中,且用导电接触130填充。
第二绝缘层140形成于第一绝缘层120上,且具有暴露导电接触130的孔142。孔142具有第一宽度W1。相变材料层150填充孔142。
相变材料层150可以由选自由碲(Te)、硒(Se)和硫(S)构成的组的至少一种硫属化物材料形成。
接触相变材料层150的上电极160形成于第二绝缘层140上。上电极160相对于相变材料层150中心对准。上电极160的第二宽度W2大于第一宽度W1,且可以是第一宽度W1的4/3到3倍。上电极160和相变材料层150的位置和尺寸使得当蚀刻上电极160时没有暴露相变材料层150的表面。
导电接触130可以由TiN或TiAlN形成。
图3A到3G是示出根据本发明的实施例的相变存储器件的制造方法的阶段的横截面图。
参考图3A,使用常规方法在半导体衬底102上形成晶体管(未示出),且在衬底102上形成电极层。然后,通过使用常规构图工艺来构图电极层,从而形成下电极110。构图下电极110以电连接到晶体管的源极区。
参考图3B,在衬底102上沉积覆盖下电极110的第一绝缘层120。然后,构图第一绝缘层120来形成暴露下电极110的接触孔122。通过用导电材料填充接触孔122来形成导电接触130,导电材料例如TiN或TiAlN。
参考图3C,在第一绝缘层120上形成第二绝缘层140。然后,蚀刻第二绝缘层140来形成具有第一宽度W1的孔142,第一宽度W1大于导电接触130的上部宽度,由此暴露导电接触130。
参考图3D,使用物理气相沉积(PVD)用相变材料层150填充孔142。
相变材料层150可以由选自由碲(Te)、硒(Se)和硫(S)构成的组的至少一种硫属化物材料形成。
参考图3E,通过化学机械抛光(CMP)平面化相变材料层150和第二绝缘层140的上表面。
参考图3F,在相变材料层150上形成导电层162。
参考图3G,通过构图导电层162,在相变材料层150上形成具有第二宽度W2的上电极160。上电极160相对于相变材料层150中心对准。上电极160的第二宽度W2大于第一宽度W1,且可以是第一宽度W1的4/3到3倍。上电极160和相变材料层150的位置和尺寸使得当蚀刻上电极160时没有暴露相变材料层150的表面。
根据本发明的相变存储器件及其制造方法,因为当蚀刻上电极时没有暴露形成于绝缘层上的相变材料层,在蚀刻期间相变材料层没有损伤。于是,可以制造具有好相变性能的相变存储单元。
虽然参考优选的实施例已经具体显示和描述了本发明,但是本领域的技术人员可以理解在不脱离由权利要求界定的本发明的精神和范围的情况下可以在这里做出各种形式和细节的修改。
Claims (9)
1.一种相变存储器件,包括:
下电极,电连接到形成于半导体衬底上的晶体管;
第一绝缘层,覆盖所述下电极和所述衬底且具有暴露所述下电极的第一孔;
导电接触,形成于所述第一孔中;
第二绝缘层,形成于所述第一绝缘层上,具有对应于所述导电接触的第二孔;
相变材料层,填充所述第二孔;和
上电极,覆盖形成的所述相变材料层的上表面,
其中,所述相变材料层和所述上电极基本对准,且所述上电极的宽度大于所述相变材料层的宽度。
2.如权利要求1所述的器件,其中,所述上电极的宽度是所述相变材料层的宽度的4/3到3倍。
3.如权利要求1所述的器件,其中,所述相变材料层由选自由碲、硒和硫构成组的至少一种硫属化物材料形成。
4.一种相变存储器件的制造方法,包括:
在半导体衬底上形成下电极,所述下电极电连接到所述半导体衬底中的晶体管;
在所述衬底上形成第一绝缘层,所述第一绝缘层覆盖所述下电极;
在所述第一绝缘层上形成导电接触,所述导电接触电接触所述下电极;
在所述第一绝缘层上形成第二绝缘层,所述第二绝缘层具有对应于所述导电接触的第一孔;
沉积相变材料层来填充所述第二绝缘层上的所述第一孔;
平面化所述第二绝缘层和所述相变材料层;和
在所述第二绝缘层和所述相变材料层上形成上电极,使得所述上电极覆盖所述相变材料层的上表面。
5.如权利要求4所述的方法,其中,所述形成第二绝缘层包括形成具有第一宽度的所述第一孔,且所述形成上电极包括形成具有第二宽度的所述上电极,所述第二宽度大于所述第一宽度。
6.如权利要求5所述的方法,其中,所述相变材料层和所述上电极基本对准,
7.如权利要求6所述的方法,其中,所述第二宽度是所述第一宽度的4/3到3倍。
8.如权利要求4所述的方法,其中,利用物理气相沉积来执行所述相变材料层的沉积来填充所述孔。
9.如权利要求4所述的方法,其中,所述相变材料层由选自由碲、硒和硫构成的组的至少一种硫属化物材料形成。
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Cited By (5)
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CN100563041C (zh) * | 2007-05-18 | 2009-11-25 | 中国科学院上海微***与信息技术研究所 | 一种电阻存储器的器件单元结构及制作方法 |
CN101399314B (zh) * | 2007-09-25 | 2010-06-09 | 财团法人工业技术研究院 | 相变化存储器及其制造方法 |
CN101783390B (zh) * | 2008-04-07 | 2013-05-22 | 旺宏电子股份有限公司 | 具有改善结构稳定性的存储单元及其制造方法 |
CN107086269A (zh) * | 2016-02-16 | 2017-08-22 | 旺宏电子股份有限公司 | 存储器结构 |
CN109686755A (zh) * | 2018-12-26 | 2019-04-26 | 上海集成电路研发中心有限公司 | 高密度相变存储器及其制备方法 |
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US7579611B2 (en) * | 2006-02-14 | 2009-08-25 | International Business Machines Corporation | Nonvolatile memory cell comprising a chalcogenide and a transition metal oxide |
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KR100437458B1 (ko) * | 2002-05-07 | 2004-06-23 | 삼성전자주식회사 | 상변화 기억 셀들 및 그 제조방법들 |
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KR100593450B1 (ko) * | 2004-10-08 | 2006-06-28 | 삼성전자주식회사 | 수직하게 차례로 위치된 복수 개의 활성 영역들을 갖는피이. 램들 및 그 형성방법들. |
KR100625170B1 (ko) * | 2005-07-13 | 2006-09-15 | 삼성전자주식회사 | 전극 구조체, 이의 제조 방법, 이를 포함하는 상변화메모리 장치 및 그 제조 방법 |
KR100722769B1 (ko) * | 2006-05-19 | 2007-05-30 | 삼성전자주식회사 | 상변화 메모리 장치 및 이의 형성 방법 |
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2005
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- 2006-02-09 CN CN200610007121.4A patent/CN1893104A/zh active Pending
- 2006-02-10 US US11/350,856 patent/US20070008774A1/en not_active Abandoned
- 2006-05-29 JP JP2006148556A patent/JP2007019475A/ja active Pending
Cited By (6)
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CN100563041C (zh) * | 2007-05-18 | 2009-11-25 | 中国科学院上海微***与信息技术研究所 | 一种电阻存储器的器件单元结构及制作方法 |
CN101399314B (zh) * | 2007-09-25 | 2010-06-09 | 财团法人工业技术研究院 | 相变化存储器及其制造方法 |
CN101783390B (zh) * | 2008-04-07 | 2013-05-22 | 旺宏电子股份有限公司 | 具有改善结构稳定性的存储单元及其制造方法 |
CN107086269A (zh) * | 2016-02-16 | 2017-08-22 | 旺宏电子股份有限公司 | 存储器结构 |
CN107086269B (zh) * | 2016-02-16 | 2019-12-24 | 旺宏电子股份有限公司 | 存储器结构 |
CN109686755A (zh) * | 2018-12-26 | 2019-04-26 | 上海集成电路研发中心有限公司 | 高密度相变存储器及其制备方法 |
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KR20070006451A (ko) | 2007-01-11 |
US20070008774A1 (en) | 2007-01-11 |
JP2007019475A (ja) | 2007-01-25 |
KR100682948B1 (ko) | 2007-02-15 |
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