CN100573898C - 自对准并平坦化的下电极相变化存储器及其制造方法 - Google Patents
自对准并平坦化的下电极相变化存储器及其制造方法 Download PDFInfo
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- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Shaping switching materials
- H10N70/068—Shaping switching materials by processes specially adapted for achieving sub-lithographic dimensions, e.g. using spacers
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- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
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- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
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Abstract
本发明公开一种在相变化随机存取存储PCRAM器件中用以将下电极自对准的方法,其中上电极作为此下电极在自对准蚀刻时的掩模。此下电极包括有由化学机械研磨而平坦化的上表面。此上电极还包括有由化学机械研磨而平坦化的上表面。在后续工艺中形成通孔之前,如氮化钛等的下电极形成于衬底上。第一介质层形成于此下电极上,且第二介质层形成于此第一介质层上。通孔形成于延伸经过此第一及第二介质层的选定区域中。
Description
相关申请
本申请于2006年1月11日申请美国临时专利申请,该申请的申请号为No.60/757,933,发明名称为“SELF-ALIGN PLANERIZEDBOTTOM ELECTRODE PHASE CHANGE MEMORY ANDMANUFACTURING METHOD”.
联合研究合约的当事人
纽约国际商业机械公司、台湾旺宏国际股份有限公司及德国英飞凌技术公司(Infineon Technologies A.G.)为联合研究合约的当事人。
技术领域
本发明涉及高密度存储装置,其基于以相变化为基础的存储材料,包括以硫属化物为基础的材料以及其他材料,及制造这些装置的方法。
背景技术
以相变化为基础的存储材料被广泛地运用于读写光盘中。这些材料包括有至少两种固态相,包括如大致为非晶态的固态相,以及大致为结晶态的固态相。激光脉冲用于读写光盘中,以在二种相中切换,并读取此种材料在相变化之后的光学性质。
如硫属化物及类似材料的这些相变化存储材料,可提供施加其幅度适用于集成电路中的电流,而引起晶相变化。一般而言非晶态的特征为其电阻高于结晶态,此电阻值可轻易测量得到而用以作为指示。这种特性则引发使用可编程电阻材料以形成非易失性存储器电路等兴趣,此电路可用于随机存取读写。
从非晶态转变至结晶态一般为低电流步骤。从结晶态转变至非晶态(以下指称为重置(reset))一般为高电流步骤,其包括短暂的高电流密度脉冲以融化或破坏结晶结构,其后此相变化材料会快速冷却,抑制相变化的过程,使得至少部份相变化结构得以维持在非晶态。理想状态下,引起相变化材料从结晶态转变至非晶态的重置电流幅度应越低越好。欲降低重置所需的重置电流幅度,可提供减低在存储器中的相变化材料元件的尺寸、以及减少电极与此相变化材料的接触面积而实现,因此可针对此相变化材料元件施加较小的绝对电流值而达成较高的电流密度。
此领域发展的一种方法致力于在集成电路结构上形成微小孔洞,并使用微量可编程的电阻材料填充这些微小孔洞。致力于这些微小孔洞的专利包括:于1997年11月11日公布的美国专利第5,687,112号”Multibit Single Cell Memory Element Having Tapered Contact”、发明人为Ovshinky;于1998年8月4日公布的美国专利第5,789,277号”Method of Making Chalogenide[sic]Memory Device”、发明人为Zahorik等;于2000年11月21日公布的美国专利第6,150,253号”Controllable Ovonic Phase-Change Semiconductor Memory Device andMethods of Fabricating the Same”、发明人为Doan等。
在以非常小的尺寸制造这些装置、以及欲满足大规模生产存储装置时所需求的严格工艺参数时,则会遭遇到问题。较佳地提供一种存储单元结构其包括有小尺寸以及低重置电流,以及用以制造这些结构的方法,其可满足大规模生产存储装置时的严格工艺规格。在先前的解决方式中,在氮化钛(TiN)沉积于侧壁处制造存储装置,在上电极及下电极之间可能造成短路的发生。因此还提供一种制造工艺以及一种结构,其可在同一集成电路上兼容地制造周边电路、同时克服在上电极及下电极间可能发生的短路现象。
发明内容
本发明描述了一种方法,其用以排列相变随机存取存储器PCRAM装置中的下电极,而在此处上电极元件则作为下电极元件自对准蚀刻时的掩模。下电极元件的侧边与上电极元件的侧边排列成直线。此下电极包括有经由化学机械研磨(CMP)而平坦化的上表面。此上电极还包括有经由化学机械研磨而平坦化的上表面。下电极层如氮化钛等在后续工艺中形成通孔之前形成于衬底上。第一介质层形成于此下电极上,且第二介质层形成于此第一介质层上,通孔形成于延伸经过此第一及第二介质层的选定区域。湿蚀刻程序则使得在第二介质层中的第一区段的长度,大于在第一介质层中的第一区段的长度。当低导热性物质沉积于通孔中并施加以各向异性蚀刻时,则在此通孔中的空洞则会造成小孔。上与下电极通过相变化材料而被电连接,此相变化材料被沉积至小孔及通孔中、而延伸于下电极的上表面以及上电极的下表面之间。
广泛地来说,存储装置包括衬底主体,其包括有多个接触栓塞以及上表面。第一电极构件置于此衬底本体的上表面,其中此第一电极的下表面接触至这些接触栓塞。此第一电极包括有大致平坦的上表面。在此第一电极构件上的低传导性填充材料,界定了小孔,其延伸至此第一电极的电极表面。位于此小孔中的可编程电阻存储材料电连接至此第一电极的电极表面。第二电极元件包括有上表面以及与此可编程电阻材料接触的电极表面,此处该第一与第二电极元件各自有其侧边,且此第二电极元件的侧边与第一电极元件的侧边对准。
本发明的优点在于提供了一种相变化存储器,其平坦化的下电极可自对准。
以下详细说明本发明的结构与方法。本发明内容说明书部分并非在于限定本发明。本发明由权利要求书所限定。凡本发明的实施例、特征、观点及优点等将可通过下列说明书、权利要求书及附图获得充分了解。
附图说明
图1为说明包括本发明的相变化存储单元的存储阵列的示意图。
图2为工艺图,其说明在实施例中,在前端处理用以形成标准CMOS器件的衬底后的一种结构,其对应图1中所示的存储阵列中的字线、源极线、以及存取晶体管。
图3为工艺图,其说明根据本发明而进行氮化钛沉积与化学机械研磨程序的第一步骤。
图4A为工艺图,其说明根据本发明而进行氧化物及氮化硅沉积程序的第二步骤;
图4B为工艺图,其说明第二步骤的替代实施例,其根据本发明而进行存储材料层、氧化物层、以及氮化硅层的沉积程序。
图5为工艺图,其说明根据本发明而进行开启多个通孔的过程的第三步骤。
图6为工艺图,其说明根据本发明而进行湿氧化硅蚀刻程序的第四步骤。
图7为工艺图,其说明根据本发明而进行低导热性物质的沉积程序的第五步骤。
图8为工艺图,其说明依据本发明而进行热与电绝缘填充层的蚀刻程序的第六步骤。
图9为工艺图,其说明根据本发明而进行相变化材料的沉积程序的第七步骤。
图10为工艺图,其说明根据本发明而进行氮化钛/钨沉积以及化学机械研磨的第八步骤。
图11A为工艺图,其说明根据本发明而进行存储单元隔离蚀刻反应的第九步骤;
图11B为工艺图,其说明第九步骤的替代实施例,其依据本发明而进行存储单元隔离蚀刻反应。
图12为工艺图,其说明根据本发明而进行氧化物填入程序的第十步骤。
图13为工艺图,其说明根据本发明而进行氧化物化学机械研磨程序的第十一步骤。
图14为工艺图,其说明根据本发明而形成金属位线的第十二步骤。
主要元件符号说明
100 存储阵列
110 源极线
112 字线
114 字线
120,122,1410 位线
139 块
150,152,154,156存取晶体管
160,164,170 电极构件
162,172 存储单元
200,1300,1400 结构
201,202 隔离沟
203,204,205 掺杂区域
206 源极线
207 多晶硅
208 覆盖金属硅化物
209 介质层
210,212,213,214栓塞
211 多晶硅线
217,218 字线多晶硅
300,400,450,500,600,700,800,900,
1000,1100,1150,1200,1300,1400 工艺图
310 导电电极层
410 第一介质层
411 第一区段
412 第二区段
420 第二介质层
421 第一区段
422 第二区段
460 存储材料层
510,520,530,540通孔
610,612 侧壁
710 填充物
712,714,716,718 空洞
810,812,814,816 小孔
910 相变化材料
912,914,916,918 相变化材料区段
1010,1020,1030,1040 氮化钛层
1012,1022,1032,1042 钨层
1110,1112,1114,1116,1118区域
1172 活性区域
1310 平坦表面
1410 金属位线
具体实施方式
本发明的实施例参照图1-14说明。
请参照图1,其显示说明包括相变化存储单元的存储阵列100的结构。共同源极线110、字线112、以及字线114以大致在Y方向平行的方式排列。位线120及122以大致在X方向平行的方式排列。在块139中的Y解码器以及字线驱动器连接至字线112及114。在块140中的X解码器及感测放大器连接至位线120及122。此共同源极线110连接至存取晶体管150,152,154及156的源极。存取晶体管150的栅极连接至字线112。存取晶体管152的栅极连接至字线114。存取晶体管154的栅极连接至字线112。存取晶体管156的栅极连接至字线114。存取晶体管150的漏极连接至电极构件160以连接存储单元162,其进而与电极构件164连接的。相似的,存取晶体管152的漏极连接至电极构件170以连接电极构件164,其进而连接存储单元172。电极构件164与164连接至位线120。为了图示方便,电极构件164示于位线120上的不同位置。可以理解的是,分离的电极构件可在其他实施例中被用作为分离的存储元件。存取存储器154及156也于位线122上连接至对应的存储单元。图中可见,共同源极线110被两列存储单元共同使用,其中一列在图中为Y轴方向。相似地,电极元构164被二存储单元在阵列的行共用,且此行在图中为X轴方向。
如图2的实施例示出用以形成标准CMOS器件的前端加工的衬底主体后的结构200,其对应如图1所示的字线、源极线、以及存储阵列100中的存取晶体管。在此半导体衬底上,源极线206位于掺杂区域203之上,此处此掺杂区域对应图2左侧的第一存取晶体管及图2右侧的第二存取晶体管的源极。在本实施例中,源极线206延伸至此结构200的上表面。在其他实施例中,此源极线并非一路延伸至此上表面。掺杂区域204对应此第一存取晶体管的漏极。包括有多晶硅207,以及覆盖金属硅化物208的字线用作此第一存取晶体管的栅极。介质层209位于此多晶硅207以及覆盖金属硅化物208上。栓塞210接触至此掺杂区域204,并提供导电路径至结构200的表面,而以后述方式连接至存储单元电极。此第二存取晶体管的漏极由掺杂区域205所提供。包括有多晶硅线211、以及覆盖金属硅化物的字线作为第二存取晶体管的栅极。栓塞212接触至掺杂区域205并提供导电路径至结构200的上表面,而以后述方式连接至存储单元电极。隔离沟槽201及202将此连接至栓塞210与212的双晶体管结构、与相邻的双晶体管结构分隔开来。在图的左侧则显示有字线多晶硅217与栓塞214。在图的右侧则显示字线多晶硅218与栓塞213。
在图3中显示工艺图300,其示出进行氮化钛沉积以及化学机械研磨(CMP)程序的第一步骤。相对薄的导电电极层310由导电电极材料如氮化钛等所构成,其形成于此结构200的表面上。导电电极层310的合适厚度可举例如,在CMP研磨后介于约20至约60nm。此氮化钛层310填满了在栓塞表面的不平整部分,并为后续加工工艺提供平坦的表面。
图4A示出工艺图400,其显示本实施例制造程序的下一步骤。第一介质层410如二氧化硅等,沉积于此导电层310上。第二介质层420包括氮化硅或其他合适材料形成于此第一介质层410上。在依实施例中,此第二介质层包括薄氮化硅层。在如图4B的工艺图450中所示的替代实施例中,存储材料层460沉积于导电层310之上、接着沉积第一介质层410以及第二介质层420。
请参见图5的工艺图500,其显示此工艺中的下一步骤,其中通孔510选择性地蚀刻经此第二介质层420与第一介质层410、而蚀刻至此导电电极材料310,从第二介质层420中制造出第一区段421,其位于此第一介质层410的第一区段411上。
如图6所示,其显示有工艺图600,其示出针对第一介质层410中各区段实行湿氧化硅蚀刻的第四步骤。此湿氧化硅蚀刻在通孔开口510中进行,而影响特定通孔中的两侧壁。在此通孔开口510中,第一介质层410的第一区段411的侧壁610被蚀刻,因此第二介质层420的第一区段421凸出于第一介质层410的第一区段411的侧壁610,此第二介质层420的第一区段421凸悬于第一介质层410的第一区段411之上。此第一介质层410的第二区段412的侧壁612被蚀刻,使得此第二介质层420的第二区段422凸出于第一介质层410的第二区段412的侧壁612。第二介质层420的第二区段422的左侧缘凸悬于第一介质层410的第二区段412上。
图7示出工艺图700,其示出进行低导热性材料的沉积程序的第五步骤。兼具有低导热性与低导电性特征的填充物710,被以化学气相沉积(CVD)而均匀一致地沉积至带有空洞712,714,716及718的通孔510,520,530,及540中、以及第二介质层420上。在此实施例中,填充物710所具备的一项性质,为其导热性低于其周围第一介质层410的介质层材料的导热性。填充物710所具备的另一性质为,其导电性低于如图9所述的相变化材料910的导电性。低导电性与低导热性材料的适当范例如下所述。此填充物710可包括二氧化硅、氮氧化硅、氮化硅、氧化铝、其他低介电系数的介质、或ONO或SONO的多层结构。“或者,此填充物可包括电绝缘物,包括一个以上选自下列组的元素:硅、氟、氮、氧、及碳。在其介质层410包括二氧化硅的装置中,此填充物的导热性低于二氧化硅的导热性约0.014J/cm*K*sec。在其他较佳实施例中,此热绝缘层包括有导热性低于相变化材料在非晶态时的导热性,或低于含有GST的相变化材料约0.003J/cm*K*sec。热绝缘材料的代表材料,包括由选自下群组的元素所组成的复合物:硅、碳、氧、氟、及氢。可用于热绝缘填充层的热绝缘材料范例包括:二氧化硅、SiCOH、聚酰亚胺、聚酰胺、以及氟碳聚合物。其他可用于热绝缘填充层的材料可举例包括:含氟二氧化硅、硅氧烷(silsesquioxane)、聚亚芳香醚(polyarylene ether)、聚对二甲苯(parylene)、含氟聚合物、含氟非晶碳、类钻石碳、多孔性二氧化硅、中孔性二氧化硅、多孔性硅氧烷(silsesquioxane)、聚亚芳香醚(polyarylene ether)、聚对二甲苯(parylene)、多孔性硅氧烷、多孔性聚亚醯胺、以及多孔性聚亚芳香醚。在管路中的单层或复合层也可提供热绝缘与电绝缘效果。
请参照图8,其示出工艺图800,其说明进行填充物蚀刻而分别从空洞712、714、716及718中产生小孔810、812、814及816的第六步骤。在本实施例中,此填充物蚀刻步骤延伸进入填充物710及空洞712、714、716及718,使得小孔810、812、814及816得以产生,其中每一此小孔的底部连通至下电极层310。在一实施例中,此小孔的宽度与长度均相当小。举例而言,小孔的宽度可选定为界于30至80nm之间。在一实施例中,此小孔的宽度被选定为60nm。在本发明中,也可选择其他宽度与长度尺寸。填充物蚀刻步骤延伸至此填充物710的实质部分,直到形成小孔810、812、814及816为止,如图8中所示。
如图9中所示,其为工艺图900的剖面图,示出沉积相变化材料的薄层910的第七步骤。此相变化材料薄层910形成于第二介质层420的第一区段421、第二区段422、第三区段423、第四区段424、及第五区段425、通孔510、512、514及516、以及小孔810、812、814及816之上。此相变化材料填满了这些小孔,并接触至下电极层310,并沿着通孔的侧壁延伸。
相变化材料能在此单元活性信道区域内依其位置顺序在材料为一般非晶状态的第一结构状态与为一般结晶固体状态的第二结构状态之间切换。这些材料至少为双稳态的。术语“非晶“用以指称一相对较无次序的结构,其比单晶更无次序性,而带有可检测的特征,如比结晶态更高的电阻值。术语”结晶态“用以指称一相对较有次序的结构,其比非晶态更有次序,因此包括有可检测的特征例如比非晶态更低的电阻值。典型地,相变化材料可电切换至完全结晶态与完全非晶态之间所有可检测的不同状态。其它受到非晶态与结晶态的改变而影响的材料特中包括,原子次序、自由电子密度、以及活化能。此材料可切换成为不同的固态、或可切换成为由两种以上固态所形成的混合物,提供从非晶态至结晶态之间的灰阶部分。此材料中的电性质也可能随之改变。
相变化合金可通过施加电脉冲而从一种相态切换至另一相态。先前观察指出,较短、较大幅度的脉冲倾向于将相变化材料的相态改变成大体为非晶态。较长、较低幅度的脉冲倾向于将相变化材料的相态改变成大体为结晶态。在较短、较大幅度脉冲中的能量够大,因此足以破坏结晶结构的键结,同时够短因此可以防止原子再次排列成结晶态。在没有不适当实验的情形下,可决定特别适用于特定相变化合金的适当脉冲量变曲线。在本文的后续部分,此相变化材料以GST代称,同时应该了解,也可使用其他类型的相变化材料。在本文中所描述的一种适用于PCRAM中的材料,为Ge2Sb2Te5。
现在请参照图10,其示出工艺图1000的剖面图,其说明进行氮化钛与钨沉积,以及化学机械研磨的第八步骤。这些氮化钛层1010、1020、1030及1040分别沉积进入各通孔,并置于相变化材料区段912、914、916及918之上。此钨层1012、1022、1032及1042连续地置于所对应的氮化钛层1010、1020、1030及1040之上。此相变化材料912电连接于下电极层310与上电极层之间,例如氮化钛层1010与钨层1012,或在氮化钛层1010与钨层1012中二选一。更详细地说,相变化材料912于通孔中的第一部份电连接至下电极层310,而相变化材料912在通孔510中的第二部分电连接至上电极层。
图11A为工艺图1100的剖面图,其说明在区域1110、1112、1114、1116及1118中进行存储单元隔离蚀刻程序的第九步骤。隔离蚀刻为工艺的部分,其用以定义硫属化物存储单元的横截面区域。每一硫属化物存储单元的宽度提供在硫属化物存储单元的每一侧进行隔离蚀刻而定义。在存储单元隔离蚀刻的实施例中,此代表上电极的钨层1012,用作下电极310以氟氩化学反应进行自对准蚀刻的掩模。此蚀刻化学反应将在蚀刻下电极310的氮化钛时,转换为氯氩化学反应。图11B为说明第九步骤的进行存储单元隔离蚀刻的替代实施例的工艺图。相变化材料的活性区域1172,经由作为活性区域1172与上电极元件1190a、1190b之间的隔离材料的相变化材料1174,而电连接至上电极构件,上电极构件在本实施例中以氮化钛1190a与钨层1190b作为代表。相变化材料的活性区域1172,提供作为活性区域1172与下电极构件1160之间的隔离材料的相变化材料1170,而电连接至下电极构件1160。此上电极构件1190a、1190b作为下电极构件1160在进行自对准蚀刻时的掩模。在另一实施例中,此上电极构件指至钨层1190b,而氮化钛层1190a则作为中间材料。此蚀刻程序可为填充物与存储材料层的单步骤各向异性蚀刻,或为两步骤程序,其先以第一蚀刻化学物蚀刻此填充材料,再以第二蚀刻化学物蚀刻此存储材料。
图12为工艺图1200的剖而图,其说明进行硅氧化物填入程序的第十步骤。在隔离蚀刻程序后,氧化硅1210用以填入此结构的沟槽,而在沟槽中形成绝缘层,并将相变化材料的各活性区域彼此隔开。
如图13中所示,其为工艺图1300的剖面图,示出了第十一步骤中所进行的氧化硅的化学机械研磨步骤。此氧化硅化学机械研磨步骤用以磨平结构1300,而在结构1300上留下大致上平坦的表面1310。图14为工艺图1400的剖面图,其说明在第十二步骤中形成金属位线的步骤。在氧化硅化学机械研磨之后,金属位线1410形成于此结构1400的上表面。
存储材料的实施例包括了相变化为基础的存储材料,包括以硫属化物为基础与的材料与其他材料做为电阻元件。硫属化物包括下列四元素中的任一种:氧(O)、硫(S)、硒(Se)、以及碲(Te),形成元素周期表上第VI族的部分。硫属化物包括将一硫属元素与一更为正电性的元素或自由基结合而得。硫属化合物合金包括将硫属化合物与其他物质如过渡金属等结合。硫属化合物合金通常包括一个以上选自元素周期表第六栏的元素,例如锗(Ge)以及锡(Sn)。通常,硫属化合物合金包括下列元素中一个以上的复合物:锑(Sb)、镓(Ga)、铟(In)、以及银(Ag)。许多以相变化为基础的存储材料已在技术文件中进行了描述,包括下列合金:镓/锑、铟/锑、铟/硒、锑/碲、锗/碲、锗/锑/碲、铟/锑/碲、镓/硒/碲、锡/锑/碲、铟/锑/锗、银/铟/锑/碲、锗/锡/锑/碲、锗/锑/硒/碲、以及碲/锗/锑/硫。在锗/锑/碲合金家族中,可以尝试大范围的合金成分。此成分可以下列特征式表示:TeaGebSb100-(a+b)。一位研究员描述了最有用的合金为,在沉积材料中所包括的平均碲浓度远低于70%,典型地低于60%,并在一般类型的合金中的碲含量范围从最低23%至最高58%,且最佳为介于48%至58%得到碲含量。锗的浓度高于约5%,且其在材料中的平均范围从最低8%至最高30%,一般低于50%。最佳地,锗的浓度范围介于8%至40%。在此成分中所剩下的主要成分则为锑。上述百分比为原子百分比,其为所有组成元素总和为100%。(Ovshinky‘112专利,栏10~11)由另一研究者所评估的特殊合金包括Ge2Sb2Te5、GeSb2Te4、以及GeSb4Te7。(Noboru Yamada,”Potential of Ge-Sb-Te Phase-changeOptical Disks for High-Data-Rate Recording”,SPIE v.3109,pp.28-37(1997))更一般地,过渡金属如铬(Cr)、铁(Fe)、镍(Ni)、铌(Nb)、钯(Pd)、铂(Pt)、以及上述的混合物或合金,可与锗/锑/碲结合以形成相变化合金,其包括有可编程的电阻性质。可使用的存储材料的特殊范例,如Ovshinsky‘112专利中栏11-13所述,其范例在此列入参考。
可用于本发明其它实施例中的其它可编程的存储材料包括,掺杂N2的GST、GexSby、掺杂银的SbxTey、或其它以不同结晶态变化来决定电阻的物质;PrxCayMnO3、PrSrMnO、ZrOx、AlOx、TiOx、NiOx、ZnOx、以铬掺杂的SrZrO3、以铌掺杂的SrZrO3、或其它利用电脉冲以改变电阻状态的材料;TCNQ、PCBM、TCNQ-PCBM、Cu-TCNQ、Ag-TCNQ、C60-TCNQ、以其它物质掺杂的TCNQ、或任何其它聚合物材料其包括有以电脉冲而控制的双稳态或多稳态电阻态。
关于相变化随机存取存储装置的制造、元件材料、使用与操作,请参见美国专利申请No.11/155,067号”Thin Film Fuse Phase ChangeRAM and Manufacturing Method”,申请日为2005年6月17日,专利权人为本申请的专利权人,并在本申请中列为参考。
虽然本发明已参照较佳实施例加以描述,应该所了解的是,本发明并不受限于其详细描述的内容。替换方式及修改方式已在先前描述中建议,并且其他替换方式及修改方式将为本领域的技术人员可想到的。特别是,根据本发明的结构与方法,所有具有实质上相同于本发明的构件结合而实现与本发明实质上相同结果的,皆不脱离本发明的精神范畴。因此,所有这些替换方式及修改方式意欲落在本发明所附的权利要求书及其等价物所界定的范畴中。
Claims (24)
1.一种存储元件,其包括:
衬底主体,其包括有多个接触栓塞,该衬底主体包括有上表面;
第一电极构件,其位于该衬底主体的上表面,并包括有下表面接触至该些接触栓塞之一,该第一电极包括有大致平坦的上表面;
低传导性填充材料,其位于该第一电极构件上,该低传导性填充材料界定延伸至该第一电极的上表面的孔洞;
可编程电阻存储材料,其位于该孔洞中,并与该第一电极的该上表面连接;以及
第二电极构件,其包括有上表面以及与该可编程电阻材料接触的电极表面;
其中该第一及第二电极构件各自包括有侧边,且其中该第二电极的侧边与该第一电极的侧边对准。
2.如权利要求1所述的元件,其中该第一电极构件包括选自下列元素组的元素:钛、钨、钼、铝、钽、铜、铂、铱、镧、镍、以及钌、以及由上述元素所构成的合金。
3.如权利要求1所述的元件,其中该第一电极构件的厚度介于20nm至60nm之间。
4.如权利要求1所述的元件,其中该可编程电阻存储材料包括至少二种固态相,其包括大致为非晶态的固态相以及大致为结晶态的固态相。
5. 如权利要求1所述的元件,其中该可编程电阻存储材料包括合金,其含有由下列组中二种以上材料所构成的复合物:锗、锑、碲、铟、钛、镓、铋、锡、铜、钯、铅、银、硫、以及金。
6.如权利要求1所述的元件,还包括第一可编程电阻存储材料元素,其置于该第一电极构件的该电极表面与该低传导性填充材料之间,该第一可编程电阻存储材料与该可编程电阻存储材料在该孔洞中接触。
7.如权利要求1所述的元件,还包括第二可编程电阻存储材料元素,其置于该第二电极构件的该电极表面与该低传导性填充材料之间,该第二可编程电阻存储材料与该第一可编程电阻存储材料在该孔洞中接触。
8.如权利要求1所述的元件,其中该低传导性填充材料包括低导电性材料,其导电性低于该可编程电阻存储材料的导电性。
9.如权利要求1所述的元件,其中该可编程电阻材料包括相变化材料,其包括有非晶态,且该低传导性填充材料包括有热阻值,其高于该相变化材料在该非晶态时的热阻值。
10.如权利要求1所述的元件,其中该第二电极构件包括钨或氮化钛。
11.一种用以制造存储元件的方法,其包括:
提供衬底主体,其包括有接触栓塞,该衬底主体包括有上表面;
在形成通孔之前,沉积第一电极层于该衬底主体上,该第一电极层包括有上表面;
形成第一及第二介质层于该第一电极层的大致上平坦的表面上,该第二介质层置于该第一介质层上;
在特定部分形成通孔,其中该通孔穿过第一及第二介质层,以于该第一及第二介质层中制造第一及第二区段,该第二介质层的该第一区段凸悬于该第一介质层的该第一区段上,该第二介质层的该第二区段凸悬于该第一介质层的该第二区段上;在该通孔中形成孔洞从而露出该第一电极层,其提供在该通孔中形成的侧壁结构而实现,该侧壁结构包括低传导性材料;
沉积可编程电阻存储材料在该孔洞中并接触该第一电极层;
在该通孔中形成第二电极层于该可编程电阻存储材料上,并图形化该第二电极层,以界定与该通孔对准的上电极构件;以及
利用该上电极构件作为掩模,蚀刻该第一及第二介质层、以及该第一电极层,以界定与该上电极构件对准的下电极构件。
12.如权利要求11所述的方法,在该第一电极层的形成步骤后,还包括研磨该第一电极层的该上表面,以在该第一电极层上制造大致上平坦的表面。
13.如权利要求12所述的方法,在该研磨步骤之后,还包括沉积存储材料层于该第一电极层大致上平坦的该表面之上,该存储材料层接触该可编程电阻存储材料,并作为该可编程电阻存储材料与该下电极构件之间的隔绝材料。
14.如权利要求13所述的方法,其中该低传导性材料包括低导电性材料,其导电性低于该可编程电阻存储材料的导电性。
15.如权利要求11所述的方法,其中沉积该可编程电阻存储材料的步骤,包括沉积该可编程电阻存储材料至横越该第一与第二介质层的表面,并沉积至被该低热传导性材料环绕的该孔洞中。
16.如权利要求15所述的方法,其中该低传导性材料包括低导电性材料,其导电性低于该可编程电阻存储材料的导电性。
17.如权利要求11所述的方法,其中该可编程电阻存储材料包括相变化材料,其包括有非晶态,且该低传导性材料的热阻值大于该相变化材料于该非晶态时的热阻值。
18.如权利要求11所述的方法,其中该低传导性材料,包括低导热性材料,其导热性低于由一个以上介质层所提供环境的导热性。
19.如权利要求11所述的方法,其中该第一电极层包括选自下列元素组的元素:钛、钨、钼、铝、钽、铜、铂、铱、镧、镍、以及钌、以及由上述元素所构成的合金。
20.如权利要求11所述的方法,其中该第二电极层包括钨或氮化钛。
21.如权利要求11所述的方法,其中该第一电极层的厚度介于20nm至60nm之间。
22.如权利要求11所述的方法,其中还包括针对该第一及第二介质层于该通孔的两侧进行湿蚀刻。
23.如权利要求11所述的方法,其中该可编程电阻存储材料包括至少二种固态相,其包括大致非晶态的固态相以及大致结晶态的固态相。
24.如权利要求11所述的方法,其中该可编程电阻存储材料包括合金,其含有由下列组中二种以上材料所构成的复合物:锗、锑、碲、铟、钛、镓、铋、锡、铜、钯、铅、银、硫、以及金。
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KR100657897B1 (ko) * | 2004-08-21 | 2006-12-14 | 삼성전자주식회사 | 전압 제어층을 포함하는 메모리 소자 |
KR100668333B1 (ko) * | 2005-02-25 | 2007-01-12 | 삼성전자주식회사 | Pram 소자 및 그 제조방법 |
US7351648B2 (en) | 2006-01-19 | 2008-04-01 | International Business Machines Corporation | Methods for forming uniform lithographic features |
KR100791477B1 (ko) * | 2006-08-08 | 2008-01-03 | 삼성전자주식회사 | 상변화 메모리 유닛, 이의 제조 방법, 이를 포함하는상변화 메모리 장치 및 그 제조 방법 |
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2006
- 2006-02-09 US US11/351,296 patent/US7825396B2/en active Active
- 2006-09-22 TW TW095135243A patent/TWI311797B/zh active
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TWI311797B (en) | 2009-07-01 |
US8143089B2 (en) | 2012-03-27 |
US20110017970A1 (en) | 2011-01-27 |
US20070158645A1 (en) | 2007-07-12 |
CN101000920A (zh) | 2007-07-18 |
TW200727406A (en) | 2007-07-16 |
US7825396B2 (en) | 2010-11-02 |
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