CN100573952C - 使用单一接触结构的桥路电阻随机存取存储元件及方法 - Google Patents
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Abstract
本发明公开了一种桥路结构中的电阻随机存取存储器,其包括接触结构,其中第一与第二电极位于接触结构中。第一电极具有周边延伸的形状(例如环形),其围绕接触结构的内壁。第二电极位于该周边延伸形状内,并以绝缘材料而与第一电极分隔开。电阻存储桥路与第一和第二电极的边缘表面接触。接触结构中的第一电极连接至晶体管,且接触结构中的第二电极连接至位线。位线通过自对准工艺而连接到第二电极。
Description
技术领域
本发明涉及由以相变为基础的存储材料所构成的的高密度存储元件,该存储材料包括以硫族化物为基础的材料与其它材料。本发明也涉及用以制造这种元件的方法。
背景技术
以相变为基础的存储材料被广泛地运用于读写光盘中。这些材料包括至少两种固态相,例如包括大体上为非晶态的固态相,以及大体上为晶态的固态相。激光脉冲用于读写光盘,以在两种相中切换,并读取此种材料在相变之后的光学性质。
如硫族化物及类似材料的相变存储材料,也可以通过施加幅度适用于集成电路的电流,而致使晶相变化。一般而言,非晶态的特征是其电阻高于晶态,该电阻值可轻易测量得到而用以作为指示。这种特性则引发对使用可编程电阻材料以形成非易失性存储器电路的关注,该电路可用于随机存取读写。
从非晶态转变至晶态一般为低电流操作。从晶态转变至非晶态(以下称为重置(reset))一般为高电流操作,其包括短暂的高电流密度脉冲以融化或破坏结晶结构,其后该相变材料会快速冷却,抑制相变的过程,使得至少部份相变结构得以维持在非晶态。理想状态下,致使相变材料从晶态转变至非晶态的重置电流幅度应越低越好。欲降低重置所需的重置电流幅度,可通过减小在存储器中的相变材料元件的尺寸,以及缩小电极与该相变材料的接触面积而达成,因此可针对该相变材料元件施加较小的绝对电流值而实现较高的电流密度。
该领域发展的一种方法是致力于在集成电路结构上形成微孔洞,并使用微量可编程的电阻材料填充这些微孔洞。致力于所述微孔洞的专利包括:1997年11月11日授权的美国专利No.5,687,112,其名称为“Multibit Single Cell Memory Element Haying TaperedContact”,发明人为Ovshinky;1998年8月4日授权的美国专利No.5,789,277,其名称为“Method of Making Chalogenide[sic]Memory Device”,发明人为Zahorik等;2000年11月21日授权的美国专利No.6,150,253,其名称为“Controllable OvonicPhase-Change Semiconductor Memory Device and Methods ofFabricating the Same”,发明人为Doan等。
此外,在以非常小的尺度制造这些装置,以及欲满足生产大规模存储装置时所需的严格工艺变量时,则会遭遇到问题。在电阻存储元件中的接点会占据相当可观的空间。因此,希望提供可以减少接点的尺寸的存储单元结构,进而缩小存储单元的整体尺寸。
发明内容
根据本发明的第一方面,提供了一种在桥路结构中的存储元件,该桥路结构包括接触结构,该存储元件包括:第一电极,位于该接触结构内,具有周边延伸的形状,且环绕该接触结构的内壁;第二电极,位于该接触结构内且位于所述第一电极的周边延伸的形状内;绝缘材料,其隔离该第一与第二电极;以及存储材料,沉积在该桥路结构中,该桥路结构与该第一电极的上表面与该第二电极的上表面接触。
在实施例中,电阻存储桥路与第一和第二电极的边缘表面接触。接触结构内的第一电极连接至晶体管,而在接触结构内的第二电极则连接至位线。使用自对准工艺以将位线连接至第二电极。
在第一实施例中,金属层间介质层隔离物沉积在电阻存储材料上,以将电阻存储材料隔绝于后续的衬底介质突破步骤,在该步骤中位线形成在该隔离物之内和之上。在第二实施例中,通孔形成在第二电极的上表面之上和之内,而位线则形成在通孔之内和之上。在第三实施例中,硬掩模形成在电阻存储材料上,且对电极进行回蚀刻,在此则不需要形成隔离物或通孔。
广泛地说,存储元件包括有接触结构,该接触结构则具有侧壁与内表面。第一电极具有周边延伸形状且沿着接触结构的内表面沉积,而第一电极也具有内表面。绝缘材料形成在钨材料的上表面上,并环绕第一电极的内表面。该绝缘材料具有支持范围,其中第二电极沉积在该绝缘材料的支持范围之内,使得绝缘材料可用以分隔第一与第二电极。
根据本发明的第二方面,提供了一种用以制造存储元件的方法,包括:提供晶体管本体,其具有接触结构与层间介质,该接触结构具有内壁;形成第一电极,该第一电极具有沿着该接触结构的内壁延伸的区域;蚀刻该接触结构的顶部以将第一介质层沉积在该区域内;将第二电极沉积在该第一介质层中;以及将存储材料沉积在一桥路结构中,该桥路结构与该第一电极和该第二电极的上表面接触。
本发明的优点在于,本发明通过将单一接触结构分为两部分用以分别连接至晶体管与位线,而缩小了存储单元的整体尺寸,因此摒除在传统设计中所需要的第二接触结构。
以下详细说明本发明的结构与方法。本发明内容的目的并非在于定义本发明。本发明是由权利要求所定义。本发明的实施例、特征、目的及优点等将可通过下面的描述、所附权利要求及附图获得充分了解。
附图说明
图1示出根据本发明的双稳态电阻随机存储器阵列;
图2是根据本发明的实施例的集成电路的简化方框图;
图3示出根据本发明的第一实施例的用以制造双稳态电阻随机存取存储器的第一步,其形成晶体管结构;
图4示出根据本发明第一实施例的用以制造双稳态电阻随机存取存储器的第二步,其蚀刻钨凹陷区域,沉积衬底介质层与第二电极;
图5示出根据本发明的第一实施例的用以制造双稳态电阻随机存取存储器的第三步,其抛光第二电极,沉积电阻存储材料,并图案化;
图6示出根据本发明的第一实施例的用以制造双稳态电阻随机存取存储器的第四步,其沉积第二衬底介质层,沉积金属层间介质层,以及图案化通孔;
图7示出根据本发明的第一实施例的用以制造双稳态电阻随机存取存储器的第五步,其形成金属层间介质隔离物、第二介质突破,以及位线;
图8是根据本发明的第二实施例的桥路电阻随机存取存储器的剖面图,其沉积金属层间介质层,并图案化通孔;
图9示出根据本发明的第二实施例的制造双稳态桥路电阻随机存取存储器的下一步骤,包括沉积位线;
图10是根据本发明的第三实施例的制造双稳态桥路电阻随机存取存储器的下一步骤的剖面图,包括将硬掩模沉积在电阻随机存储材料桥路上;
图11是根据本发明的第三实施例中的桥路电阻随机存取存储器的剖面图,包括回蚀刻第一与第二电极,以及沉积衬底介质层;
图12是根据本发明第三实施例的制造该桥路电阻随机存取存储器的下一步骤的剖面图,包括蚀刻介质隔离物,以及形成位线;
图13是根据本发明的实例的桥路电阻随机存取存储器的剖面图,其具有示例性电流路径;
图14A是根据本发明的以管状电极为基础的存储单元的实施例的剖面图,该管状电极耦合到可编程电阻材料;
图14B是根据本发明的第一与第二电极为管状构件的实施例的正交剖面图;
图15是根据本发明的用以制造桥路电阻随机存取存储器的示例性参数布局图。
具体实施方式
本发明结构实施例与方法的说明参考图1-15。可以理解的是,这些实施例并非用以限定本发明,且本发明可利用其它特征、元件、方法与实施例进行实施。在不同实施例中的相似元件,以相似的数字指定。
参考图1,其示出存储阵列100的示意图,其可依照本发明而实施。在图1中,共同源极线128、字线123、以及字线124大致平行于Y轴而排列。位线141与142大致平行于X轴而排列。因此,在方框145中的Y轴解码器与字线驱动器,耦合到字线123、124。在方框146中的X轴解码器与一组感测放大器耦合到位线141与142。共同源极线128耦合到存取晶体管150、151、152、153的源极端。存取晶体管150的栅极耦合到字线123。存取晶体管151的栅极耦合到字线124。存取晶体管152的栅极耦合到字线123。存取晶体管153的栅极耦合到字线124。存取晶体管150的漏极耦合到侧壁引脚存储单元135的底电极构件132,该存储单元具有顶电极构件134。顶电极构件134耦合到位线141。相似地,存取晶体管151的漏极耦合到侧壁引脚存储单元的底电极构件133,该存储单元具有顶电极构件137。该顶电极构件耦合到位线141。存取晶体管152与153也耦合到相对应的侧壁引脚存储单元的位线142。从图中可见,共同源极线128被两列存储单元所共用,其中一列如图所示以y轴方向排列。在其它实施例中,这些存取晶体管可被二极管,或其它结构所取代,这些结构可控制电流以在存储阵列中选定用以读取与写入数据。
如图2所示,其根据本发明的实施例,示出集成电路200的简化方框图。该集成电路275在半导体基板上包括存储阵列,其利用侧壁有源引脚双稳态随机存取存储单元来实施。列解码器261耦合到多个字线262,字线沿着存储阵列260中的各列设置。行解码器263耦合到多个位线264,位线沿着存储阵列260中的行设置,以从侧壁引脚存储单元中读取并编程数据。阵列260中的地址经由总线265提供给行解码器263与列解码器261。在方框266中的感测放大器与数据输入结构,经由数据总线267耦合到行解码器263。数据从集成电路275的输入/输出端口、或集成电路内部与外部的其它数据源,经由数据输入线271将数据传输至方框266中的数据输入结构。在所示的实施例中,在该集成电路上包括其它电路274,例如通用处理器或专用应用电路、或可提供片上***功能的模块的组合,其由薄膜保险丝双稳态电阻随机存取存储单元阵列支持。数据从方框266中的感测放大器,经由数据输出线272,传输至集成电路275的输入/输出端口或其它位于集成电路275内部或外部的数据终点。
在本实施例中,使用偏压安排状态器269的控制器,控制所施加的偏压安排供应电压268,例如读取、编程、擦除、擦除确认、与程序确认电压。该控制器可以利用在该领域中所公知的专用逻辑电路来实施。在替代实施例中,该控制器包括通用处理器,该通用处理器可安排在同一集成电路上,而该集成电路执行电脑程序以控制该元件的操作。在另一实施例中,可使用专用逻辑电路与通用处理器的结合,以实施该控制器。
图3是根据本发明的第一实施例的制造双稳态电阻随机存取存储器300的第一步骤的剖面图,其包括形成晶体管结构。该双稳态电阻随机存取存储器300形成在半导体基板310上。存取晶体管由在p型基板310内作为共同源极区域的n型端312与作为漏极区域的n型端314与316形成。多晶硅字(栅极)线320、322形成了存取晶体管的栅极。层间介质层330包括介质填充物330a、330b、330c,其中介质填充物330b形成在多晶硅字线320、322上。适合用于该层间介质层330的材料包括硼磷硅玻璃氧化物(BPSG oxide)与等离子体增强正硅酸乙酯(PETEOS)氧化物。该层经图案化,并形成导电结构,包括共同源极线与接触结构326、328。该导电材料可以是钨或其它适用于接触结构的材料与复合材料。接触结构326、328包括多种形状,包括圆形、方形、或其它依赖于所选设计的适用于接触栓塞的形状。
第一电极345具有周边延伸形状(例如环形),其围绕接触结构326的内壁。相似地,第一电极347具有周边延伸形状(例如环形),其围绕接触结构328的内壁。每一该第一电极345、347由如氮化钛的导电材料所构成。该导电材料可以是钨或其它适用于栓塞与导线结构的材料与组合物。共同源极线接触源极区域,并沿着阵列中的列作用为共同源极线。该接触结构326、328分别接触漏极端314、316。
图4示出根据本发明第一实施例的用以制造双稳态桥路电阻随机存取存储器的第二步骤的剖面图400,其包括钨凹陷蚀刻,沉积衬底介质层,以及沉积第二电极。在接触结构326中,接触结构326中的钨的顶部被蚀刻,蚀刻深宽比约为1∶1。在蚀刻步骤中,层间介质层330的选择性足够高以避免介质填充物330a、330b受到蚀刻的损伤。适用于钨蚀刻的化合物为六氟化硫(SF6)。相对于接触孔的尺寸选择钨蚀刻的深度。在一个实施例中,对于0.2μm的接触孔而言,栓塞326的钨蚀刻深度约为200nm。衬底介质层410沉积在接触结构中的钨金属的剩余部分,并沿着第一电极345的内壁利用化学气相沉积(CVD)工艺进行。该衬底介质层410的选择条件,为具有低导热性特征的物质,例如二氧化硅。第二电极420沉积在衬底介质层410、衬底介质层412内,以及沉积在介质填充物330a、330b、330c的上表面上。第二电极420可利用钨、氮化钛、氮化钽,或其它可提供充分导电性同时具有低导热性特征的材料来实施。
管状单元中的衬底介质层410可包括二氧化硅、氮氧化硅、氮化硅、氧化铝、其它低K值(低介电常数)介质,或氧化物-氮化物-氧化物(ONO)或硅-氧化物-氮化物-氧化物(SONO)多层结构。或者,该填充物可包括电绝缘体,其包括一种或多种选自包括硅、钛、铝、钽、氮、氧和碳的组中的元素。在优选元件中,该填充物具有低导热性,约低于0.014J/cm*K*sec。在一个优选实施例中,该热绝缘体的导热性低于相变材料的非晶态的导热性,或者对于包含有GST的相变材料而言,约低于0.003J/cm*K*sec。代表性的绝热材料包括由硅、碳、氧、氟和氢所组成的复合材料。可用于热绝缘填充层的热绝缘材料的例子,包括二氧化硅、SiCOH、聚亚酰胺、聚酰胺、以及氟碳聚合物。其它可用于热绝缘填充层中的材料的例子,包括氟化的二氧化硅、硅氧烷(silsesquioxane)、聚亚芳香醚(polyaryleneether)、聚对二甲苯(parylene)、含氟聚合物、含氟非晶碳、类金刚石碳、多孔性二氧化硅、中孔性二氧化硅、多孔性硅氧烷、多孔性聚亚酰胺,以及多孔性聚亚芳香醚。单层或复合层均可提供热绝缘与电绝缘效果。
图5示出剖面图500,其说明在第一实施例中制造双稳态桥路电阻随机存取存储器时的第三步骤,包括抛光第二电极,沉积电阻存储材料,以及图案化该电阻存储材料。第二电极420的上表面被抛光,以移除过量的可能从接触材料326、328中露出的材料,进而在第一接触结构326中形成第二电极420a,并在第二接触结构328中形成第二电极420b。抛光工艺的实施例包括化学机械抛光工艺,随后是毛刷清洁与液体和/或气体清洁程序,如在本领域中所公知的那样。或者,进行化学机械抛光时,可进行至过度抛光程度,以同时移除可能突出于接触结构326的衬底介质层410。第二电极420a通过薄衬底介质层410与第一电极345隔开。第一电极345、衬底介质层410、与第二电极420a的上表面位于同一平面。
电阻存储材料通过光刻工艺被图案化,以形成电阻存储材料桥路510,其中电阻存储材料桥路510的长度大于衬底介质层410的厚度。相似地,电阻存储材料由光刻工艺图案化以形成电阻存储材料桥路520,其中电阻存储材料桥路520的长度大于衬底介质层412的厚度。电阻存储材料桥路510被蚀刻,以允许第一电极345连接至第二电极420a。电阻存储材料桥路510的适合形状为方形,但也可以使用其它形状。电阻存储材料桥路510的优选宽度介于10至80nm之间。
电阻存储材料桥路510、520的成分可以从许多材料中选择,包括但不限于,硫族化物材料、超巨磁阻(CMR)材料、双元素化合物、以及聚合物材料。存储单元的实施例包括以相变为基础的存储材料作为桥路,包括以硫族化物为基础的材料与其它材料。硫族化物包括下列四种元素中的任何一种:氧(O)、硫(S)、硒(Se)、以及碲(Te),形成元素周期表上第VI族的部分。硫族化物包括将硫族元素与更为正电性的元素或自由基结合而得。硫族化合物合金包括将硫族化合物与其它物质如过渡金属等结合。硫族化合物合金通常包括一个以上选自元素周期表第六列的元素,例如锗(Ge)和锡(Sn)。通常,硫族化合物合金包括下列元素中的一个或多个的复合物:锑(Sb)、镓(Ga)、铟(In)、以及银(Ag)。许多以相变为基础的存储材料已经在技术文件中进行了描述,包括下列合金:镓/锑、铟/锑、铟/硒、锑/碲、锗/碲、锗/锑/碲、铟/锑/碲、镓/硒/碲、锡/锑/碲、铟/锑/锗、银/铟/锑/碲、锗/锡/锑/碲、锗/锑/硒/碲、以及碲/锗/锑/硫。在锗/锑/碲合金家族中,可以尝试大范围的合金成分。该成分可以下列特征式表示:TeaGebSb100-(a+b)。一位研究员描述了最有用的合金为,在沉积材料中所包含的平均碲浓度远低于70%,典型的是低于60%,并在一般形态合金中的碲含量范围从最低23%至最高58%,且最佳是介于48%至58%的碲含量。锗的浓度高于约5%,且其在材料中的平均范围是从最低8%至最高30%,一般低于50%。最佳地,锗的浓度范围介于8%至40%。在该成分中所剩下的主要成分则为锑。上述百分比为原子百分比,其为所有组成元素加总为100%。(Ovshinky‘112专利,栏10~11)由另一研究者所评估的特殊合金包括Ge2Sb2Te5、GeSb2Te4、以及GeSb4Te7。(Noboru Yamada,”Potential of Ge-Sb-Te Phase-changeOptical Disks for High-Data-Rate Recording”,SPIE v.3109,pp.28-37(1997))更一般地,过渡金属如铬(Cr)、铁(Fe)、镍(Ni)、铌(Nb)、钯(Pd)、铂(Pt)、以及上述的混合物或合金,可与锗/锑/碲结合以形成相变合金,其包括有可编程的电阻性质。可使用的存储材料的特殊例子,如Ovshinsky‘112专利中栏11-13所述,在此列入参考。
在该存储单元的有源沟道区域中,相变合金可在第一结构态与一第二结构态之间以其局部次序切换,其中第一结构态一般为非晶固态(amorphous solid phase),而第二结构态一般为结晶固态(crystalline solid phase)。该合金至少为双稳态的。该词汇“非晶”是用以指称相对较无次序的结构,其较之单晶更无次序性,而带有可侦测的特征如较之晶态更高的电阻值。该词汇“晶态”是用以指称相对较有次序的结构,其较非晶态更有次序,因此包括有可侦测的特征例如比非晶态更低的电阻值。典型地,相变材料可电切换至完全晶态与完全非晶态之间所有可侦测的不同状态。其它受到非晶态与晶态的改变而影响的材料特中包括,原子次序、自由电子密度、以及活化能。该材料可切换成为不同的固态、或可切换成为由两种以上固态所形成的混合物,提供从非晶态至晶态之间的灰阶部分。该材料中的电性质亦可能随之改变。
相变合金可通过施加电脉冲而从一种相态切换至另一相态。先前观察指出,较短、较大幅度的脉冲倾向于将相变材料的相态改变成大体为非晶态。较长、较低幅度的脉冲倾向于将相变材料的相态改变成大体为晶态。在较短、较大幅度脉冲中的能量,够大因此足以破坏结晶结构的键结,同时够短因此可以防止原子再次排列成晶态。在没有不适当实验的情形下,可决定特别适用于特定相变合金的适当脉冲量变曲线。在本文的后续部分,该相变材料是以GST代称,同时也需了解,也可使用其它类型的相变材料。在本文中所描述的一种适用于PCRAM中的材料,为GexSbyTez,其中x∶y∶z=2∶2∶5。其它GexSbyTez的成分包括x:0~5;y:0~5;z:0~10。
可用于本发明其它实施例中的其它可编程的存储材料包括,掺杂N2的GST、GexSby、或其它以不同晶态转换来决定电阻的物质;PrxCayMnO3、PrSrMnO3、ZrOx、或其它使用电脉冲以改变电阻状态的物质;TCNQ(7,7,8,8-tetracyanoquinodimethane)、PCBM(methanofullerene 6,6-phenyl C61-butyric acid methyl ester)、TCNQ-PCBM、Cu-TCNQ、Ag-TCNQ、C60-TCNQ、以其它物质掺杂的TCNQ、或任何其它聚合物材料,其包括有以电脉冲而控制的双稳态或多稳态电阻态;超巨磁阻(CMR)材料,如PrxCayMnO3,其中x∶y=0.5∶0.5、或其它成分为x:0~1;y:0~1、或其它包括有锰氧化物的超巨磁阻材料;以及双元素化合物,如NixOy,其中x∶y=0.5∶0.5、或其它成分为x:0~1;y:0~1。
图6示出剖面图600,其说明在第一实施例中制造双稳态桥路电阻随机存取存储器的第四步骤,包括沉积第二衬底介质层,沉积金属层间介质层,以及图案化通孔。第二衬底介质层610沉积在电阻存储材料桥路510、520上,并遍布整个剖面图600的上表面。金属层间介质层620形成在第二衬底介质层610的上表面上。金属层间介质层620的蚀刻选择性实质上与第二衬底介质层610相同或类似。适合实施金属层间介质层620的材料为二氧化硅。第一通孔630经蚀刻并停止在第二衬底介质层610上而被图案化。第二通孔632经蚀刻并停止在第二衬底介质层610上而被图案化。适用于通孔蚀刻的化合物用于以氟为基础的干式蚀刻,并选择性地停止在第二衬底介质层610上。
图7示出剖面图700,其说明在第一实施例中制造双稳态桥路电阻随机存取存储器的第五步骤,包括形成金属层间介质隔离物,形成第二介质突破,并形成位线。金属层间介质隔离物710、712通过化学气相沉积而沉积在通孔630、632中。金属层间介质隔离物710、712的目的是在第二介质突破步骤之后保护电阻存储材料。当金属层间介质隔离物710、712之间隔离物蚀刻停止在第二衬底介质层610上时,则利用以氟为基础的各向异性干式蚀刻工艺而进行第二介质突破步骤,该蚀刻停止在第二电极420a、420b的上表面上。位线720沉积在金属层间介质隔离物710、712内,并在金属层间介质层620上形成金属化层。位线720的方向垂直于栅极或字线。
图8示出第二实施例中的桥路电阻随机存取存储器800的剖面图,包括沉积金属层间介质层810,以及图案化通孔820、822。金属层间介质层810沉积在电阻存储材料桥路510、520上,并且不包括在第一实施例中所示的第二衬底介质层。二氧化硅为可用于金属层间介质层810中的适合材料。第一通孔820利用蚀刻步骤而被图案化,该蚀刻步骤停止在第二电极420a的上表面上。选择通孔820的尺寸,使得通孔820够小而可座落在第二电极420a上。适用于通孔蚀刻的化合物用于以氟为基础的干式蚀刻。通孔820的深宽比为约1~2。图9是第二实施例的桥路电阻随机存取存储器的剖面图900,包括沉积位线910。位线910沉积在通孔820、822内,并在金属层间介质层810上形成金属层。位线910的方向垂直于栅极或字线。
图10是本发明第三实施例的桥路电阻随机存取存储器的剖面图1000,包括将硬掩模沉积在电阻存储材料桥路上。第二电极420的上表面被抛光,以移除突出于接触结构326、328的过量材料,而生成在第一接触结构326中的第二电极420a、以及位于第二接触结构328中的第二电极420b。抛光工艺的实施例包括化学机械抛光工艺,随后是毛刷清洁与液体和/或气体清洁程序,如在本领域中所公知的那样。或者,进行化学机械抛光时,可进行至超抛光程度,以同时移除可能突出于接触结构326的衬底介质层410。第二电极420a通过薄膜衬底介质层410而与第一电极345分隔开。第一电极345、衬底介质层410、以及第二电极420a的上表面位于同一平面。
电阻存储材料通过光刻工艺被图案化,以形成电阻存储材料桥路510,其中电阻存储材料桥路510的长度大于衬底介质层410的厚度。相似地,电阻存储材料由光刻工艺图案化以形成电阻存储材料桥路520,其中电阻存储材料路桥520的长度大于衬底介质层412的厚度。电阻存储材料桥路510被蚀刻,以允许第一电极345连接至第二电极420a。电阻存储材料桥路510的适合形状为方形,但也可使用其它形状。电阻存储材料桥路510的优选宽度介于10至80nm之间。
硬掩模1010沉积在电阻存储材料桥路510上。该硬掩模1010包括介质材料,如二氧化硅。对于硬掩模1010以及第一与第二电极345、420a而言,该蚀刻步骤可为单步骤各向异性蚀刻,或为双步骤工艺,先以第一蚀刻化合物蚀刻硬掩模1010,接着以第二蚀刻化合物蚀刻第一与第二电极345、420a。在一个实施例中,硬掩模1010的蚀刻速率远小于第二电极420a与在接触结构326中的第一电极345的侧壁的蚀刻速率。适合的蚀刻方式是使用以Cl2为基础的化合物的干式蚀刻。
图11是剖面图1100,其说明第三实施例的桥路电阻随机存取存储器,包括回蚀刻第一与第二电极,以及沉积衬底介质层。第一与第二电极345、420a的回蚀刻,可视其材料种类而定。在一个实施例中,第一与第二电极345、420a使用氮化钛。针对第一与第二电极345、420a中的氮化钛所进行的回蚀刻,可通过利用以Cl2为基础的化合物进行的干式蚀刻来完成。在另一实施例中,第一电极345包括氮化钛材料,而第二电极420a则包括钨材料。氮化钛材料与钨材料的回蚀刻通过两步骤干蚀刻工艺来完成,其中以Cl2为基础的化合物用以在第一蚀刻步骤中蚀刻氮化钛,而以SF6为基础的化合物则在第二蚀刻步骤中蚀刻钨材料。在回蚀刻之后,衬底介质层1110沉积在剖面图1100的整个上表面上。将该衬底介质层1110设计为足够顺形,以使得衬底介质层1110的沉积可允许在第一电极345的回蚀刻之后,将介质填充物填入在孔洞中。该衬底介质层1110的材料,可从氮化硅或二氧化硅中选择。衬底介质层1110的适当厚度为约20nm。
图12是剖面图1200,说明第三实施例中的桥路电阻随机存取存储器,包括蚀刻介质隔离物,并形成位线。在图11中的衬底介质层1110被蚀刻以在侧壁上形成介质隔离物。该介质隔离物位于第二电极420a的上表面上,而剩余的衬底介质层410则将第一电极345与第二电极420a分隔开。在第一电极345中,表面上的衬底介质层1110可以被移除,但是衬底介质填充物1112仍残留在第一电极345上。可以通过利用以氟为基础的化合物进行的各向异性干式蚀刻对介质隔离物1210进行蚀刻。在形成介质隔离物1210之后,位线1220沉积在介质隔离物1210内,并形成金属化层。位线1220的方向垂直于栅极或字线。
图13是剖面图1300,其说明第三实施例中的桥路电阻随机存取存储器,包括示例性电流路径1310。在示例性路径中,从源极312流出,流经漏极314,再流经接触结构326,再流经第一电极345,再流经电阻存储材料桥路510,再流经第二电极420a,到达位线1220。
图14A是剖面图,其说明以管状构件1400为基础的存储单元实施例,该管状构件1400耦合到可编程电阻材料510,而图14B是正交剖面图,其说明具有第一与第二电极的管状构件。管状构件1400包括侧壁,侧壁则具有内表面345a与外表面345b,其均为圆筒状。第一电极345的厚度T限定在内表面345a与外表面345b之间。因此,内表面345a与外表面345b可以被理解为基本上为圆柱状的表面,典型地限定为平行于固定直线移动的表面轨迹并与固定曲线相交,而对于圆柱而言该固定直线位于管状构件的中央(或轴心),而该固定曲线为以该固定直线为中心的圆形。该圆柱状的内表面345a与外表面345b,可以分别由具有不同半径的圆(差异为管状构件的厚度)所代表,并因此限定管状构件的内部与外部周缘。在管状构件的实施例中,圆柱状形状具有圆形、椭圆形、方形或不规则形状的外周缘,取决于形成管状构件时所使用的制造技术。因此,此处所描述的“环形”上表面,并非必须为圆形,而是管状构件的横截面的形状。
图15是布局图1500,其说明制造桥路电阻随机存取存储器的示例性制造参数。环绕着接触结构而具有周边延伸形状的第一电极345,其厚度约为100埃。用以分隔第一电极345与第二电极420a的衬底介质层410,其厚度约为100埃。用以接触第一电极345与第二电极420a的电阻存储材料桥路510的宽度约为400埃,而厚度约为100埃。
“环形”不仅包括圆形,也包括其它周边延伸形状,无论其为规则或不规则的周边延伸形状,取决于制造工艺。
对于相变随机存取存储元件的额外制造信息、元件材料、使用、与操作方法,请参见美国专利申请No.11/155,067,其名称为“ThinFilm Fuse Phase Change RAM and Manufacturing Method”,申请日为2005年6月17日,申请人与本案相同,且该专利申请并入本申请作为参考。
虽然本发明是参考优选实施例来加以描述的,但应该理解的是,本发明的创造并不受限于其详细描述内容。替换方式及修改样式已在先前描述中所建议,并且本领域技术人员将能想到其它替换方式及修改样式。特别是,根据本发明的结构与方法,所有具有实质上相同于本发明的构件结合而实现与本发明实质上相同的技术方案皆不脱离本发明的精神和范围。因此,所有这些替换方式及修改样式旨在落入本发明所附权利要求及其等同物所限定的范畴中。任何在前文中提及的专利申请以及印刷文本,均列为本申请的参考。
Claims (40)
1、一种在桥路结构中的存储元件,该桥路结构包括接触结构,该存储元件包括:
第一电极,位于该接触结构内,具有周边延伸的形状,且环绕该接触结构的内壁;
第二电极,位于该接触结构内且位于所述第一电极的周边延伸的形状内;
绝缘材料,其隔离该第一与第二电极;以及
存储材料,沉积在该桥路结构中,该桥路结构与该第一电极的上表面与该第二电极的上表面接触。
2、如权利要求1所述的元件,该存储材料还包括电阻存储材料,其水平延伸并与该第一电极、该绝缘材料、以及该第二电极接触。
3、如权利要求2所述的元件,还包括设置在该电阻存储材料上的隔离物,其保护该电阻存储材料在蚀刻过程中不受到破坏。
4、如权利要求3所述的元件,还包括位线,其包括沉积在该隔离物内的导电材料,该位线与该第二电极接触。
5、如权利要求1所述的元件,还包括形成在该第二电极的上表面上的通孔;以及位线,其包括沉积在该通孔内的导电材料。
6、如权利要求2所述的元件,还包括形成在该电阻存储材料上的硬掩模。
7、如权利要求1所述的元件,还包括导电材料,其沉积在位于该第二电极下方的栓塞内并填满该栓塞内的孔洞的一部份。
8、如权利要求2所述的元件,其中该电阻存储材料包括方形结构。
9、如权利要求1所述的元件,其中该第二电极包括钨、氮化钛、或氮化钽。
10、如权利要求1所述的元件,其中该第一电极电连接至晶体管端子。
11、如权利要求1所述的元件,其中该第二电极电连接至位线。
12、如权利要求2所述的元件,其中该电阻存储材料包括硫族化物。
13、如权利要求2所述的元件,其中该电阻存储材料具有至少两个固态相,该至少两个固态相之间可通过电流而可逆地诱发。
14、如权利要求2所述的元件,其中该电阻存储材料具有至少两个固态相,该至少两个固态相包括大部分为非晶相与大部分为结晶相。
15、如权利要求2所述的元件,其中该电阻存储材料包括锗、锑、碲。
16、如权利要求2所述的元件,其中该电阻存储材料包括选自包括锗(Ge)、锑(Sb)、碲(Te)、硒(Se)、铟(In)、钛(Ti)、镓(Ga)、铋(Bi)、锡(Sn)、铜(Cu)、钯(Pd)、铅(Pb)、银(Ag)、硫(S)及金(Au)的组中的至少两种所形成的组合物。
17、如权利要求2所述的元件,其中该电阻存储材料包括超巨磁阻(CMR)材料。
18、如权利要求2所述的元件,其中该电阻存储材料包括双元素化合物。
19、如权利要求1所述的元件,还包括接触结构,且该第一与第二电极设置在该接触结构内。
20、一种用以制造存储元件的方法,包括:
提供晶体管本体,其具有接触结构与层间介质,该接触结构具有内壁;
形成第一电极,该第一电极具有沿着该接触结构的内壁延伸的区域;
蚀刻该接触结构的顶部以将第一介质层沉积在该区域内;
将第二电极沉积在该第一介质层中;以及
将存储材料沉积在一桥路结构中,该桥路结构与该第一电极和该第二电极的上表面接触。
21、如权利要求20所述的方法,其中该存储材料包括电阻存储材料。
22、如权利要求21所述的方法,还包括将第二介质沉积在该第一电极、该第一介质层、该第二电极、与该电阻存储材料的上表面上。
23、如权利要求22所述的方法,还包括通过选择性蚀刻该第二介质,以形成通孔。
24、如权利要求23所述的方法,还包括将间隔物形成在该通孔中,以保护该电阻存储材料不被该第二介质的蚀刻过程破坏;以及将包括有导电材料的位线沉积在该间隔物中并形成该位线。
25、如权利要求20所述的方法,还包括通过选择性蚀刻该第二电极的上表面而形成通孔;以及将包括有导电材料的位线沉积在该通孔中。
26、如权利要求21所述的方法,还包括将硬掩模沉积在该电阻存储材料上。
27、如权利要求26所述的方法,还包括通过使用具有以Cl2为基础的化合物的干式蚀刻,来回蚀刻该第一与第二电极。
28、如权利要求27所述的方法,还包括将第二介质沉积在该第一电极、该第一介质层、该第二电极、与该硬掩模上。
29、如权利要求28所述的方法,还包括蚀刻该第二介质以将介质间隔物形成在该第二电极的上表面上;以及将包括有导电材料的位线沉积在该介质间隔物中。
30、如权利要求28所述的方法,其中该第二介质包括氮化硅或二氧化硅。
31、如权利要求20所述的方法,其中该蚀刻步骤包括具有六氟化硫(SF6)的蚀刻化合物。
32、如权利要求20所述的方法,在该沉积步骤之后,还包括抛光该第二电极的上表面,以移除突出于该接触结构的上表面的过量材料。
33、如权利要求21所述的方法,其中该电阻存储材料包括硫族化物。
34、如权利要求21所述的方法,其中该电阻存储材料具有至少两个固态相,该两个固态相之间可通过电流而可逆地诱发。
35、如权利要求21所述的方法,其中该电阻存储材料具有至少至少两个固态相,该至少两个固态相包括大部分为非晶相与大部分为结晶相。
36、如权利要求21所述的方法,其中该电阻存储材料包括锗、锑、碲。
37、如权利要求21所述的方法,其中该电阻存储材料包括选自包括锗(Ge)、锑(Sb)、碲(Te)、硒(Se)、铟(In)、钛(Ti)、镓(Ga)、铋(Bi)、锡(Sn)、铜(Cu)、钯(Pd)、铅(Pb)、银(Ag)、硫(S)及金(Au)的组中的至少二种所形成的组合物。
38、如权利要求21所述的方法,其中该电阻存储材料包括超巨磁阻(CMR)材料。
39、如权利要求21所述的方法,其中该电阻存储材料包括双元素化合物。
40、如权利要求20所述的方法,还包括将钨沉积在该第一电极的区域内。
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