A7 B7 469581 5l57twf.doc/008 五、發明說明（（） 本發明是有關於一種半導體元件的製造方法，且特 別是有關於一種進行導線定義時，可縮小光阻線寬，藉以 縮小導線線寬的方法。 在積體電路的製程中，爲了製作閘極、導線與電極 等導電結構，往往需要以微影蝕刻技術來定義導電層。 由於積體電路的積集度不斷提昇，導電層的關鍵尺寸 (Critical Dimension ; CD)也隨著減小，因此需要持續改 善定義導電層的精確度。但是，當積體電路的線寬到達 〇·25微米以下的程度時，導電層的關鍵尺寸卻受限於進 行微影步驟之機台的光學解析度（Optical Resolution)，而 無法達到製程的要求。 而且’對於〇·21μιη的動態隨機存取記憶體而言， 其多晶矽位元線已被要求達到0.18 μιη，甚至更小的線 寬。然而’在定義位兀線時，遭遇到製程窗（process window) 的瓶頸，容易發生對準失誤（misalign)，或所形成的開口 過大，因而導致短路（short)的情形。 習知解決上述方法之一爲縮小導線的線寬，其係採 用氧電漿，並對其電漿產生器之上下電極通以能量，來 壓縮光阻的線寬，以爭取較大的製程窗。然而，此法雖 然可以達到縮小導電層之關鍵尺寸的目的，但是此方法 在蝕刻過程中，會造成光阻損失（loss)相當嚴重，而且所 縮小的線寬寬度有限等問題。 因此’本發明的目的之一就是在提供一種定義導線 的方法’在不消耗大量光阻的情況下，縮小光阻的線寬， 3 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐） (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製A7 B7 469581 5l57twf.doc / 008 V. Description of the invention (() The present invention relates to a method for manufacturing a semiconductor element, and particularly to a method for defining a wire, which can reduce the width of a photoresistor line, thereby reducing the wire width. In the manufacturing process of integrated circuits, in order to make conductive structures such as gates, wires, and electrodes, it is often necessary to define the conductive layer by lithographic etching technology. As the integration of integrated circuits continues to increase, the key to conductive layers As the critical dimension (CD) also decreases, the accuracy of defining the conductive layer needs to be continuously improved. However, when the line width of the integrated circuit reaches a level below 0.25 micron, the critical size of the conductive layer is affected. It is limited to the optical resolution of the lithography machine and cannot meet the requirements of the manufacturing process. And 'for the dynamic random access memory of 0.21 μm, its polycrystalline silicon bit line has been required to achieve 0.18 μιη, even smaller line width. However, when defining a bit line, it encounters the bottleneck of the process window, which is prone to Misalignment, or the opening formed is too large, resulting in a short. One of the known solutions to the above is to reduce the line width of the wire, which uses oxygen plasma, and the plasma generator The upper and lower electrodes are energized to compress the line width of the photoresist to obtain a larger process window. However, although this method can achieve the purpose of reducing the critical size of the conductive layer, this method will cause photoresist during the etching process The loss is quite serious, and the reduced line width and width are limited. Therefore, 'one of the objectives of the present invention is to provide a method for defining a wire', without reducing a large amount of photoresist, reducing the line of the photoresist Wide, 3 This paper size applies to Chinese National Standard (CNS) A4 (210x297 mm) (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs
A7 B7 469 58 5l57twf.doc/008 31、發明說明（> ) 進而得到更小線寬的導線。 本發明的另一個目的是在提供一種縮小導線線寬的 方法’可以解決定義導線時所遭遇製程窗瓶頸的問題。 本發明的再一個目的是在提供一種縮小導線線寬的 方法’可於定義位元線時，得到較小線寬的位元線，藉以 避免習知容易發生短路等問題。 根據本發明之上述目的，提出一種定義導線的方法， 當定義導線時，其蝕刻步驟採用氧氣與氯氣作爲電漿氣體 源’而且僅對電禁產生器之上電極施加能量，以縮小光阻 層的線寬，藉以形成較小線寬的導線。 爲讓本發明之上述目的、特徵、和優點能更明顯易 懂，下文特舉一較佳實施例’並配合所附圖式，作詳細說 明如下： 第1A至1D圖繪示依照本發明一較佳實施例之一種 導線的製造流程剖面圖。 圖式之簡單說明： 100 :基底 102 :導電層 104、104a :多晶矽層 106、106a :矽化鎢層 108、108a :光阻層 實施輒 第1A至1D圖繪示依照本發明一較佳實施例之一種 導線的製造流程剖面圖。 4 (請先間讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 n ^6,、· .^1 n I 1 u ( i f— D n n ti 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） 469581 A7 5157twf.doc/008 37 經濟部智慧財產局員工消費合作杜印製 五、發明說明（乃） 請參照第1A圖，提供一半導體基底100，基底100 上例如包括一電晶體（未繪示），基底100上更包括一介電 層（未顯示）覆蓋電晶體。接著，於基底100上形成一導電 層102，導電層102例如以典型的化學氣相沈積法，依序 沈積一多晶矽層104與一矽化鎢層106而形成。多晶矽層 104的厚度約爲1000埃，矽化鎢層106的厚度約爲1〇〇〇 埃。 請參照第1B圖，於導電層102上形成一線寬爲”a” 之圖案化光阻層108，光阻層108覆蓋的區域即爲欲形成 導線之區域。 請參照第1C圖，對包括多晶矽層104與矽化鎢層106 之導電層102進行一蝕刻步驟，此蝕刻步驟係於一電漿產 生器中進行，採用包括氧氣與氯氣的混合氣體來作爲電漿 氣體源。在進行蝕刻步驟過程中，僅對電漿產生器的上電 極施加能量，而不對其下電極施加能量。此時，氧氣會完 全解離爲氧自由基（radicle)，而氯氣則可輔助電漿，增加 電漿的穩定度。 由於此步驟中不對電漿產生器之下電極施以能量， 氧氣與氯氣形成電獎後，將會全方位等向性（isotropic)的 去除光阻層108的側壁與頂端，如此形成了具有較小線 寬”b”的光阻層108a，進而得到具有線寬較小之導線102a， 其中導線102a包括多晶矽層104a與矽化鎢層106a。 此蝕刻步驟所採用的蝕刻氣體中，氧氣的氣體流速 約爲10-60sccm，較佳約爲50scCm ;氯氣的氣體流速約爲 5 (請先閲讀背面之注意事項再填寫本頁) 訂---------線丨-------------1! 本紙張尺度適用尹國國家標準（CNS)A4規格（210x297公釐） A7 B7 4 69 58 5l57twf.doc/〇〇8 •、發明說明（C ) 80-120sccm，較佳約爲100sccm。電漿產生器的上電極所 施加之能量約爲600-1000瓦，較佳約爲800瓦。而電漿 產生器中的壓力約爲5_12 mtorr，較佳約爲i〇mtorr。 請參照第1D圖’去除光阻層i〇8a，而得到一較小線 寬之導電層102。 本發明可應用於動態隨機存取記憶體（dynamic random access memory，DRAM)之製造，如此定義出的導電 層即爲位元線（bit line)。 綜上所述’本發明的特徵在於當進行導線的定義時， 以氧氣與氯氣作爲電漿氣體源，且僅對電漿產生器之上電 極施以能量’使得氧電漿會等向性地蝕刻光阻層的側壁， 藉以縮小光阻層的線寬，進而得到縮小線寬的導線。 本發明不對電漿產生器的下電極施加能量，利用電 獎氣體的等向性蝕刻，來縮小光阻的線寬，而形成較小線 寬的導線’如此避免了導線之關鍵尺寸受限於進行微影 步驟之機台的光學解析度的問題。 再者’由於本發明可縮小導線的線寬，當應用於動 態隨機存取記憶體的製造時，因爲爭取了較大的製程窗， 故可避免習知因製程窗的限制而產生的短路問題。 此外’本發明不但可以用於導線的定義，亦可適用 於形成電晶體之閘極、導電結構、電容器的電極以及其 他導電層的製作。 本發明當有其他優點、目的及特徵，顯示於上文和' 後述之專利申請範圍之中，或是在實施本發明的過程中 6 本紙張尺度適用中國國家標準（CNS)A4規格（2i〇x 297公楚） (請先閱讀背面之注意事項再填寫本頁) 訂---I---!線1.. 經濟部智慧財產局員工消費合作杜印製 469581 A7 5i57twf.d〇c/008 β-7 經濟部智慧財產局員工消費合作社印製 五、發明說明（欠） 顯示出來。 雖然本發明已以一較佳實施例揭露如上，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍內，當可作各種之更動與潤飾’因此本發明之 保護範圍當視後附之申請專利範圍所界定者爲準。 {請先閱讀背面之注意事項再填寫本頁) -n |> ^-jeJI n 線-( 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐）A7 B7 469 58 5l57twf.doc / 008 31. Description of the invention (>) Further, a wire with a smaller line width is obtained. Another object of the present invention is to provide a method for reducing the wire width of a wire, which can solve the problem of a process window bottleneck encountered when defining a wire. It is still another object of the present invention to provide a method for reducing the line width of a conductive wire ', which can be used to obtain a bit line with a smaller line width when defining a bit line, thereby avoiding problems such as the susceptibility to short circuits in the conventional art. According to the above purpose of the present invention, a method for defining a wire is proposed. When defining a wire, its etching step uses oxygen and chlorine gas as a plasma gas source 'and applies energy only to the electrode above the electric generator to reduce the photoresist layer. Wire width to form a smaller wire width. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings, and described in detail as follows: FIGS. 1A to 1D illustrate one embodiment of the present invention. A cross-sectional view of a manufacturing process of a conductive wire in a preferred embodiment. Brief description of the drawings: 100: substrate 102: conductive layer 104, 104a: polycrystalline silicon layer 106, 106a: tungsten silicide layer 108, 108a: photoresist layer implementation. Figures 1A to 1D illustrate a preferred embodiment according to the present invention. A cross-sectional view of the manufacturing process of one kind of wire. 4 (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs n ^ 6 ,,. .1 1 I I u (if— D nn ti Standard (CNS) A4 specification (210 x 297 mm) 469581 A7 5157twf.doc / 008 37 Intellectual Property Bureau, Ministry of Economic Affairs, Consumption Cooperation by Employees 5. Printed Description of the Invention (Yes) Please refer to Figure 1A to provide a semiconductor substrate 100 The substrate 100 includes, for example, a transistor (not shown), and the substrate 100 further includes a dielectric layer (not shown) to cover the transistor. Next, a conductive layer 102 is formed on the substrate 100. The conductive layer 102 is typically The chemical vapor deposition method is formed by sequentially depositing a polycrystalline silicon layer 104 and a tungsten silicide layer 106. The thickness of the polycrystalline silicon layer 104 is about 1000 angstroms, and the thickness of the tungsten silicide layer 106 is about 1000 angstroms. In FIG. 1B, a patterned photoresist layer 108 having a line width “a” is formed on the conductive layer 102. The area covered by the photoresist layer 108 is the area where the wires are to be formed. Referring to FIG. 1C, the polysilicon layer 104 and The conductive layer 102 of the tungsten silicide layer 106 is The etching step is performed in a plasma generator, and a mixed gas including oxygen and chlorine gas is used as a plasma gas source. During the etching step, energy is applied only to the upper electrode of the plasma generator. No energy is applied to its lower electrode. At this time, oxygen will completely dissociate into oxygen radicals, while chlorine can assist the plasma, increasing the stability of the plasma. Because the electrode below the plasma generator is not used in this step. After the energy is applied, oxygen and chlorine gas form an electrical award, and the sidewalls and tops of the photoresist layer 108 will be removed isotropically in all directions, thus forming a photoresist layer 108a with a smaller line width "b". Further, a wire 102a having a smaller line width is obtained, wherein the wire 102a includes a polycrystalline silicon layer 104a and a tungsten silicide layer 106a. In the etching gas used in this etching step, the gas flow rate of oxygen is about 10-60 sccm, preferably about 50 scCm; Chlorine gas flow rate is about 5 (Please read the precautions on the back before filling this page) Order --------- Line 丨 ------------- 1! This paper size Applicable Yin National Standard (CNS) A4 specification (21 0x297 mm) A7 B7 4 69 58 5l57twf.doc / 〇〇8 • Description of the invention (C) 80-120sccm, preferably about 100sccm. The energy applied by the upper electrode of the plasma generator is about 600-1000 watts , Preferably about 800 watts. The pressure in the plasma generator is about 5-12 mtorr, preferably about 〇mtorr. Please refer to Figure 1D 'remove the photoresist layer 〇8a, and get a smaller line width The conductive layer 102. The present invention can be applied to the manufacture of dynamic random access memory (DRAM). The conductive layer thus defined is a bit line. In summary, 'The present invention is characterized in that when defining a wire, oxygen and chlorine gas are used as the plasma gas source, and energy is only applied to the electrode above the plasma generator' so that the oxygen plasma will be isotropic. The sidewall of the photoresist layer is etched to reduce the line width of the photoresist layer, thereby obtaining a wire with a reduced line width. The invention does not apply energy to the lower electrode of the plasma generator, and uses the isotropic etching of the electricity award gas to reduce the line width of the photoresist, and forms a wire with a smaller line width. This prevents the critical size of the wire from being limited. Problems with the optical resolution of the machine performing the lithography step. Furthermore, because the present invention can reduce the line width of the wires, when applied to the manufacture of dynamic random access memory, because a larger process window is sought, the short circuit problem caused by the limitation of the process window can be avoided. . In addition, the present invention can be used not only for the definition of wires, but also for the fabrication of gates, conductive structures, capacitor electrodes, and other conductive layers that form transistors. The present invention should have other advantages, objects, and features, as shown in the scope of the above-mentioned patent applications, or in the process of implementing the present invention. 6 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (2i〇). x 297 公 楚) (Please read the notes on the back before filling out this page) Order --- I ---! Line 1: The consumer cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs Du printed 469581 A7 5i57twf.d〇c / 008 β-7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. The invention description (owed) is displayed. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. {Please read the precautions on the back before filling this page) -n | > ^ -jeJI n LINE- (This paper size applies to China National Standard (CNS) A4 (210 x 297 mm)