CN101408902A - Method for acquiring and transporting high speed data based on FPGA and USB bus - Google Patents
Method for acquiring and transporting high speed data based on FPGA and USB bus Download PDFInfo
- Publication number
- CN101408902A CN101408902A CNA2008101565899A CN200810156589A CN101408902A CN 101408902 A CN101408902 A CN 101408902A CN A2008101565899 A CNA2008101565899 A CN A2008101565899A CN 200810156589 A CN200810156589 A CN 200810156589A CN 101408902 A CN101408902 A CN 101408902A
- Authority
- CN
- China
- Prior art keywords
- module
- fpga
- analog
- data
- digital conversion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 9
- 238000006243 chemical reaction Methods 0.000 claims abstract description 44
- 230000005540 biological transmission Effects 0.000 claims abstract description 29
- 238000005070 sampling Methods 0.000 claims abstract description 26
- ZNJRONVKWRHYBF-VOTSOKGWSA-N 4-(dicyanomethylene)-2-methyl-6-julolidyl-9-enyl-4h-pyran Chemical compound O1C(C)=CC(=C(C#N)C#N)C=C1\C=C\C1=CC(CCCN2CCC3)=C2C3=C1 ZNJRONVKWRHYBF-VOTSOKGWSA-N 0.000 claims description 12
- YLYPIBBGWLKELC-RMKNXTFCSA-N 2-[2-[(e)-2-[4-(dimethylamino)phenyl]ethenyl]-6-methylpyran-4-ylidene]propanedinitrile Chemical compound C1=CC(N(C)C)=CC=C1\C=C\C1=CC(=C(C#N)C#N)C=C(C)O1 YLYPIBBGWLKELC-RMKNXTFCSA-N 0.000 claims description 11
- 230000002093 peripheral effect Effects 0.000 claims description 11
- 230000009471 action Effects 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000013501 data transformation Methods 0.000 claims description 4
- 230000006870 function Effects 0.000 claims description 4
- 230000008520 organization Effects 0.000 claims description 4
- 230000004044 response Effects 0.000 claims description 4
- 230000008676 import Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 6
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 4
- 238000012360 testing method Methods 0.000 description 3
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 description 2
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 2
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 102100040856 Dual specificity protein kinase CLK3 Human genes 0.000 description 1
- 102100040858 Dual specificity protein kinase CLK4 Human genes 0.000 description 1
- 101000749304 Homo sapiens Dual specificity protein kinase CLK3 Proteins 0.000 description 1
- 101000749298 Homo sapiens Dual specificity protein kinase CLK4 Proteins 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Images
Landscapes
- Bus Control (AREA)
Abstract
A high-speed data acquisition and transmission method based on an FPGA bus and a USB bus is used for acquiring and transmitting data to an upper PC based on four modules, namely, an analog-to-digital conversion module, an FPGA module, a cache module and a USB transmission module. The method comprises the following steps: (1) the analog-to-digital conversion module realizes the function of converting an input signal to be acquired into a digital signal, receives an analog signal to be acquired input from the outside and a sampling clock input signal from the FPGA module, and outputs the converted digital signal data to the FPGA module; (2) the FPGA module completes a task of caching the digital signal data to an off-chip DDR SDRAM; (3) the cache module is used for caching the digital signal data output by the analog-to-digital conversion module; and (4) the USB transmission module causes the digital signal data stored in the cache module to work with a processor of the FPGA module to transmit the data to a host computer.
Description
One, technical field
The present invention relates to a kind of novel high-speed data acquisition and transmission method and system based on FPGA and USB2.0 bus.
Two, technical background
Data acquisition has been widely used in every field as the basic means of obtaining information.Data acquisition modes commonly used now mainly is based on the card insert type data collecting card of ISA, PCI, and there is following defective in these data collecting cards: trouble is installed; Cost an arm and a leg; Be subjected to computer slot quantity, address, interrupt resources to limit poor expandability; In the strong test site of some electromagnetic interference (EMI), can't do electromagnetic screen to it specially, cause the data distortion of gathering.Simultaneously, the speed and the accuracy requirement of on the engineering data being gathered now is more and more higher, and traditional microcontroller and interface bus can not satisfy this requirement.
Three, summary of the invention
The objective of the invention is: a kind of high-speed data acquisition and transmission system based on FPGA and usb bus (universal serial bus) is provided, make full use of the powerful hardware capability of FPGA, finish data sync in the system, buffer memory control and USB transmission control, constitute a SOC (system on a chip) and make that use, the installation of data acquisition system (DAS) are more convenient flexibly, have collection, transfer rate faster, and the support hot plug, easy to use.
The object of the present invention is achieved like this: based on the high-speed data acquisition and the transmission method of FPGA and usb bus, carry out data acquisition and transmission to upper PC computing machine on the basis of totally four modules at analog-to-digital conversion module, FPGA module, cache module and USB transport module:
1) analog-to-digital conversion module realizes that the conversion of signals to be collected that will import is the function of digital signal.Analog-to-digital conversion module accepts the simulating signal to be collected of outside input and from the sampling clock input signal of FPGA module, the digital signal data after analog-to-digital conversion module will be changed is exported to the FPGA module.2) the FPGA module is finished the task of described digital signal data being cached to the outer DDR SDRAM of sheet, and by making up on the sheet that processor with the FPGA module is a core embedded system and the work of USB module cooperative data is transferred on the PC.The FPGA module is accepted the digital signal data from analog-to-digital conversion module, by the built-in asynchronous data FIFO of FPGA and DDR controller with metadata cache in cache module, cache module is the outer DDR SDRAM storer of sheet,
3) cache module is used for the digital signal data of buffer memory analog-to-digital conversion module output.Cache module is the table tennis storage organization that (by the DDR SDRAM storer of two 32MB) constitutes, and the DDR controller of FPGA inside modules partly is responsible for the read-write operation to this memory device, and digital signal data is temporary in cache module.After the data of table tennis storage organization monolithic memory were filled with in the cache module, the processor that triggers the FPGA module was that the program (program in the PowerPC405) of embedded system controller is transferred to data in the cache module in the internal RAM of USB controller on the sheet of core.
4) digital signal data that is stored in the most at last in the cache module of USB transport module is transferred to PC.The USB transmission command that USB transport module response main frame sends with the PowerPC405 collaborative work, arrives main frame with the data transmission that collects.
Based on the high-speed data acquisition and the transmission system of FPGA and usb bus, system is by analog-to-digital conversion module, the FPGA module, and cache module and USB transport module totally four modules are formed; Digital dock administrative unit DCM in the FPGA module connects the controlling of sampling end of analog-to-digital conversion module, and analog-to-digital conversion module output connects the asynchronous data mouth FIFO of FPGA, and the DDR controller of FPGA connects the output of cache module; By the DCM1 in the FPGA module 2, asynchronous data FIFO, DDR controller and cache module 3 are finished data acquisition; GPIO controller 7 connects the hardware reset end of USB transport module 4; By the DCM2 in the FPGA module 2, GPIO controller 7, embedded system and USB transport module 4 are finished data-transformation facility jointly on the sheet that peripheral control unit EPC, PowerPC405 processor 11, DDR controller 12 constitute.Most of hardware circuit that plays control, booster action is realized by the programming in logic to the FPGA module in the system.The sampling clock of analog-to-digital conversion module 1 is provided by the DCM1 of FPGA module, and the sampling clock that the FPGA module provides is input to the input end of clock of ADC through the clock input circuit 5 in the analog-to-digital conversion module 1.The hardware reset of USB transport module 4, firmware downloads and program start are by embedded system on the sheet of the DCM2 in the FPGA module 2, GPIO controller 7, peripheral control unit EPC, PowerPC405, DDR controller formation.
The invention has the beneficial effects as follows:
1), employing provides the method for system sampling clock by the configuration to FPGA, reduced sampling clock and produced the interference of circuit the data acquisition system, improved the stability of system, and make the change of sampling clock become convenient, flexibly, can change the sampling clock of system easily and flexibly according to the actual feature of sampled signal for the treatment of in using.
2), FPGA pin configuration flexible and changeable makes that the variation of sampling precision becomes convenient in the system, only need that after the analog-to-digital conversion module is used the ADC parts with new conversion accuracy the pin of FPGA is done corresponding expanded configuration and can adapt to new ADC sampling output, the system that makes has good expandability.
3), the application of FPGA makes data synchronizer unit in the system, the buffer memory control assembly, the USB transmission control element concentrates on the inner realization of a slice FPGA, constitutes a SOC (system on a chip), has simplified the hardware design of data acquisition and transmission system, improve the reliability of system, reduced system cost.
4), the USB2.0 bus system that makes have faster transfer rate (device is suitable, can transmission speed reach 200M/s? more than), and support hot plug, the convenient use.
Four, description of drawings
Fig. 1 is a system architecture diagram of the present invention;
Fig. 2 is the clock input circuit of analog-to-digital conversion module;
Fig. 3 is a FPGA internal module structured flowchart;
Fig. 4 is the usb function program flow diagram;
Fig. 5 is the PowerPC405 program flow diagram;
Fig. 6 is the test and the set operation of control position;
Five, specific embodiments
As shown in the figure, particularly, data acquisition and buffer memory are by DCM1 in the FPGA module 2 and asynchronous data FIFO, and DDR controller 12 and cache module 3 are finished jointly.Data-transformation facility is by the DCM2 in the FPGA module 2, GPIO controller 7, and embedded system and USB transport module 4 are finished jointly on the sheet that peripheral control unit EPC, PowerPC405 processor 11, DDR controller 12 constitute.Most of hardware circuit that plays control, booster action is realized by the programming in logic to the FPGA module in the system.The sampling clock of analog-to-digital conversion module 1 is provided by the DCM1 of FPGA module, and the sampling clock that the FPGA module provides is input to the input end of clock of ADC through the clock input circuit 5 in the analog-to-digital conversion module 1.The hardware reset of USB transport module 4, firmware downloads and program start are finished by embedded system on the sheet of the DCM2 in the FPGA module 2, GPIO controller 7, peripheral control unit EPC, PowerPC405, DDR controller formation.
Shown in Figure 1, comprise based on the high-speed data acquisition and the transmission system of FPGA and USB2.0 bus: analog-to-digital conversion module 1, FPGA module 2, cache module 3, USB transport module 4.Wherein:
1), what analog-to-digital conversion module was accepted outside input treats the sampled analog signal, and is digital signal with the analog signal conversion of input under the driving of the sampling clock that the FPGA module provides.The clock input circuit of analog-to-digital conversion module as shown in Figure 2, the system sampling clock that the FPGA module provides is imported by the SMA interface, through importing the input end A1 that enters into high speed phase inverter 74VHC04 behind one 49 ohm build-out resistor R4 and the capacitance C3, after two-stage is reverse, obtain the sampling clock CLK of system.Potentiometer R1 and resistance R 2, R3 constitutes a bleeder circuit, and the direct current biasing that is input to 74VHC04 pin A1 is provided, and this DC voltage is used for adjusting the dutycycle of sampling clock CLK.
2),, the logical resource of fpga chip inside is configured, obtains FPGA inner structure module frame chart as shown in Figure 3 by logic development to fpga chip.
Comprise two digital dock administrative unit DCM1 and DCM2, the digital dock administrative unit manages distribution to the clock resource of FPGA, provides system needed most of clock resource.Wherein DCM1 output two-way clock CLK1 and CLK2, CLK1 is by the be divided into two write data clock of asynchronous data FIFO in the sampling clock that supplies the front end analog-to-digital conversion module respectively and the FPGA of FPGA clock internal impact damper; CLK2 also is divided into two respectively as the read data clock of asynchronous data FIFO and the main operation clock of DDR controller.Three road clock CLK3 of DCM2 output, CLK4 and CLK5 are respectively as major clock and the operating clock of peripheral control unit EPC and the clock of GPIO controller of PowerPC405 processor.
Because the sampling clock of analog-to-digital conversion module generally is not equal to the operating clock of DDR controller, the data of analog-to-digital conversion module output are asynchronous clock signals for the DDR controller.So the data of analog-to-digital conversion module output are undertaken by an asynchronous data FIFO earlier synchronously.The read-write clock frequency of asynchronous data FIFO is respectively the master clock frequency of DDR controller and the sampling clock frequency of modulus module.What data in buffer reached that some will trigger FIFO in data FIFO will expire signal, and this letter starts the enable signal of reading of FIFO, and exports data to the DDR controller.
Linking to each other with the data output end of FIFO according to input end of DDR controller number, when the data fifo output terminal had data output, the DDR controller was responsible in the DDR SDRAM storer of metadata cache to sheet.
With the PowerPC405 processor is core, comprises DCM2, the DDR controller, and GPIO controller and peripheral control unit EPC have made up embedded system on the sheet in FPGA.Peripheral control unit EPC is in charge of by the HPI interface mode and is connected to USB controller in this system; The signal input pin of GPIO controller is connected to the hardware reset pin of USB controller, is responsible for the hardware reset to USB controller HPI connected mode; The DDR controller is responsible for responding the rdma read order of PowerPC405, and outer buffer memory DDR SDRAM carries out read operation to sheet; DCM2 is responsible for the clock distribution of this embedded system.Program flow diagram on the PowerPC405 as shown in Figure 5.PowerPC405 writes control word toward the register of GPIO controller, and the GPIO responsing control command at the reseting controling signal of corresponding output pin output USB chip, is finished the hardware reset of the HPI connected mode of USB controller; After this PowerPC405 reads in the configuration file of USB firmware, and by the HPI interface USB firmware downloads in the internal memory, is finished the download of USB firmware in the USB sheet; Next PowerPC405 sends USB warm reset order and program skip command in succession by the HPI interface, and the USB firmware brings into operation; PowerPC405 enters and fills the USB transmission data structure stage after this, constantly with the data transmission in the cache module in the USB ram in slice.
3), the transmission command of the mainly responsible response main frame of USB module is finished the transformation task of data to main frame.Because the hardware reset of USB and the work such as download of firmware are finished by the FPGA module, the just only remaining response main frame transmission command of the task of USB module, the program flow diagram of USB interface is as shown in Figure 4.Wherein the usb data frame structure is the fixing data structure that the USB chip factory decides through consultation justice, the content of its data division is filled by the data buffer area in " initialization data buffer area " in the process flow diagram, this metadata cache is a block data structure that is defined in the program in the USB sheet, share by USB controller and PowerPC405, PowerPC405 mainly carries out write operation to this data structure, the data that constantly will be temporarily stored in the outer cache module of sheet write this data structure, the USB controller reads the content of this data structure, and sends it to main frame.In order effectively to control the operation of PowerPC405 and USB chip to this data structure, in this data structure, defined a control bit control, test and set operation TAS have been introduced, PowerPC405 and USB chip are carried out corresponding read-write operation according to the state of control, and the value of control is made amendment.TAS to the control position operates as shown in Figure 6.
Claims (5)
1, based on the high-speed data acquisition and the transmission method of FPGA and usb bus, it is characterized in that carrying out data acquisition and transmission to upper PC computing machine on the basis of totally four modules at analog-to-digital conversion module, FPGA module, cache module and USB transport module:
1) analog-to-digital conversion module realizes that the conversion of signals to be collected that will import is the function of digital signal, analog-to-digital conversion module accepts the simulating signal to be collected of outside input and from the sampling clock input signal of FPGA module, the digital signal data after analog-to-digital conversion module will be changed is exported to the FPGA mould;
2) the FPGA module is finished the task of described digital signal data being cached to the outer DDR SDRAM of sheet, and by making up on the sheet that processor with the FPGA module is a core embedded system and the work of USB module cooperative data is transferred on the PC; The FPGA module is accepted the digital signal data from analog-to-digital conversion module, by the built-in asynchronous data FIFO of FPGA and DDR controller with metadata cache in cache module, cache module is the outer DDR SDRAM storer of sheet,
3) cache module is used for the digital signal data of buffer memory analog-to-digital conversion module output; Cache module is the table tennis storage organization that the DDR SDRAM storer by two 32MB constitutes, and the DDR controller of FPGA inside modules partly is responsible for the read-write operation to this memory device, and digital signal data is temporary in cache module; After the data of table tennis storage organization monolithic memory were filled with in the cache module, the processor that triggers the FPGA module was that the program of embedded system controller is transferred to data in the cache module in the internal RAM of USB controller on the sheet of core;
4) digital signal data that is stored in the most at last in the cache module of USB transport module is transferred to PC: the USB transmission command that USB transport module response main frame sends, with the processor collaborative work of FPGA module, with the data transmission that collects to main frame.
2, based on the high-speed data acquisition and the transmission system of FPGA and usb bus, system is by analog-to-digital conversion module, the FPGA module, and cache module and USB transport module totally four modules are formed; Digital dock administrative unit DCM in the FPGA module connects the controlling of sampling end of analog-to-digital conversion module, and analog-to-digital conversion module output connects the asynchronous data mouth FIFO of FPGA, and the DDR controller of FPGA connects the output of cache module; By the DCM1 in the FPGA module 2, asynchronous data FIFO, DDR controller and cache module 3 are finished data acquisition; GPIO controller 7 connects the hardware reset end of USB transport module 4; By the DCM2 in the FPGA module 2, GPIO controller 7, embedded system and USB transport module 4 are finished data-transformation facility jointly on the sheet that peripheral control unit EPC, PowerPC405 processor 11, DDR controller 12 constitute.Most of hardware circuit that plays control, booster action is realized by the programming in logic to the FPGA module in the system.The sampling clock of analog-to-digital conversion module 1 is provided by the DCM1 of FPGA module, and the sampling clock that the FPGA module provides is input to the input end of clock of ADC through the clock input circuit 5 in the analog-to-digital conversion module 1.The hardware reset of USB transport module 4, firmware downloads and program start are by embedded system on the sheet of the DCM2 in the FPGA module 2, GPIO controller 7, peripheral control unit EPC, PowerPC405, DDR controller formation.
Based on the high-speed data acquisition and the transmission system of FPGA and USB2.0 bus, comprise analog-to-digital conversion module (1), FPGA module (2), cache module (3), USB transport module (4), it is characterized in that:
1), data acquisition and caching function be by analog-to-digital conversion module (1), the DCM1 (8) in the FPGA module (2), and asynchronous data FIFO (9), DDR controller (12) and cache module (3) are finished jointly.
2), data-transformation facility is by the DCM2 (6) in the FPGA module (2), GPIO controller (7), and embedded system and USB transport module (4) are finished jointly on the sheet that peripheral control unit EPC (10), PowerPC405 processor (11), DDR controller (12) constitute.
3, high-speed data acquisition and transmission system based on FPGA and USB2.0 bus according to claim 1 is characterized in that: most of hardware circuit that plays control, booster action is realized by the programming in logic to FPGA module (2) in the system.
4, high-speed data acquisition and transmission system based on FPGA and USB2.0 bus according to claim 1, it is characterized in that: the sampling clock of analog-to-digital conversion module (1) is provided by the DCM1 (8) of FPGA module (2), and the sampling clock that FPGA module (2) provides is input to the input end of clock of ADC through the clock input circuit (5) in the analog-to-digital conversion module (1).
5, high-speed data acquisition and transmission system based on FPGA and USB2.0 bus according to claim 1 is characterized in that: hardware reset, firmware downloads and the program start of USB transport module (4) finished by embedded system on the sheet of the DCM2 (6) in the FPGA module (2), GPIO controller (7), peripheral control unit EPC (10), PowerPC405 (11), DDR controller (12) formation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008101565899A CN101408902A (en) | 2008-10-06 | 2008-10-06 | Method for acquiring and transporting high speed data based on FPGA and USB bus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008101565899A CN101408902A (en) | 2008-10-06 | 2008-10-06 | Method for acquiring and transporting high speed data based on FPGA and USB bus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101408902A true CN101408902A (en) | 2009-04-15 |
Family
ID=40571914
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2008101565899A Pending CN101408902A (en) | 2008-10-06 | 2008-10-06 | Method for acquiring and transporting high speed data based on FPGA and USB bus |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101408902A (en) |
Cited By (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101650702A (en) * | 2009-07-10 | 2010-02-17 | 北京巨数数字技术开发有限公司 | On-line USB communication maintenance device and method |
| CN102253915A (en) * | 2011-06-16 | 2011-11-23 | 中国科学院自动化研究所 | Data acquisition and playback system |
| CN102253916A (en) * | 2010-05-21 | 2011-11-23 | 淮阴工学院 | Double-end double-channel first in first out (FIFO) for synchronous-to-asynchronous conversion |
| CN101770424B (en) * | 2010-01-05 | 2011-11-30 | 天津七一二通信广播有限公司 | Data acquisition and emulation system suitable for underlying protocol stack of digital communication terminal |
| CN102354392A (en) * | 2011-06-08 | 2012-02-15 | 无锡引速得信息科技有限公司 | Parallel accelerating apparatus used in industrial computerized tomography (CT) image reconstruction |
| CN102439534A (en) * | 2011-10-25 | 2012-05-02 | 华为技术有限公司 | Method for reducing data chip plug-in ddr power dissipation and data chip system |
| CN102522113A (en) * | 2011-09-28 | 2012-06-27 | 华为技术有限公司 | SDRAM bridge circuit |
| CN101707629B (en) * | 2009-11-13 | 2012-11-14 | 国网电力科学研究院 | Synchronous communication method of mirror images for self organization information of safety and stability control device of electric network |
| CN102854375A (en) * | 2012-09-07 | 2013-01-02 | 哈尔滨工业大学 | High-speed voltage and current analog quantity acquisition system based on FPGA (field programmable gate array) |
| CN102930064A (en) * | 2012-09-20 | 2013-02-13 | 苏州生物医学工程技术研究所 | Data acquisition system and data acquisition method of system based on USB (universal serial bus) |
| CN103353725A (en) * | 2013-03-19 | 2013-10-16 | 中国科学院声学研究所 | PCI interface protocol based array expandable data collection system realized by adopting FPGA (field programmable gate array) |
| CN103455452A (en) * | 2012-06-04 | 2013-12-18 | 广州众诺电子科技有限公司 | Method, device and system for USB (universal serial bus) data acquisition |
| CN104361143A (en) * | 2014-11-28 | 2015-02-18 | 成都龙腾中远信息技术有限公司 | Portable data acquisition card and method thereof |
| CN104485962A (en) * | 2014-11-28 | 2015-04-01 | 成都龙腾中远信息技术有限公司 | Portable data acquisition system and acquisition method thereof |
| CN104535835A (en) * | 2014-12-09 | 2015-04-22 | 重庆西南集成电路设计有限责任公司 | Double-channel PCI data acquisition card and method |
| CN105718219A (en) * | 2016-01-19 | 2016-06-29 | 浙江大学 | Method and module for high-speed data transmission and storage based on USB3.0 |
| CN106470017A (en) * | 2015-08-20 | 2017-03-01 | 深圳市中兴微电子技术有限公司 | A kind of pre-distortion coefficients treating method and apparatus |
| CN106569743A (en) * | 2016-10-20 | 2017-04-19 | 北方电子研究院安徽有限公司 | Miniature programmable acquisition, control and storage device |
| CN106681944A (en) * | 2016-11-25 | 2017-05-17 | 南京美乐威电子科技有限公司 | FX3-FPGA (field programmable gate array) rapid starting method and FX3-FPGA rapid starting system based on single SPI (serial peripheral interface) flash memory |
| CN108206835A (en) * | 2016-12-16 | 2018-06-26 | 株洲中车时代电气股份有限公司 | A kind of comprehensive data acquisition device and its data consistency checking test method |
| CN108664428A (en) * | 2017-12-18 | 2018-10-16 | 深圳市鼎阳科技有限公司 | A kind of communication means and FPGA controller and USB adapter based on FPGA |
| CN111444131A (en) * | 2020-03-23 | 2020-07-24 | 电子科技大学 | Data acquisition and transmission device based on USB3.0 |
| CN114442048A (en) * | 2021-12-23 | 2022-05-06 | 西安电子科技大学 | FPGA implementation method for EPC-MIMO radar receiving signal processing |
| CN115080491A (en) * | 2022-06-22 | 2022-09-20 | 无锡华普微电子有限公司 | PCI bus data acquisition system based on FPGA |
-
2008
- 2008-10-06 CN CNA2008101565899A patent/CN101408902A/en active Pending
Cited By (35)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101650702B (en) * | 2009-07-10 | 2015-04-01 | 北京巨数数字技术开发有限公司 | On-line USB communication maintenance device and method |
| CN101650702A (en) * | 2009-07-10 | 2010-02-17 | 北京巨数数字技术开发有限公司 | On-line USB communication maintenance device and method |
| CN101707629B (en) * | 2009-11-13 | 2012-11-14 | 国网电力科学研究院 | Synchronous communication method of mirror images for self organization information of safety and stability control device of electric network |
| CN101770424B (en) * | 2010-01-05 | 2011-11-30 | 天津七一二通信广播有限公司 | Data acquisition and emulation system suitable for underlying protocol stack of digital communication terminal |
| CN102253916B (en) * | 2010-05-21 | 2013-09-18 | 淮阴工学院 | Double-end double-channel first in first out (FIFO) for synchronous-to-asynchronous conversion |
| CN102253916A (en) * | 2010-05-21 | 2011-11-23 | 淮阴工学院 | Double-end double-channel first in first out (FIFO) for synchronous-to-asynchronous conversion |
| CN102354392A (en) * | 2011-06-08 | 2012-02-15 | 无锡引速得信息科技有限公司 | Parallel accelerating apparatus used in industrial computerized tomography (CT) image reconstruction |
| CN102253915A (en) * | 2011-06-16 | 2011-11-23 | 中国科学院自动化研究所 | Data acquisition and playback system |
| CN102522113A (en) * | 2011-09-28 | 2012-06-27 | 华为技术有限公司 | SDRAM bridge circuit |
| CN102522113B (en) * | 2011-09-28 | 2014-09-17 | 华为技术有限公司 | SDRAM bridge circuit |
| WO2012163019A1 (en) * | 2011-10-25 | 2012-12-06 | 华为技术有限公司 | Method for reducing power consumption of externally connected ddr of data chip and data chip system |
| CN102439534A (en) * | 2011-10-25 | 2012-05-02 | 华为技术有限公司 | Method for reducing data chip plug-in ddr power dissipation and data chip system |
| CN103455452B (en) * | 2012-06-04 | 2016-08-10 | 广州众诺电子科技有限公司 | The method of a kind of usb data collection, Apparatus and system |
| CN103455452A (en) * | 2012-06-04 | 2013-12-18 | 广州众诺电子科技有限公司 | Method, device and system for USB (universal serial bus) data acquisition |
| CN102854375A (en) * | 2012-09-07 | 2013-01-02 | 哈尔滨工业大学 | High-speed voltage and current analog quantity acquisition system based on FPGA (field programmable gate array) |
| CN102930064A (en) * | 2012-09-20 | 2013-02-13 | 苏州生物医学工程技术研究所 | Data acquisition system and data acquisition method of system based on USB (universal serial bus) |
| CN103353725A (en) * | 2013-03-19 | 2013-10-16 | 中国科学院声学研究所 | PCI interface protocol based array expandable data collection system realized by adopting FPGA (field programmable gate array) |
| CN104361143A (en) * | 2014-11-28 | 2015-02-18 | 成都龙腾中远信息技术有限公司 | Portable data acquisition card and method thereof |
| CN104485962A (en) * | 2014-11-28 | 2015-04-01 | 成都龙腾中远信息技术有限公司 | Portable data acquisition system and acquisition method thereof |
| CN104485962B (en) * | 2014-11-28 | 2017-08-29 | 成都龙腾中远信息技术有限公司 | A kind of Portable Data-Acquisition System and its acquisition method |
| CN104361143B (en) * | 2014-11-28 | 2018-06-05 | 成都龙腾中远信息技术有限公司 | A kind of portable data acquisition card and its method |
| CN104535835A (en) * | 2014-12-09 | 2015-04-22 | 重庆西南集成电路设计有限责任公司 | Double-channel PCI data acquisition card and method |
| CN106470017A (en) * | 2015-08-20 | 2017-03-01 | 深圳市中兴微电子技术有限公司 | A kind of pre-distortion coefficients treating method and apparatus |
| CN106470017B (en) * | 2015-08-20 | 2020-04-03 | 深圳市中兴微电子技术有限公司 | Predistortion coefficient processing method and device |
| CN105718219A (en) * | 2016-01-19 | 2016-06-29 | 浙江大学 | Method and module for high-speed data transmission and storage based on USB3.0 |
| CN105718219B (en) * | 2016-01-19 | 2018-12-04 | 浙江大学 | The method and module of high speed data transfer storage based on USB3.0 |
| CN106569743A (en) * | 2016-10-20 | 2017-04-19 | 北方电子研究院安徽有限公司 | Miniature programmable acquisition, control and storage device |
| CN106681944A (en) * | 2016-11-25 | 2017-05-17 | 南京美乐威电子科技有限公司 | FX3-FPGA (field programmable gate array) rapid starting method and FX3-FPGA rapid starting system based on single SPI (serial peripheral interface) flash memory |
| CN106681944B (en) * | 2016-11-25 | 2019-10-18 | 南京美乐威电子科技有限公司 | A kind of FX3-FPGA quick start method and system based on single SPI Flash |
| CN108206835A (en) * | 2016-12-16 | 2018-06-26 | 株洲中车时代电气股份有限公司 | A kind of comprehensive data acquisition device and its data consistency checking test method |
| CN108664428A (en) * | 2017-12-18 | 2018-10-16 | 深圳市鼎阳科技有限公司 | A kind of communication means and FPGA controller and USB adapter based on FPGA |
| CN108664428B (en) * | 2017-12-18 | 2020-05-05 | 深圳市鼎阳科技股份有限公司 | Communication method based on FPGA (field programmable Gate array), FPGA controller and USB (Universal Serial bus) adapter |
| CN111444131A (en) * | 2020-03-23 | 2020-07-24 | 电子科技大学 | Data acquisition and transmission device based on USB3.0 |
| CN114442048A (en) * | 2021-12-23 | 2022-05-06 | 西安电子科技大学 | FPGA implementation method for EPC-MIMO radar receiving signal processing |
| CN115080491A (en) * | 2022-06-22 | 2022-09-20 | 无锡华普微电子有限公司 | PCI bus data acquisition system based on FPGA |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101408902A (en) | Method for acquiring and transporting high speed data based on FPGA and USB bus | |
| CN111984562B (en) | Method for controlling burst access to register, electronic device and storage medium | |
| CN201130369Y (en) | Multichannel synchronous data capturing card based on VXI bus | |
| CN201418086Y (en) | Data communication protocol controller used for satellite-borne equipment | |
| CN101901202B (en) | Circuit for cross clock domain accessing of AHB bus equipment to APB bus equipment | |
| CN101236774B (en) | Device and method for single-port memory to realize the multi-port storage function | |
| CN111143264B (en) | APB bridge for realizing synchronous mode, APB bridge for realizing asynchronous mode and control method thereof | |
| CN114490460B (en) | FLASH controller for ASIC and control method thereof | |
| CN209842608U (en) | DDR3 memory control based on FPGA FIFO module | |
| CN201540469U (en) | Data acquiring device | |
| CN106354063A (en) | High-speed four-channel signal acquisition board | |
| CN107329929B (en) | Data transmission system and data transmission method based on SoC FPGA | |
| CN104485962B (en) | A kind of Portable Data-Acquisition System and its acquisition method | |
| CN116224270A (en) | Zynq-based near-sensing radar echo data and state information acquisition system | |
| CN112269754A (en) | LPC bus EMC extension device based on FPGA | |
| CN204886928U (en) | Small time interval data acquisition device based on PCIE bus | |
| CN104281082A (en) | Partial discharge signal collecting method and system | |
| CN101998135A (en) | System for collecting and playing mobile television signal and control method | |
| CN107727930A (en) | Intelligent high-precision analog signal sampling system and the method for sampling | |
| CN207586908U (en) | A kind of high speed dilatation memory module | |
| CN103226531A (en) | Dual-port peripheral configuration interface circuit | |
| CN215376139U (en) | Efficient data acquisition system based on ARM and FPGA | |
| CN100561590C (en) | A kind of method and system of reading data in EMS memory | |
| CN111953333B (en) | SPI parallel data acquisition circuit and sensing system of array MEMS sensor | |
| CN115050405A (en) | Read-write control circuit, control method, chip and electronic equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Open date: 20090415 |