CN108664428A - A kind of communication means and FPGA controller and USB adapter based on FPGA - Google Patents
A kind of communication means and FPGA controller and USB adapter based on FPGA Download PDFInfo
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- CN108664428A CN108664428A CN201711367607.3A CN201711367607A CN108664428A CN 108664428 A CN108664428 A CN 108664428A CN 201711367607 A CN201711367607 A CN 201711367607A CN 108664428 A CN108664428 A CN 108664428A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0042—Universal serial bus [USB]
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Abstract
A kind of communication means and FPGA controller and USB adapter based on FPGA.The communication means includes acquisition, parsing, judgement, transmission and the encapsulation of answer data of load data, passback step, and the communication process of driving layer USB can be implemented separately.FPGA controller compatible with the communication means includes fifo module, data transmit-receive module and state machine module, communication process using the various data of fifo module is not in that data overstock phenomenon, data transmit-receive module enhances the transmittability of data, and adoption status machine module to realize harmonious data handling procedure between FIFO and data transmit-receive module.The USB adapter includes USB controller and FPGA controller, realizes the communication mode between another USB master-slave equipments using the USB adapter, goes back the integrated circuit structure of reducing adaptor, reduce the use cost of adapter.
Description
Technical field
The present invention relates to fields of communication technology, and in particular to a kind of communication means and FPGA controller based on FPGA and
USB adapter.
Background technology
USB (Universal Serial Bus, universal serial bus) is a kind of general serial transfer bus agreement, tool
Have the advantages that data transmission efficiency is high, easy to use, USB standard interface has become most popular in active computer equipment
One of interface.The communication protocol of USB 2.0 and USB 3.0 have obtained public acceptance, and are obtained extensively in electronic technology field
Using.
It is usually responded from equipment using main equipment initiation between the equipment communicated due to use USB communication protocol
Mode completes information exchange, so, the USB device being related to generally is divided into master/slave arrangement, wherein USB main equipment refers to having
The equipment such as host computer, PC, the server of usb communication function, USB refer to the USB flash disk with usb communication function, mouse, beat from equipment
The equipment such as print machine.To realize communication function of the USB main equipment with USB from equipment, need to match main equipment and between equipment
Communication response speed often uses communication adapter to coordinate USB master to make to reach the net synchronization capability of communication data transmitting-receiving between the two
From the communication process of equipment room, the bottom association of existing communication adapter generally use communications chip centralized processing usb communication
It negotiates peace and drives layer protocol.Since such communication chip needs the job requirement of competent big data, quick response, to the mistake of its performance
It is require so that the peripheral circuit of such communication chip is complicated and so that communication adaptation application cost is higher more.
Invention content
The present invention solves the technical problem of how by usb communication function between FPGA realization master-slave equipments.For
Solve the above problems, the present invention provides a kind of solution based on FPGA, i.e., a kind of communication means based on FPGA and
FPGA controller and USB adapter.
A kind of communication means based on FPGA controller, includes the following steps：FPGA obtains load by its fifo module
Data, the load data include protocol headers and read-write data, and the protocol headers include write order or query command；
FPGA parses the load data by its data transmit-receive module；FPGA judges the order of the protocol headers by its state machine
Type, if it is write order, then by the transmission of its data transmit-receive module, reading writes data to external communication device to FPGA accordingly, such as
Fruit is query command, then FPGA sends corresponding reading by its data transmit-receive module and writes data to external communication device and reception
The answer data that the external communication device returns.
The communication means that above-described embodiment provides uses USB associative processor systems, and driving layer is individually completed using FPGA
Usb communication process so that reading, parsing and the transmission process of operational order and related communication data are closely incorporated in one
It rises, the phenomenon that bottom usb communication process influences each other with driving layer usb communication process is effectively prevented, to speed data
Load is from USB main equipment to USB from the processing speed between equipment.
A kind of FPGA controller for communication, including：Fifo module, data transmit-receive module and state machine module.It is described
Fifo module connects USB main equipment for signal, and the fifo module is for caching load data；The data transmit-receive module is used for
USB is communicated to connect from equipment, for parsing load data and sending the read-write data in load data；The state machine module is used
In the communication process for controlling the fifo module and the data transmit-receive module.External communication device is to the data transmit-receive module
When returning to answer data, the data transmit-receive module is for receiving and encapsulating the answer data.
The FPGA controller that above-described embodiment provides uses fifo module, and charge number is cached in the form of data are temporary
According to so that communication process is not in that data are overstock, or even communicate the phenomenon that stagnating.In addition, the FPGA controller uses number
According to transceiver module, parsing or the encapsulation work of data are individually handled, is conducive to and fifo module is the same as time-triggered protocol load data.This
Outside, state machine module does not undertake the processing work of data, is only used for coordination data communication process, so that fifo module sum number
The function of itself is can make full use of during handling data according to transceiver module, band was increased while carrying traffic rate
It is wide.
A kind of USB adapter for communication, including：USB controller and FPGA controller.Wherein, USB controller is used for
USB main equipment and FPGA controller are communicated to connect, for executing the communication of bottom usb protocol, the FPGA controller is for executing drive
Dynamic layer usb protocol communication.
Usb data communication process is divided into two stages by the USB adapter that above-described embodiment provides, and respectively drives layer
On the one hand usb communication and protocol layer usb communication have been coordinated the communication response speed between the master and slave equipment of USB, have on the other hand been carried
The high speed of service of hardware, to ensure that the data communication efficiency between the master and slave equipment of USB.Moreover, FPGA controller
Integrated level is high, application cost is low, is not only conducive to simplify the integrated circuit structure of USB adapter, is additionally favorable for reducing USB adapter
Use cost.
Description of the drawings
Fig. 1 is the structural schematic diagram of one FPGA controller of embodiment；
Fig. 2 is the structural schematic diagram of load data；
Fig. 3 is flow diagram of the embodiment two based on FPGA communication means；
Fig. 4 is the operation principle schematic diagram of three FPGA state machine modules of embodiment.
Specific implementation mode
Below by specific implementation mode combination attached drawing, invention is further described in detail.Wherein different embodiments
Middle similar component uses associated similar element numbers.In the following embodiments, many datail descriptions be in order to
The application is better understood.However, those skilled in the art can be without lifting an eyebrow recognize, which part feature
It is dispensed, or can be substituted by other elements, material, method in varied situations.In some cases, this Shen
Please it is relevant some operation there is no in the description show or describe, this is the core in order to avoid the application by mistake
More descriptions are flooded, and to those skilled in the art, these relevant operations, which are described in detail, not to be necessary, they
It can completely understand relevant operation according to the general technology knowledge of description and this field in specification.
It is formed respectively in addition, feature described in this description, operation or feature can combine in any suitable way
Kind embodiment.Meanwhile each step in method description or action can also can be aobvious and easy according to those skilled in the art institute
The mode carry out sequence exchange or adjustment seen.Therefore, the various sequences in the description and the appended drawings are intended merely to clearly describe a certain
A embodiment is not meant to be necessary sequence, and wherein some sequentially must comply with unless otherwise indicated.
It is herein component institute serialization number itself, such as " first ", " second " etc., is only used for distinguishing described object,
Without any sequence or art-recognized meanings.And " connection ", " connection " described in the application, unless otherwise instructed, include directly and
It is indirectly connected with (connection).
Usb protocol generally includes underlying protocol and driving layer protocol, wherein including data in Treated Base usb protocol
The treatment mechanisms such as identification, certification and the verification of (referring to usb communication data, i.e. load data) are wrapped, when processing drives layer usb protocol
The treatment mechanisms such as parsing, encapsulation and transmission including data packet.
Load data, is the data packet for referring to realize usb communication, which frequently includes usb protocol and assisted with USB
Corresponding read-write data are discussed, usb protocol is the Main Basiss for judging to read and write data format and type, and opposite with usb protocol
The read-write data answered are to judge the Main Basiss of Content of Communication.
FPGA, as a kind of programmable logic device, integrated level is high and logical resource is abundant, develops very just
Victory, also, since FPGA processing speeds are fast, there is original advantage in the realization of Digital Signal Processing or hardware algorithm.Such as
Fruit all realizes the process for handling usb protocol on FPGA, then more FPGA Resources on Chip can certainly will be occupied, is unfavorable for
Hardware-accelerated effects of the FPGA when handling digital signal.Therefore, use it is a kind of based on the communication means of FPGA individually to handle
Driving layer usb protocol is conducive to give full play to the Digital Signal Processing performance of FPGA.
Embodiment one, the FPGA controller for communication, as shown in Figure 1.
In the present embodiment, USB main equipment D1 and USB is from being connected with USB controller 101 and FPGA in turn between equipment D2
Controller 102, wherein connected by the way of usb communication between USB controller 101 and USB main equipment D1, FPGA controller
102 and USB between equipment D2 by the way of usb communication or I/O communication from being connected, USB controller 101 and FPGA controller
It is connected using bus between 102.
In the present embodiment, USB controller 101 and FPGA controller 102 constitute USB adapter, the former is for handling
Bottom usb protocol, the latter communicate to connect and cooperate, greatly strengthen for handling driving layer usb protocol between the two
Hardware-accelerated effect when usb communication.
In the present embodiment, USB controller 101 has the functional component of Treated Base usb protocol, which can be real
Now the identification of communication data, certification and checking treatment function are such as used to rationally determine the transmission form of the communication data
The communication standards such as USB2.0 agreements or USB3.0 agreements complete communication work.
In the present embodiment, FPGA controller 102 includes fifo module 1021, data transmit-receive module 1023 and state machine mould
Block 1022.1021 signal of fifo module is connected to USB main equipment (fifo module 1021 is connect with 101 bus of USB controller), should
Fifo module is for caching load data.Data transmit-receive module 1023 is communicatively coupled to USB from equipment D2, the data transmit-receive module
1023 for parse load data and send with the relevant read-write data of protocol headers, moreover, in the data transmit-receive module 1023
It is useful for the I/O control module of transceiving data.State machine module 1022 is connect by fifo interface with fifo module 1011, is led to
It crosses state machine interface to connect with data transmit-receive module 1023, which controls fifo module 1021 and data transmit-receive
Communication process between module 1023.
In the present embodiment, the load data often exists in the form of data packet, and there are some in the data packet
The data of specific meanings.See that Fig. 2, load data A1 include protocol headers A11 and read-write data A12, protocol headers A11 include two
(protocol headers of a load data only have a type by the operational order of type, write order A111 or query command A112
The operational order of type).Write order A111 is used to instruct the data writing process to USB from equipment, and therefore, the write order is corresponding
It is write-in content to read and write data A12.Query command A112 is used to instruct the passback process to USB from the answer result of equipment, because
This, the corresponding read-write data A12 of query command A112 are inquiry problem, and answer result corresponding with inquiry problem is to answer
Complex data.
Embodiment two, the communication means based on FPGA, as shown in Figure 3.
Initial in communication, USB main equipment D1 sends load data to USB controller 101, and USB controller 101 receives load
Checking treatment is carried out after lotus data to it, checking treatment includes the identification of data packet flag bit, the certification of bottom usb protocol and data packet
The load data of checking treatment is sent to fifo module 1021 by the processes such as completeness check, then, USB controller 101.
Hereafter, FPGA controller 102 will receive the load data and handle the data.
In the present embodiment, the communication means provided is the section communication mechanism between the master and slave equipment of USB, main to realize
The processing function for driving layer usb protocol, is explained in detail the communication means below in conjunction with Fig. 1, which includes
Following steps：
201, fifo module 1021 obtains load data.
In USB main equipment D1 and USB from equipment D2 in the communication starting stage, USB main equipment D1 is actively to USB from equipment D2
Load data is sent, to improve USB from equipment D2 to the response speed of load data, by FPGA controller 102 to the load
Data are obtained to carry out the processing of driving layer to it, obtain the process of the load data by FPGA controller 102
State machine module 1022 controls fifo module 1021 and completes.
202, data transmit-receive module 1023 parses load data and obtains protocol headers and read-write data.
State machine module 1022 reads load data in fifo module 1021 and the load data is sent to data transmit-receive
Module 1023, state machine module 1022 control data transmit-receive module 1023 and parse the load data and from wherein obtaining protocol headers
With read-write data.This protocol headers includes a kind of operational order, is write order or query command.The corresponding read-write number of write order
According to for content is written, the corresponding read-write data of query command are inquiry problem.
203, state machine module 1022 judges whether protocol headers include write order.
The mark character of protocol headers is identified and can be obtained by the corresponding operational order type of data load, the behaviour
It is write order or query command to make order.
204, if entering this step when protocol headers include write order, data transmit-receive module 1023 sends the read-write data
To external communication device.
State machine module 1022 controls data transmit-receive module 1023 and read-write data (content is written) is sent to external lead to
Believe that equipment, the external communication device are USB from equipment D2.
After the completion of step 204, the step of system is again introduced into 201 to 204.
205, if protocol headers enter this step when not including write order, data transmit-receive module 1023 sends the read-write number
According to external communication device.
State machine module 1022 controls data transmit-receive module 1023 and read-write data (inquiring problem) is sent to external lead to
Believe that equipment, the external communication device are USB from equipment D2.USB not only receives read-write data from equipment, will also be according to inquiry problem
Return to corresponding answer data.After the completion of step 205, system enters step 206.
In the present embodiment, due to there was only two kinds of command forms of write order and inquiry command in load data, association
It includes query command that the case where view head does not include write order, which is considered as protocol headers,.
206, data transmit-receive module 1023 receives and encapsulates answer data.
Data transmit-receive module 1023 is received from USB from the answer data of equipment D2, using the answer data as read-write number
It is combined according to protocol headers corresponding with query command, to form new load data, to complete to reply the encapsulation of data
Operation.
207, fifo module 1021 caches the answer data encapsulated.
Fifo module is written in load data (the answer data encapsulated) described in step 206 by state machine 1022
1021 to cache the load data.The purpose of the step is that fast transfer replies data and completes subsequent replies data
Encapsulation work.
208, fifo module 1021 sends the answer data encapsulated.
State machine 1022 controls fifo module 1021 and the load data of caching is sent to USB controller 101, USB controls
Device verifies the load data and is sent it to USB main equipment D1, to complete to reply the passback work of data.
In another embodiment, during one replies data completion passback work, step 205 to step 208 quilt
It being performed a plurality of times, i.e. USB main equipment D1 sends multigroup load data with query command to USB from equipment D2 in a short time,
At this point, FPGA controller 102 has the function of while handling multigroup load data.Under this situation, data transmit-receive module 1023
Multigroup load data is continuously received, these load datas are subjected to parsing and by the protocol headers of each load data according to excellent respectively
First grade sequence is latched one by one, is then sent each reading respectively and is write data to USB from equipment D2.Since USB is from equipment D2 processing
The time of each read-write data is different or each priority orders for replying data of return are different so that each return for replying data is suitable
Sequence does not follow the transmission sequence of each read-write data.At this point, the answer number that the meeting initiative recognition of data transmit-receive module 1023 has returned
According to Priority flag, matched protocol headers are obtained from latch units according to Priority flag, and then answer this
Complex data executes the operation of step 206.
Embodiment three, state machine module operational flow diagram, as shown in Figure 4.
Since state machine module 1022 is the control unit in FPGA controller 102, so, the present embodiment will be with state machine
The active control process of module 1022 is served as theme come the processing procedure that FPGA controller is described in detail to load data, including four
Processing step, respectively：
301, state machine module 1022 enters " free time " state.
The state is the original state of state machine module 1022, and state machine module 1022 can identify in fifo module 1021
State data memory, the identification method can be that active mode can also be passive mode.
In this state, state machine module 1022 enables its write operation by fifo module 1021 is controlled, to obtain at any time
Load data from USB controller 101.
302, state machine module 1022 enters " reading FIFO " state.
After fifo module 1021 is written into the load data from USB controller, state machine module 1022 judges
Fifo module 1021 is non-empty, at this point, state machine module 1022 enters " reading FIFO " state.Under this state, state machine module
1022 can read the load data in fifo module 1021 and the load data is sent to data transmit-receive module 1023.
In this step, it during load data is sent to data transmit-receive module 1023 by state machine module 1022, carries
Lotus data are existed in the form of data flow, and therefore, which will control data transmit-receive module 1023 from the number
Protocol headers and read-write data are obtained according to load data is parsed in stream, then, state machine module 1022 judges obtained agreement
Whether head includes write order or query command.
If protocol headers include write order, state machine module 1022 by fail fifo module 1021 write operation
(i.e. FIFO write operations are not enabled on), at this point, fifo module 1021 no longer receives data, the purpose of this operation is temporary close FIFO
The data buffer storage function of module 1021, the load data that priority processing has received ensure data processing speed, avoid receiving excessive
Data congestion phenomenon caused by load data.Later, state machine module 1022 will control data transmit-receive module 1023 and send solution
Obtained read-write data (content is written) are analysed to USB from equipment D2.
If protocol headers include query command, state machine module 1022 will by latch to the protocol headers into
Row is latched with to being operated from the answer data execute encapsulation of equipment from USB, and fifo module 1021 is kept to write enabled operation
With fast cache from USB from the answer data of equipment D2.Later, state machine module 1022 will control data transmit-receive module 1023
The obtained read-write data (inquiring problem) of parsing are sent to USB from equipment D2.
It is empty and has all sent load data to data transmit-receive when state machine module 1022 recognizes fifo module 1021
When module 1023, show it is processed at or completion load data will be handled, then state machine module 1022 will enter next
A state.Conversely, all not sending load data extremely for non-empty or when state machine module 1022 recognizes fifo module 1021
When data transmit-receive module 1023, show that also untreated complete load data, state machine module 1022 will continue into " reading FIFO " shape
State.
303, state machine module 1022 enters " waiting " state.
Since fifo module 1021 is empty and has all sent load data so that state machine module 1022 enters " waiting "
State.Under this state, state machine module 1022 judges the write operation state of fifo module 1021, if write operation fails, shows
USB enters step " free time " state in 301 from equipment D2 no reply data, then state machine module 1022.If fifo module
1021 write operation is enabled, shows that USB has answer data from equipment D2, then state machine module 1022 can wait for USB from equipment D2
Answer data, data transmit-receive module 1023 receive a reply data or reply time-out when, under state machine module 1022 will enter
One state.
304, state machine module 1022 enters " writing FIFO " state.
Under this state, state machine module 1022 controls data transmit-receive module 1023 and receives the answer that USB is returned from equipment D2
Data (the answer data are empty in the case where replying time-out), and by the answer data and the protocol headers (association latched
View head is handled, is adapted to reply the protocol form of data) it combines and is encapsulated as new load data.Then, state
Fifo module 1021 is written in the load data encapsulated by machine module 1022, which, which is written in fifo module 1021, has
Conducive to the resource of quick release data transmit-receive module 1023.Hereafter, state machine module 1022 is sent fifo module 1021 is controlled
The new load data is to USB controller 101.
It is empty and has all sent load data to USB controller 101 when state machine module 1022 recognizes fifo module
When, " free time " state which will enter step in 301.Conversely, when state machine module 1022 recognizes
Fifo module be non-empty or all send load data to USB controller 101 when, the state machine module 1022 will continue into
Enter " writing FIFO " state.
It in the present embodiment, can be to the load after USB controller 101 receives the load data from fifo module 1021
Data carry out checking treatment, and checked load data is then sent to USB main equipment D1.
Use above specific case is illustrated the present invention, is merely used to help understand the present invention, not limiting
The system present invention.For those skilled in the art, according to the thought of the present invention, can also make several simple
It deduces, deform or replaces.
Claims (7)
1. a kind of communication means based on FPGA, which is characterized in that include the following steps：
FPGA obtains load data by its fifo module, and the load data includes protocol headers and read-write data, the association
It includes write order or query command to discuss head；
FPGA parses the load data by its data transmit-receive module；
FPGA judges the command type of the protocol headers by its state machine, and if it is write order, then FPGA passes through its data
Transceiver module send it is corresponding read to write data to external communication device, if it is query command, then FPGA passes through its data transmit-receive
Module sends the corresponding answer data for reading to write data to external communication device and receive the external communication device return.
2. a kind of communication means based on FPGA as described in claim 1, which is characterized in that when protocol headers include write order
When, the read-write data are write-in content；
When the protocol headers include query command, the read-write data are inquiry problem.
3. a kind of communication means based on FPGA as claimed in claim 2, which is characterized in that further include that the FPGA passbacks are answered
The step of complex data：
FPGA encapsulates the answer data by its data transmit-receive module；
The fifo module is written in the answer data encapsulated by the state machine of FPGA；
FPGA sends the answer data encapsulated by fifo module.
4. a kind of communication means based on FPGA as claimed in claim 3, which is characterized in that the data transmit-receive module encapsulation
Described the step of replying data includes the operation that protocol headers are added for the answer data.
5. a kind of FPGA controller for communication, which is characterized in that including fifo module, data transmit-receive module and state machine mould
Block；
The fifo module connects USB main equipment for signal, and the fifo module is for caching load data；
The data transmit-receive module is for communicating to connect USB from equipment, for parsing load data and sending in load data
Read and write data；
The state machine module is used to control the communication process of the fifo module and the data transmit-receive module.
6. a kind of FPGA controller for communication as claimed in claim 5, which is characterized in that external communication device is to described
When data transmit-receive module returns to answer data, the data transmit-receive module is additionally operable to receive and encapsulate the answer data.
7. a kind of USB adapter for communication, which is characterized in that including the FPGA controls described in USB controller and claim 5
Device processed；
The USB controller is for communicating to connect USB main equipment and the FPGA controller, for running bottom usb protocol；
The FPGA controller is for executing driving layer usb protocol.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711367607.3A CN108664428B (en) | 2017-12-18 | 2017-12-18 | Communication method based on FPGA (field programmable Gate array), FPGA controller and USB (Universal Serial bus) adapter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711367607.3A CN108664428B (en) | 2017-12-18 | 2017-12-18 | Communication method based on FPGA (field programmable Gate array), FPGA controller and USB (Universal Serial bus) adapter |
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| Publication Number | Publication Date |
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| CN108664428A true CN108664428A (en) | 2018-10-16 |
| CN108664428B CN108664428B (en) | 2020-05-05 |
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| CN101419582A (en) * | 2008-12-10 | 2009-04-29 | 北京交通大学 | MVB/USB adapter based on SOPC technology and communication method thereof |
| CN104765321A (en) * | 2015-01-22 | 2015-07-08 | 镇江同舟螺旋桨有限公司 | Motion controller being compatible with various field bus protocols |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101009781A (en) * | 2006-01-24 | 2007-08-01 | 深圳清华大学研究院 | A multifunctional receiving box and mobile receiving method of USB interface digital TV |
| CN101408902A (en) * | 2008-10-06 | 2009-04-15 | 南京大学 | Method for acquiring and transporting high speed data based on FPGA and USB bus |
| CN101419582A (en) * | 2008-12-10 | 2009-04-29 | 北京交通大学 | MVB/USB adapter based on SOPC technology and communication method thereof |
| CN104765321A (en) * | 2015-01-22 | 2015-07-08 | 镇江同舟螺旋桨有限公司 | Motion controller being compatible with various field bus protocols |
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| CN108664428B (en) | 2020-05-05 |
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