CN115050405A - Read-write control circuit, control method, chip and electronic equipment - Google Patents
Read-write control circuit, control method, chip and electronic equipment Download PDFInfo
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- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
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Abstract
The application provides a read-write control circuit, a control method, a chip and electronic equipment, and belongs to the technical field of electronics. The read-write control circuit comprises a cache module; the read-write control circuitry is configured to: when continuous read-write operation exists, executing the read operation, and storing data corresponding to the write operation in the cache module; and writing the data corresponding to the write operation into a memory from the cache module. By the method and the device, system access efficiency can be improved.
Description
Technical Field
The present disclosure relates to the field of electronic technologies, and in particular, to a read/write control circuit, a control method, a chip, and an electronic device.
Background
An AHB (Advanced High performance Bus) may trigger an Access to an SRAM (Static Random-Access Memory) by initiating a read operation or a write operation.
When the AHB bus accesses the SRAM, if a read operation is performed immediately after a write operation, the read operation may wait due to the time required for the SRAM write, and the system access efficiency may be affected.
Disclosure of Invention
In order to solve the problems in the prior art, embodiments of the present application provide a read/write control circuit, a control method, a chip, and an electronic device, which can improve system access efficiency. The technical scheme is as follows:
according to an aspect of the present application, there is provided a read-write control circuit, including a cache module;
the read-write control circuitry is configured to:
when continuous read-write operation exists, executing the read operation, and storing data corresponding to the write operation in the cache module;
and writing the data corresponding to the write operation into a memory from the cache module.
Optionally, the cache module includes a first-level write cache unit and a second-level write cache unit;
the read-write control circuitry is configured to:
when write operation exists, storing data corresponding to the write operation in the first-level write cache unit;
and if the read operation to be executed does not exist currently, executing the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit.
Optionally, the read-write control circuit is configured to:
receiving a first operation instruction, and if the first operation instruction is determined to be write operation, executing the first operation instruction and storing data corresponding to the first operation instruction in the first-level write cache unit;
receiving a second operation instruction, determining that the second operation instruction is read operation, if the first operation instruction is in an execution state, suspending the first operation instruction, executing the second operation instruction to acquire data required by the second operation instruction and writing back the data;
after the second operation instruction is executed, if no read operation to be executed exists currently, executing the suspended first operation instruction, and executing an operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit.
Optionally, the read-write control circuit is configured to:
receiving a third operation instruction, and if the third operation instruction is determined to be read operation, executing the third operation instruction to acquire data required by the third operation instruction and writing back the data;
receiving a fourth operation instruction, determining that the fourth operation instruction is write operation, and after the third operation instruction is executed, executing the fourth operation instruction and storing data corresponding to the fourth operation instruction in the first-level write cache unit;
and if the read operation to be executed does not exist currently, executing the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit.
Optionally, the read-write control circuit is further configured to:
receiving a fifth operation instruction, and if the fifth operation instruction is determined to be write operation, executing the fifth operation instruction and storing data corresponding to the fifth operation instruction in the first-level write cache unit;
and if the read operation to be executed does not exist currently, executing the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit.
Optionally, the read-write control circuit is further configured to:
when the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit is executed, taking the data currently stored in the first-level write cache unit as first data, and if the second-level write cache unit currently stores second data, judging whether a write address corresponding to the first data and a write address corresponding to the second data meet an adjacent condition, wherein the adjacent condition refers to that storage positions in the memory are adjacent;
if the adjacent condition is met, writing the first data and the second data into the memory;
and if the adjacent condition is not met, writing the second data into the memory, and writing the first data into the second-level write cache unit.
Optionally, the read-write control circuit is further configured to:
and when the bus is idle, writing the data currently stored in the cache module into the memory.
Optionally, the read-write control circuit is configured to:
when data required by read operation exists in the cache module, acquiring the required data from the cache module;
and when the data required by the read operation does not exist in the cache module, reading the required data from the memory.
Optionally, the cache module includes a first-level write cache unit and a second-level write cache unit;
the read-write control circuitry is configured to:
for the first level write cache unit: judging whether a read address corresponding to the current read operation is the same as a write address corresponding to the data of the first-level write cache unit, and if so, acquiring the data of the current read operation from the first-level write cache unit; if not, the following judgment on the second-level write cache unit is carried out;
for the second level write cache unit: and judging whether the read address corresponding to the current read operation is the same as the write address corresponding to the data of the second-level write cache unit, and if so, acquiring the data of the current read operation from the second-level write cache unit.
Optionally, the cache module further includes a read cache unit;
the read-write control circuitry is further configured to:
after judging whether the read address corresponding to the current read operation is the same as the address corresponding to the data of the second-level write cache unit, if not, entering the following judgment on the read cache unit;
for the read cache unit: judging whether a read address corresponding to the current read operation is the same as an address corresponding to the data of the read cache unit, and if so, acquiring the data of the current read operation from the read cache unit; and if not, reading the required data from the memory.
Optionally, the cache module further includes a read cache unit;
the read-write control circuitry is further configured to:
reading the data of the read address and the adjacent storage position thereof from the memory based on the read address corresponding to the current read operation;
and writing the data of the read address as the data required by the current read operation, and writing the data of the adjacent storage positions into the read cache unit.
Optionally, the cache module includes a first-level write cache unit, a second-level write cache unit, and a read cache unit, and the read-write control circuit further includes a first data selector, a second data selector, a third data selector, a fourth data selector, and a write data selection control circuit;
the input end of the first-level write cache unit is connected with a bus, and the output end of the first-level write cache unit is respectively connected with the input end of the first data selector and the input end of the second data selector;
the input end of the second-level write cache unit is connected with the output end of the first data selector, and the output end of the second-level write cache unit is respectively connected with the input end of the write data selection control circuit and the input end of the third data selector;
the input end of the read cache unit is connected with the memory, and the output end of the read cache unit is connected with the input end of the fourth data selector;
the input end of the first data selector is also connected with a bus, and the output end of the first data selector is also connected with the write data selection control circuit;
the input end of the second data selector is also connected with the output end of the third data selector, and the output end of the second data selector is connected with a bus;
the input end of the third data selector is also connected with the output end of the fourth data selector;
the input end of the fourth data selector is also connected with the memory;
the output end of the write data selection control circuit is also connected with the memory.
According to another aspect of the present application, there is provided a control method of a read-write control circuit, the read-write control circuit including a cache module;
the method comprises the following steps:
when continuous read-write operation exists, executing the read operation, and storing data corresponding to the write operation in the cache module;
and writing the data corresponding to the write operation into a memory from the cache module.
According to another aspect of the present application, a chip is provided, which includes the above-mentioned read-write control circuit.
According to another aspect of the present application, there is provided an electronic device including the above-described read-write control circuit.
According to the method and the device, when continuous read-write operation exists, the data of the write operation can be cached in the cache module, the data of the read operation is read preferentially, and then the data of the write operation is written into the memory, so that the waiting time of the read operation in the previous process of the write operation is eliminated, and the system access efficiency is improved.
Drawings
Further details, features and advantages of the present application are disclosed in the following description of exemplary embodiments, which is to be read in connection with the accompanying drawings, in which:
FIG. 1 illustrates a schematic diagram of a read-write control circuit provided in accordance with an exemplary embodiment of the present application;
FIG. 2 illustrates a cache module provided in accordance with an exemplary embodiment of the present application;
FIG. 3 illustrates a cache module provided in accordance with an exemplary embodiment of the present application;
FIG. 4 is a diagram illustrating a cache module provided in accordance with an illustrative embodiment of the present application;
FIG. 5 illustrates a read-write control circuit schematic provided in accordance with an exemplary embodiment of the present application;
FIG. 6 shows a system timing diagram when the read/write control circuit provided by the present application is not employed;
FIG. 7 is a timing diagram of a system employing the read/write control circuit provided herein;
FIG. 8 is a system timing diagram illustrating a read/write control circuit according to the present application;
FIG. 9 is a timing diagram of a system employing the read/write control circuit of the present application;
FIG. 10 is a flowchart illustrating a control method of the read/write control circuit according to an exemplary embodiment of the present application.
Detailed Description
Embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided for a more thorough and complete understanding of the present application. It should be understood that the drawings and embodiments of the present application are for illustration purposes only and are not intended to limit the scope of the present application.
The term "include" and variations thereof as used herein are open-ended, i.e., "including but not limited to". The term "based on" is "based, at least in part, on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Relevant definitions for other terms will be given in the following description. It should be noted that the terms "first", "second", and the like in the present application are only used for distinguishing different devices, modules or units, and are not used for limiting the order or interdependence relationship of the functions performed by the devices, modules or units.
It is noted that references to "a", "an", and "the" modifications in this application are intended to be illustrative rather than limiting, and that those skilled in the art will recognize that reference to "one or more" unless the context clearly dictates otherwise.
The names of messages or information exchanged between a plurality of devices in the embodiments of the present application are for illustrative purposes only, and are not intended to limit the scope of the messages or information.
The embodiment of the application provides a read-write control circuit, which can be integrated in a chip or arranged in an electronic device.
Referring to the schematic diagram of the read/write control circuit shown in fig. 1, the read/write control circuit may include a buffer module.
The read-write control circuitry may be configured to:
when continuous read-write operation exists, executing the read operation, and storing data corresponding to the write operation in a cache module;
and writing the data corresponding to the write operation into the memory from the cache module.
In one possible embodiment, the read-write control circuit may be provided between the bus and the memory, between which data is transferred. Specifically, the bus may be an AHB bus, and the memory may be an SRAM. As an example, the read/write control circuit can be applied in 32-bit MCU (micro controller Unit) design, where each address of SRAM stores 64 bits of data.
When the bus sends out continuous read-write operation, the read-write control circuit can execute the read operation first, read out the data required by the read operation, then execute the write operation, store the data corresponding to the write operation in the buffer module, and write the data of the write operation into the memory.
When continuous read-write operation exists, particularly continuous write + read operation exists, the waiting time of the read operation when the write operation is performed before is eliminated, and the system access efficiency is improved.
The write operation-related configuration of the read/write control circuit will be described below.
Referring to the schematic diagram of the cache module shown in fig. 2, the cache module may include a first-level write cache unit and a second-level write cache unit. As an example, the data stored by the first level write cache unit and the second level write cache unit may be 32 bits.
On this basis, the read-write control circuit may be configured to:
when write operation exists, storing data corresponding to the write operation in a first-level write cache unit;
and if the read operation to be executed does not exist currently, executing the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit.
In a possible implementation manner, whenever a write operation is issued by the bus, data corresponding to the write operation is first stored in the first-level write cache unit, and when the bus is in a next non-read address phase (i.e., there is no read operation to be performed), the data in the first-level write cache unit is written into the second-level write cache unit. That is, if the next clock cycle of the write address phase in the bus is the read address phase (i.e., triggering the read operation), the write operation is temporarily suspended, the SRAM is preferentially read, and when the bus has no read address phase, the suspended write operation is executed, i.e., written into the second-level write cache unit. As an example, referring to fig. 6, HWRITE is high and HADDR has an address phase indicating that the AHB bus issues a write operation, where the address phase is the write address phase; HWRITE is low and HADDR has an address phase indicating that the AHB bus issued a read operation, which is the read address phase.
Optionally, after the data in the first-level write cache unit is written into the second-level write cache unit, the first-level write cache unit may be emptied.
The respective cases of the trigger operation will be described separately below.
The first condition is as follows: and triggering continuous writing and reading operations, namely writing operation is performed before and reading operation is performed after.
In this case, the read-write control circuit may be configured to:
receiving a first operation instruction, and if the first operation instruction is determined to be write operation, executing the first operation instruction and storing data corresponding to the first operation instruction in a first-level write cache unit;
receiving a second operation instruction, determining that the second operation instruction is read operation, if the first operation instruction is in an execution state, suspending the first operation instruction, executing the second operation instruction to acquire data required by the second operation instruction and writing back the data;
and after the second operation instruction is executed, if the read operation to be executed does not exist currently, executing the suspended first operation instruction, and executing the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit.
In a possible implementation manner, in a first clock cycle, a first operation instruction corresponding to a write operation is triggered in the bus, and then the first operation instruction may be received and the type of the instruction is determined to be the write operation, and then the read-write control circuit may execute the write operation, and store data corresponding to the write operation in the first-level write cache unit. In the next second clock cycle, a second operation instruction corresponding to the read operation is triggered in the bus, the second operation instruction can be received, the type of the instruction is determined to be the write operation, and then the read-write control circuit can suspend the write operation, execute the read operation, acquire data required by the read operation and write back the data as the result of the second operation instruction. In the next third clock cycle, if another write operation is triggered in the bus or no operation is triggered, and there is no read address phase in the bus, the read-write control circuit may execute the suspended write operation, that is, execute the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit.
Furthermore, in the third clock cycle, if another read operation is triggered in the bus, the read operation still has a conflict with the suspended write operation for accessing the memory (i.e., the read operation has a wait time before the write operation), which still meets the first condition. At this time, the suspension of the write operation may be continuously maintained until there is no read operation to be executed in the bus, and then an operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit is executed.
Case two: and triggering continuous read + write operations, namely, a read operation is performed before and a write operation is performed after.
In this case, the read-write control circuit may be configured to:
receiving a third operation instruction, determining that the third operation instruction is read operation, executing the third operation instruction to acquire data required by the third operation instruction and writing back the data;
receiving a fourth operation instruction, determining that the fourth operation instruction is write operation, and after the third operation instruction is executed, executing the fourth operation instruction and storing data corresponding to the fourth operation instruction in a first-level write cache unit;
and if the read operation to be executed does not exist currently, executing the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit.
In a possible implementation manner, in a first clock cycle, a third operation instruction corresponding to a read operation is triggered in the bus, and then the third operation instruction may be received and the instruction type may be determined to be the read operation, and then the read-write control circuit may execute the read operation, acquire data required by the read operation, and write back the data as a result of the third operation instruction. In the next second clock cycle, a fourth operation instruction corresponding to the write operation is triggered in the bus, and the fourth operation instruction may be received, the type of the instruction is determined to be the write operation, and whether the read operation is completed or not may be determined. After the read operation is completed, the read-write control circuit may execute a write operation corresponding to the fourth operation instruction, and store data corresponding to the write operation in the first-level write cache unit. In the next third clock cycle, if another write operation is triggered in the bus or no operation is triggered, and there is no read address phase in the bus, the read-write control circuit may perform an operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit.
Similarly, in the third clock cycle, if another read operation is triggered in the bus, the read operation and the write operation corresponding to the fourth operation command have conflict of accessing the memory (i.e., the read operation has a waiting time before the write operation), which corresponds to the first clock cycle. At this time, the write operation may be suspended until there is no read operation to be executed in the bus, and then an operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit is executed.
Case three: triggering a sequential write + write operation or a separate write operation.
In this case, the read-write control circuit may be configured to:
receiving a fifth operation instruction, and if the fifth operation instruction is determined to be write operation, executing the fifth operation instruction and storing data corresponding to the fifth operation instruction in the first-level write cache unit;
and if the read operation to be executed does not exist currently, executing the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit.
In a possible implementation manner, in a first clock cycle, a fifth operation instruction corresponding to a write operation is triggered in the bus, and then the fifth operation instruction may be received and the instruction type is determined to be the write operation, so that the read-write control circuit may execute the write operation, and store data corresponding to the write operation in the first-level write cache unit. In the next second clock cycle, a sixth operation instruction corresponding to another write operation is triggered or no operation is triggered in the bus (i.e., there is no read operation to be executed), and the read-write control circuit may execute an operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit. After that, corresponding to the situation that the sixth operation instruction is received, the read-write control circuit may also clear the first-level write cache unit, and store the data corresponding to the write operation of the sixth operation instruction into the first-level write cache unit.
Optionally, the specific processing for executing the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit may be as follows:
taking the data currently stored in the first-level write cache unit as first data, and judging whether a second-level write cache unit stores second data or not;
if the second-level write cache unit currently stores the second data, judging whether the write address corresponding to the first data and the write address corresponding to the second data meet an adjacent condition, wherein the adjacent condition is that the storage positions in the memory are adjacent; if the adjacent conditions are met, writing the first data and the second data into a memory; if the adjacent conditions are not met, writing the second data into the memory, and writing the first data into the second-level write cache unit;
and if the second-level write cache unit does not currently store the second data, writing the data currently stored by the first-level write cache unit into the second-level write cache unit. At this time, the data stored in the second-level write cache unit may be used as second data when an operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit is performed next time.
As an example, the address of the AHB bus initiated read and write operation may be as 0xxxx _ XXX0, 0xxxx _ XXX4, 0xxxx _ XXX8, and 0xxxx _ XXXC, each address corresponding to 32 bits of data, where 0xxxx _ XXX0 and 0xxxx _ XXX4 are adjacent and 0xxxx _ XXX8 and 0xxxx _ XXXC are adjacent. Two adjacent addresses can be addressed to the same physical address in an SRAM (with a 64-bit width), and data of 64 bits in total corresponding to the two adjacent addresses is stored in the addressed same physical address, namely, the adjacent conditions are met.
When data needs to be written into the second-level write cache unit, whether the second-level write cache unit is full or not can be judged according to the empty and full mark of the cache. If the cache is full, the data cannot be written, and at this time, it may be determined whether the address of the current data to be written (i.e., the first data) and the address of the data already cached in the second-level write cache unit (i.e., the second data) satisfy the adjacency condition.
If yes, the corresponding position can be accessed by addressing once in the SRAM, and 64bit of data is written into the SRAM.
If the data is not satisfied, the 32-bit data buffered in the second-level write cache unit is written into the SRAM, the current to-be-written 32-bit data is written into the second-level write cache unit, and the data of another 32-bit adjacent to the second-level write cache unit is waited to be written into the SRAM together.
Through the configuration, the second-level write cache unit can be used for caching the data waiting for the adjacent addresses, and when the data of the two adjacent addresses are written in twice continuously, the data of the two addresses can be written in the memory at the same time, so that the times of accessing the memory are reduced, and the power consumption of the system is reduced.
Thereafter, data may be written to the memory while the bus is idle, and based thereon, the read-write control circuitry may be further configured to: and when the bus is idle, writing the data currently stored in the cache module into the memory. Optionally, after the data is written into the memory, the corresponding data in the cache module may be deleted, that is, the cache module is cleared.
Through the configuration, when continuous read-write operation exists, the data of the write operation can be cached in the cache module, the data of the read operation is read preferentially, and then the data of the write operation is written into the memory, so that the waiting time of the read operation in the prior process of the write operation is eliminated, and the system access efficiency is improved.
The read operation-related configuration of the read-write control circuit will be described below.
For read operations, the read-write control circuitry may be configured to:
when data required by read operation exists in the cache module, the required data is obtained from the cache module;
when the data required by the read operation does not exist in the cache module, the required data is read from the memory.
In one possible implementation, whether the data is required for the read operation may be determined based on the address of the read operation and the address of the data already buffered in the cache module. If the data with the same address as the read operation exists in the cache module, which indicates that the data is the data required by the read operation, the data can be obtained from the cache module as the result of the read operation and written back. If not, the memory may be accessed, the data required for the read operation read and written back.
Through the configuration, the times of accessing the memory can be reduced, and the system power consumption is reduced.
Optionally, when the cache module includes a first-level write cache unit and a second-level write cache unit, the read-write control circuit may be configured to:
for a first level write cache unit: judging whether a read address corresponding to the current read operation is the same as a write address corresponding to the data of the first-level write cache unit, and if so, acquiring the data of the current read operation from the first-level write cache unit; if not, the following judgment on the second-level write cache unit is carried out;
for a second level write cache unit: and judging whether the read address corresponding to the current read operation is the same as the write address corresponding to the data of the second-level write cache unit, and if so, acquiring the data of the current read operation from the second-level write cache unit.
That is, whether the first-level write cache unit and the second-level write cache unit store data required by a read operation may be sequentially determined, and if so, the data of the read operation is sourced from the corresponding write cache unit.
If the required data is not found in the second-level write cache unit, the required data can be read from the memory, or the searching is continued by adopting the technical scheme provided below.
In order to further reduce the power consumption of the system, similar to the above technical scheme of writing the data of the two adjacent addresses at the same time, the data of the two adjacent addresses can be read out at the same time through the cache module, and after the data required by the read operation is taken away, the data of the adjacent storage positions are written into the cache module. When judging whether the data required by the read operation exists in the cache module, whether the data required by the current read operation is read out at the same time by judging whether the previous read operation exists can be judged, so that whether the data is the required data can be judged.
On this basis, as an alternative, referring to the schematic diagram of the cache module shown in fig. 3, the cache module may further include a read cache unit, and the read cache unit may be configured to store the data of the adjacent storage locations. As an example, the data stored by the read cache unit may be 32 bits.
When the read cache unit is combined with the first-level write cache unit and the second-level write cache unit, as shown in fig. 4. On this basis, the read-write control circuit may be further configured to:
after judging whether the read address corresponding to the current read operation is the same as the address corresponding to the data of the second-level write cache unit, if not, entering the following judgment on the read cache unit;
for read cache units: judging whether a read address corresponding to the current read operation is the same as an address corresponding to the data of the read cache unit, and if so, acquiring the data of the current read operation from the read cache unit; if not, the required data is read from the memory.
That is, whether the first-level write cache unit, the second-level write cache unit, and the read cache unit store data required for a read operation may be sequentially determined, and if yes, the data for the read operation originates from the corresponding cache unit.
The processing of judging whether the read address corresponding to the current read operation is the same as the address corresponding to the data of the read cache unit may also be realized by judging whether the read address corresponding to the current read operation and the read address corresponding to the previous read operation meet the adjacent condition, and if so, it indicates that the read address corresponding to the current read operation is the same as the address corresponding to the data of the read cache unit.
Thereafter, if the desired data is not yet located, the desired data may be read from the memory.
When data needs to be read from the memory, the read-write control circuitry may be configured to:
reading the read address and the data of the adjacent storage position from the memory based on the read address corresponding to the current read operation;
and writing the data of the read address into the read cache unit after the data of the read address is written back as the data required by the current read operation.
As a specific example, referring to a schematic diagram of a read-write control circuit shown in fig. 5, the read-write control circuit may specifically include a first-level write cache unit, a second-level write cache unit, a read cache unit, a first data selector, a second data selector, a third data selector, a fourth data selector, and a write-data selection control circuit, where the first-level write cache unit, the second-level write cache unit, and the read cache unit may correspond to the cache module, and the configuration of the read-write control circuit may be implemented by the first data selector, the second data selector, the third data selector, the fourth data selector, and the write-data selection control circuit.
The input end of the first-level write cache unit can be connected with the AHB bus, and the output end of the first-level write cache unit is respectively connected with the first data selector and the second data selector.
The input end of the second-level write cache unit can be connected with the first data selector, and the output end of the second-level write cache unit is respectively connected with the write data selection control circuit and the third data selector.
The input end of the read cache unit can be connected with the SRAM, and the output end of the read cache unit is connected with the fourth data selector.
The input end of the first data selector can be respectively connected with the AHB bus and the first-level write cache unit, and the output end of the first data selector is respectively connected with the second-level write cache unit and the write data selection control circuit.
The input end of the second data selector can be respectively connected with the first-level write cache unit and the third data selector, and the output end of the second data selector is connected with the AHB bus.
The input end of the third data selector can be respectively connected with the second-level write cache unit and the fourth data selector, and the output end of the third data selector is connected with the second data selector.
The input end of the fourth data selector can be respectively connected with the SRAM and the read cache unit, and the output end of the fourth data selector is connected with the third data selector.
The input end of the write data selection control circuit can be respectively connected with the first data selector and the second-level write cache unit, and the output end of the write data selection control circuit is connected with the SRAM.
The embodiment of the application can obtain the following beneficial effects:
(1) when continuous read-write operation exists, the data of the write operation can be cached in the cache module, the data of the read operation is read preferentially, and then the data of the write operation is written into the memory, so that the waiting time of the read operation when the write operation is performed before is eliminated, and the system access efficiency is improved.
Fig. 6 shows a system timing diagram when the read/write control circuit provided in the present application is not used, where HWRITE is high and an address phase exists in HADDR, which indicates that the AHB bus issues a write operation, HWRITE is low and an address phase exists in HADDR, which indicates that the AHB bus issues a read operation, and in fig. 6, the write operation and the read operation are consecutive and the write operation is preceded. As can be seen from the timing diagram, the SRAM first triggers the write operation WR and then triggers the read operation RD, but since the SRAM write takes time, HREADYOUT is low when the read operation RD is triggered, indicating that the data is not ready to be read (indicated by the shaded portion in HRDATA), and the read operation delays reading the data one beat later (indicated by RDATA in HRDATA, which is not reading RDATA in the next beat of RD).
Fig. 7 shows a system timing diagram after the read/write control circuit provided by the present application is used, in which the SRAM first triggers the read operation RD and then triggers the write operation WR, and RDATA can be read out in the next beat of RD, thereby eliminating the time waiting for the write operation WR to write.
(2) When the data of the two adjacent addresses are written in twice continuously, the data of the two addresses can be written into the memory at the same time, and/or the data of the two adjacent addresses can be read out at the same time, and when the data of the two adjacent addresses are read in twice continuously, the data can be obtained from the buffer module, so that the number of times of accessing the memory is reduced, and the power consumption of the system is reduced.
Fig. 8 shows a system timing diagram when the read-write control circuit provided by the present application is not used, where addr0 and addr1 are two adjacent write addresses, and addr2 and addr3 are two adjacent read addresses, it can be seen that each AHB bus read-write triggers SRAM read-write (each WR corresponds to one write address, and each RD corresponds to one read address), and the system power consumption is high.
Fig. 9 shows a system timing diagram after the read-write control circuit provided by the present application is used, where it can be seen that 2 read/write operations of the AHB bus trigger only 1 read/write operation of the SRAM (addr0 and addr1 trigger a WR, addr2 and addr3 trigger an RD), thereby reducing system power consumption.
The embodiment of the application also provides a control method of the read-write control circuit, which can be used for controlling the read-write control circuit, and the read-write control circuit comprises a cache module. Referring to the flowchart of the control method of the read/write control circuit shown in fig. 10, the method may include the following steps 1001 and 1002:
1001, when continuous read-write operation exists, executing the read operation, and storing data corresponding to the write operation in the cache module;
step 1002, writing data corresponding to the write operation into a memory from the cache module.
Optionally, the cache module includes a first-level write cache unit and a second-level write cache unit;
the storing the data corresponding to the write operation in the cache module includes:
when the write operation exists, storing data corresponding to the write operation in the first-level write cache unit;
and if the read operation to be executed does not exist currently, executing the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit.
Optionally, when there is continuous read-write operation, executing the read operation, and storing data corresponding to the write operation in the cache module, including:
receiving a first operation instruction, and if the first operation instruction is determined to be write operation, executing the first operation instruction and storing data corresponding to the first operation instruction in the first-level write cache unit;
receiving a second operation instruction, determining that the second operation instruction is read operation, if the first operation instruction is in an execution state, suspending the first operation instruction, executing the second operation instruction to acquire data required by the second operation instruction and writing back the data;
after the second operation instruction is executed, if no read operation to be executed exists currently, executing the suspended first operation instruction, and executing an operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit.
Optionally, when there is continuous read-write operation, executing the read operation, and storing data corresponding to the write operation in the cache module, including:
receiving a third operation instruction, and if the third operation instruction is determined to be read operation, executing the third operation instruction to acquire data required by the third operation instruction and writing back the data;
receiving a fourth operation instruction, determining that the fourth operation instruction is write operation, and after the third operation instruction is executed, executing the fourth operation instruction and storing data corresponding to the fourth operation instruction in the first-level write cache unit;
and if the read operation to be executed does not exist currently, executing the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit.
Optionally, the method further includes:
receiving a fifth operation instruction, and if the fifth operation instruction is determined to be write operation, executing the fifth operation instruction and storing data corresponding to the fifth operation instruction in the first-level write cache unit;
and if the read operation to be executed does not exist currently, executing the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit.
Optionally, the executing the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit includes:
taking the data currently stored in the first-level write cache unit as first data, and if the second-level write cache unit currently stores second data, judging whether a write address corresponding to the first data and a write address corresponding to the second data meet an adjacent condition, wherein the adjacent condition refers to that storage positions in the memory are adjacent;
if the adjacent condition is met, writing the first data and the second data into the memory;
and if the adjacent condition is not met, writing the second data into the memory, and writing the first data into the second-level write cache unit.
Optionally, the method further includes:
and when the bus is idle, writing the data currently stored in the cache module into the memory.
Optionally, the performing a read operation includes:
when data required by read operation exists in the cache module, acquiring the required data from the cache module;
and when the data required by the read operation does not exist in the cache module, reading the required data from the memory.
Optionally, the cache module includes a first-level write cache unit and a second-level write cache unit;
when the data required by the read operation exists in the cache module, acquiring the required data from the cache module includes:
for the first level write cache unit: judging whether a read address corresponding to the current read operation is the same as a write address corresponding to the data of the first-level write cache unit, and if so, acquiring the data of the current read operation from the first-level write cache unit; if not, the following judgment on the second-level write cache unit is carried out;
for the second level write cache unit: and judging whether the read address corresponding to the current read operation is the same as the write address corresponding to the data of the second-level write cache unit, and if so, acquiring the data of the current read operation from the second-level write cache unit.
Optionally, the cache module further includes a read cache unit;
the method further comprises the following steps:
after judging whether the read address corresponding to the current read operation is the same as the address corresponding to the data of the second-level write cache unit, if not, entering the following judgment on the read cache unit;
for the read cache unit: judging whether a read address corresponding to the current read operation is the same as an address corresponding to the data of the read cache unit, and if so, acquiring the data of the current read operation from the read cache unit; and if not, reading the required data from the memory.
Optionally, the method further includes:
reading the data of the read address and the adjacent storage position thereof from the memory based on the read address corresponding to the current read operation;
and writing the data of the read address as the data required by the current read operation, and writing the data of the adjacent storage positions into the read cache unit.
In the embodiment of the application, when continuous read-write operation exists, the data of the write operation can be cached in the cache module, the data of the read operation is read preferentially, and then the data of the write operation is written into the memory, so that the waiting time of the read operation in the previous time of the write operation is eliminated, and the system access efficiency is improved.
The embodiment of the application also provides a chip which comprises the read-write control circuit provided by the embodiment of the application. The Chip may be, but is not limited to, an SOC (System on Chip) Chip or an SIP (System in package) Chip. The chip enables system access efficiency to be improved by configuring the read-write control circuit.
The embodiment of the application also provides electronic equipment, which comprises an equipment main body and the chip arranged in the equipment theme. The electronic device may be, but is not limited to, a weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a body composition analyzer, a mobile power supply, a wireless charger, a quick charger, a vehicle charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a stylus, a true wireless headset, a car center screen, a car, an intelligent wearable device, a mobile terminal, and an intelligent home device. The intelligent wearable device comprises but is not limited to an intelligent watch, an intelligent bracelet and a cervical vertebra massager. Mobile terminals include, but are not limited to, smart phones, laptops, tablets, point of sale (POS) machines. The intelligent household equipment comprises but is not limited to an intelligent socket, an intelligent electric cooker, an intelligent sweeper and an intelligent lamp. The electronic equipment improves the system access efficiency of the electronic equipment by configuring the read-write control circuit.
Although the present application has been described with reference to the preferred embodiments, it is to be understood that the present application is not limited to the disclosed embodiments, but rather, the present application is intended to cover various modifications, equivalents and alternatives falling within the spirit and scope of the present application.
Claims (15)
1. A read-write control circuit is characterized by comprising a cache module;
the read-write control circuitry is configured to:
when continuous read-write operation exists, executing the read operation, and storing data corresponding to the write operation in the cache module;
and writing the data corresponding to the write operation into a memory from the cache module.
2. The read-write control circuit of claim 1, wherein the cache module comprises a first level write cache unit and a second level write cache unit;
the read-write control circuitry is configured to:
when write operation exists, storing data corresponding to the write operation in the first-level write cache unit;
and if the read operation to be executed does not exist currently, executing the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit.
3. The read-write control circuit of claim 2, wherein the read-write control circuit is configured to:
receiving a first operation instruction, and if the first operation instruction is determined to be write operation, executing the first operation instruction and storing data corresponding to the first operation instruction in the first-level write cache unit;
receiving a second operation instruction, determining that the second operation instruction is read operation, if the first operation instruction is in an execution state, suspending the first operation instruction, executing the second operation instruction to acquire data required by the second operation instruction and writing back the data;
after the second operation instruction is executed, if no read operation to be executed exists currently, executing the suspended first operation instruction, and executing an operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit.
4. The read-write control circuit of claim 2, wherein the read-write control circuit is configured to:
receiving a third operation instruction, and if the third operation instruction is determined to be read operation, executing the third operation instruction to acquire data required by the third operation instruction and writing back the data;
receiving a fourth operation instruction, determining that the fourth operation instruction is write operation, and after the third operation instruction is executed, executing the fourth operation instruction and storing data corresponding to the fourth operation instruction in the first-level write cache unit;
and if the read operation to be executed does not exist currently, executing the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit.
5. The read-write control circuit of claim 2, further configured to:
receiving a fifth operation instruction, and if the fifth operation instruction is determined to be write operation, executing the fifth operation instruction and storing data corresponding to the fifth operation instruction in the first-level write cache unit;
and if the read operation to be executed does not exist currently, executing the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit.
6. The read-write control circuit of any of claims 2-5, further configured to:
when the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit is executed, taking the data currently stored in the first-level write cache unit as first data, and if the second-level write cache unit currently stores second data, judging whether a write address corresponding to the first data and a write address corresponding to the second data meet an adjacent condition, wherein the adjacent condition refers to that storage positions in the memory are adjacent;
if the adjacent condition is met, writing the first data and the second data into the memory;
and if the adjacent condition is not met, writing the second data into the memory, and writing the first data into the second-level write cache unit.
7. The read-write control circuit of claim 1, further configured to:
and when the bus is idle, writing the data currently stored in the cache module into the memory.
8. The read-write control circuit of claim 1, wherein the read-write control circuit is configured to:
when data required by read operation exists in the cache module, acquiring the required data from the cache module;
and when the data required by the read operation does not exist in the cache module, reading the required data from the memory.
9. The read-write control circuit of claim 8, wherein the cache module comprises a first level write cache unit and a second level write cache unit;
the read-write control circuitry is configured to:
for the first level write cache unit: judging whether a read address corresponding to the current read operation is the same as a write address corresponding to the data of the first-level write cache unit, and if so, acquiring the data of the current read operation from the first-level write cache unit; if not, the following judgment on the second-level write cache unit is carried out;
for the second level write cache unit: and judging whether the read address corresponding to the current read operation is the same as the write address corresponding to the data of the second-level write cache unit, and if so, acquiring the data of the current read operation from the second-level write cache unit.
10. The read-write control circuit of claim 9, wherein the buffer module further comprises a read buffer unit;
the read-write control circuitry is further configured to:
after judging whether the read address corresponding to the current read operation is the same as the address corresponding to the data of the second-level write cache unit, if not, entering the following judgment on the read cache unit;
for the read cache unit: judging whether a read address corresponding to the current read operation is the same as an address corresponding to the data of the read cache unit, and if so, acquiring the data of the current read operation from the read cache unit; and if not, reading the required data from the memory.
11. The read-write control circuit of claim 8, wherein the buffer module further comprises a read buffer unit;
the read-write control circuitry is further configured to:
reading the data of the read address and the adjacent storage position thereof from the memory based on the read address corresponding to the current read operation;
and writing the data of the read address as the data required by the current read operation, and writing the data of the adjacent storage positions into the read cache unit.
12. The read-write control circuit of claim 1, wherein the cache module comprises a first level write cache unit, a second level write cache unit, and a read cache unit, and the read-write control circuit further comprises a first data selector, a second data selector, a third data selector, a fourth data selector, and a write data selection control circuit;
the input end of the first-level write cache unit is connected with a bus, and the output end of the first-level write cache unit is respectively connected with the input end of the first data selector and the input end of the second data selector;
the input end of the second-level write cache unit is connected with the output end of the first data selector, and the output end of the second-level write cache unit is respectively connected with the input end of the write data selection control circuit and the input end of the third data selector;
the input end of the read cache unit is connected with the memory, and the output end of the read cache unit is connected with the input end of the fourth data selector;
the input end of the first data selector is also connected with a bus, and the output end of the first data selector is also connected with the write data selection control circuit;
the input end of the second data selector is also connected with the output end of the third data selector, and the output end of the second data selector is connected with a bus;
the input end of the third data selector is also connected with the output end of the fourth data selector;
the input end of the fourth data selector is also connected with the memory;
the output end of the write data selection control circuit is also connected with the memory.
13. A control method of a read-write control circuit is characterized in that the read-write control circuit comprises a cache module;
the method comprises the following steps:
when continuous read-write operation exists, executing the read operation, and storing data corresponding to the write operation in the cache module;
and writing the data corresponding to the write operation into a memory from the cache module.
14. A chip comprising a read-write control circuit according to at least one of claims 1 to 12.
15. An electronic device comprising a read-write control circuit according to at least one of claims 1 to 12.
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| CN202210789662.6A CN115050405A (en) | 2022-07-06 | 2022-07-06 | Read-write control circuit, control method, chip and electronic equipment |
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| CN202210789662.6A CN115050405A (en) | 2022-07-06 | 2022-07-06 | Read-write control circuit, control method, chip and electronic equipment |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117149671A (en) * | 2023-08-30 | 2023-12-01 | 上海合芯数字科技有限公司 | Cache realization method, system, medium and electronic equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117149671A (en) * | 2023-08-30 | 2023-12-01 | 上海合芯数字科技有限公司 | Cache realization method, system, medium and electronic equipment |
| CN117149671B (en) * | 2023-08-30 | 2024-05-24 | 上海合芯数字科技有限公司 | Cache realization method, system, medium and electronic equipment |
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