CN102522113A - SDRAM bridge circuit - Google Patents
SDRAM bridge circuit Download PDFInfo
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- CN102522113A CN102522113A CN2011103021383A CN201110302138A CN102522113A CN 102522113 A CN102522113 A CN 102522113A CN 2011103021383 A CN2011103021383 A CN 2011103021383A CN 201110302138 A CN201110302138 A CN 201110302138A CN 102522113 A CN102522113 A CN 102522113A
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Abstract
The invention relates to an SDRAM bridge circuit, comprising a first module, a second module and a PHY module, wherein the first module is used for analyzing SDRAM access commands sent by a controller, the second module is used for converting the SDRAM access commands into commands which are acceptable to the PHY module, the PHY module is used for accessing a memory by using the commands which are acceptable to the PHY module, and the memory and the controller are different in SDRAM type. According to the invention, the SDRAM controller can be allowed to realize the access to the DDR3 SDRAM to carry out data access through the bridge circuit; compared with replacing or redeveloping chips of the integrated SDRAM controller, the circuit modification is small, the development period is short, the cost is low, and the bridge circuit is well compatible with the original system.
Description
Technical field
The present invention relates to the access control of Synchronous Dynamic Random Access Memory.
Background technology
Synchronous Dynamic Random Access Memory (SDRAM) is widely used in various electronic products, simultaneously also in continuous update.Up to now, a large amount of commercial successive dynasties products have SDRAM, DDR SDRAM, DDR2SDRAM and DDR3SDRAM (full name of DDR is Double Data Rate, and meaning is a double data rate).More early stage SDRAM has withdrawed from main flow even stopping production, and increasing product uses the storer such as the DDR3SDRAM of a new generation.
SDRAM accepts the visit of sdram controller, and DDR/DDR2/DDR3 SDRAM accepts the visit of controller and PHY (Physical Interface, physical layer interface), realizes data access.Each all can only carry out physical connection with corresponding controller or PHY for storer, can not be general between each generation, can only connect sdram controller such as SDRAM, and can not connect DDR3PHY.
The chip that needs plug-in storer generally through integrated corresponding memory controller or PHY, is realized the visit to storer.When memory updating was regenerated, original memory controller or PHY also faced the replacing problem, and more changer controller or PHY just need to change or develop again chip.
When integrated new PHY is changed or revised to existing chip, meeting " pulled one hair and move the whole body ", causes circuit change amount big, and the construction cycle is long, and is costly, and can not with the original system compatibility.Such as need be replaced by the CPU of plug-in DDR3SDRAM to the central processor CPU of plug-in SDRAM the time, operating system also faces replacing, and software is exploitation again all; Huge when chip-scale, the overall operation amount is huge when developing again, and is costly.
Summary of the invention
The purpose of this invention is to provide can solution of the above problems.
For realizing above-mentioned purpose, the invention provides a kind of SDRAM bridgt circuit.This circuit comprises first module, second module and PHY module; Wherein, The SDRAM visit order that the first module parses controller is sent here; Second module converts the SDRAM visit order the acceptable order of into PHY module, and the PHY module is utilized the acceptable command access storer of said PHY module, and wherein storer has different SDRAM types with controller.
The present invention can let sdram controller pass through this bridgt circuit through a kind of SDRAM bridgt circuit of design, realizes the visit to DDR3SDRAM, carries out data access; Compare the chip of changing or developing integrated sdram controller again, circuit is changed little, and the construction cycle is short, and cost is low, and well compatible with original system.
Description of drawings
Through accompanying drawing and embodiment, technical scheme of the present invention is done further detailed description below.In the accompanying drawing:
Fig. 1 is the synoptic diagram of the SDRAM bridgt circuit of the embodiment of the invention;
Fig. 2 has illustrated the interface signal situation of first module 110;
Fig. 3 has illustrated the synoptic diagram that second module 120 is changed;
Fig. 4 is a SDRAM reading of data switching synoptic diagram;
Fig. 5 is that SDRAM writes data switching synoptic diagram;
Fig. 6 is the synoptic diagram under the situation of transferring one to one;
Fig. 7 is that the long synoptic diagram that has influence on the switching of next reading order of holding time is handled in write command;
Fig. 8 be a pair of two the switching situation under synoptic diagram;
Fig. 9 has illustrated to utilize two to overlap the synoptic diagram that the PHY switching is read and write;
Figure 10 is a state-transition table;
Figure 11 increases bit wide to reduce BL minimizing data transmission period;
Figure 12 reduces the synoptic diagram that bit wide increases BL;
Figure 13 is the synoptic diagram of the SDRAM bridgt circuit of another embodiment of the present invention.
Embodiment
Fig. 1 is the synoptic diagram of the SDRAM bridgt circuit of the embodiment of the invention.As shown in Figure 1, the SDRAM bridgt circuit comprises first module, 110, the second modules 120 and DDR3 physical interface (calling PHY in the following text) module 130.Three common processes that realize the sdram controller visit order is converted into access DDR3SDRAM storer of module.
Fig. 2 has illustrated the interface signal situation of first module 110.As shown in Figure 2; First module 110 according to sdram controller send here synchronously with road clock CLK; All reception signals from sdram controller are carried out input sample, the data that the transmission signal of giving sdram controller is exported and prepared for sdram controller to read from DDR3 SDRAM storer.
Signal from sdram controller comprises SDRAM control signal CKE, CS#, WE#, CAS#, RAS#, and address signal A, BA, data I shielded signal DQM, data-signal are DQ (writing/read).CKE is a sheet internal clock enable signal, and CS# forbids or enables all outer input signals of CLK, CKE and DQM.WE# writes enable signal.CAS#, RAS# are respectively row and row address latch signal.Address signal A is an address bus, and BA is that group address is selected.DQM controls the output buffering under reading mode, shielding input data under WriteMode.
Fig. 3 has illustrated the synoptic diagram that second module 120 is changed.Conversion as shown in Figure 3, that second module 120 is responsible between SDRAM visit order, data and the DDR3 PHY unit.In an example; According to the work clock of second module 120 and sdram controller send here synchronously with the phase relation between the clock CLK of road; Convert visit order ACTIVE, READ, WRITE, PRECHARGE, REFRESH into the DDR3PHY command signal, simultaneously the relevant data of conversion.The work clock of second module is the interface clock of DDR3 PHY unit regulation, can confirm the phase relation between the two with the hopping edge of road clock CLK synchronously through what the collection sdram controller was sent here, to guarantee the correctness of data acquisition.Generally speaking, the interface clock of PHY unit regulation has the frequency that is higher than synchronously with the road clock.DDR3 PHY unit provides the internuncial IP (ip module) between memory controller and the DDR3 memory devices.The PHY unit provides standard DDR phy interface bus in the memory interface side, in local side internal bus interface is provided.Internal bus interface has defined signal, the sequential between DDR3 PHY and the corresponding D DR3 sdram controller.
In the present invention, sdram controller sends various visit orders, and the SDRAM bridgt circuit is correct resolves and the conversion visit order, realizes that data correctly write DDR3 SDRAM storer and from wherein reading.
Fig. 4 is a SDRAM reading of data switching synoptic diagram.When sdram controller was initiated the read operation request, first module in the SDRAM bridgt circuit and second module converted the read operation request into to DDR3 SDRAM logic reading order, and DDR3 PHY module reads DDR3 SDRAM according to this logic reading order.In embodiments of the present invention, second module 120 receives the data of the DDR3 SDRAM that reads that DDR3 PHY modules are sent here; Then, first module 110 is seen reading of data off and is given sdram controller, accomplishes the process that reads.In an example, second module is accomplished in the time and is read DDR3 SDRAM at the DDR3 side CL of agreement (CAS latency, column address strobe postpones, approximately 6-7 PHY clock); First module is given sdram controller with reading of data at the controller side CL (being generally 2,3 clocks) from the agreement of reading order in the time.
Fig. 5 is that SDRAM writes data switching synoptic diagram.When sdram controller was initiated write operation requests, the SDRAM bridgt circuit converted write operation requests into the write order of DDR3 SDRAM.In addition, under burst mode, the SDRAM bridgt circuit will receive complete usually or part writes data, just can give DDR3 PHY module, writes DDR3 SDRAM then.Therefore, write the time that DDR3 SDRAM data are accomplished, longer than the SDRAM ablation process time of routine possibly, taken the portion of time after the sdram controller write command.
When sdram controller initiates to write data, and when initiating reading of data, whether can have influence on the switching of SDRAM reading order according to writing DDR3SDRAM command process holding time, can produce following two kinds of substitute modes: transfer one to one (1); (2) a pair of two switchings.
Fig. 6 is the synoptic diagram under the situation of transferring one to one.When writing DDR3 SDRAM command process holding time and can not have influence on the switching of next reading order of sdram controller, adopt and to accomplish the sdram controller visit once the plug-in DDR3 SDRAM of cover DDR3 PHY and transfer.At this moment, after sdram controller sent and writes data command, the interval time enough that is bound to was initiated reading order again.Under another kind of situation,, its buffer memory that leaves in the PHY module is ready to if reading the address and can predicting of sdram controller just can be read DDR3 SDRAM data in advance.When PHY module to DDR3 SDRAM write data the time, the PHY module sends to sdram controller with the data of depositing in the buffer memory through second module 120, first module 110 based on read request.
Specifically; Order and data that second module 120 is sent first module 110 here; Convert command signal form and the sequential of DDR3PHY into, give DDR 3PHY module 130, receive the reading of data that DDR3 PHY module 130 is sent here simultaneously; Convert the form and the sequential of sdram controller into, give first module 110.
If it is long to write DDR3 SDRAM command process holding time, can have influence on the switching (referring to Fig. 7) of the next reading order of sdram controller.At this moment, adopt two cover plug-in DDR3 SDRAM of DDR3 PHY and inner buffer binding operations, accomplish sdram controller visit switching.
Fig. 8 be a pair of two the switching situation under synoptic diagram.As shown in Figure 8, PHY module 130 comprises two cover DDR3 PHY unit (being designated as 1# PHY, 2# PHY respectively).The all external DDR3SDRAM storer in 1# and 2#PHY unit (being designated as 1# DDR3,2# DDR3 respectively).Need to do mirror image synchronous for the data that write of 1#, 2# two cover DDR3.
1# PHY, 2# PHY two cover switching carrying out in turn switch over operations, inner buffer are only just launched when identical with nearest write address and are accomplished reading of data reading the address, combine to accomplish the sdram controller visit and transfer.
When sdram controller writes data, suppose that 1# PHY writes earlier, write inner buffer simultaneously, 2# PHY awaits orders, and prepares to accept the reading order that sdram controller sends at any time.If this moment (when promptly writing 1# PHY), sdram controller is initiated the read operation order, if the address of read and write is different, is responsible for accomplishing data by 2#PHY and reads; If the address of read and write is identical, data in buffer before then inner buffer is read.After 1#PHY writes completion, the data that write 1#PHY are write 2#PHY, to keep the data sync mirror image of two cover PHY unit write stories.Avoided reading the switching failure like this.Fig. 9 has illustrated to utilize two to overlap the synoptic diagram that the PHY switching is read and write.
Normal work period, if it is different with nearest write address to read the address, which just reads cover free time among 1# PHY and the 2# PHY, if two overlap all the free time then select a cover arbitrarily; If it is identical with nearest write address to read the address, then read inner buffer.
In an example, second module 120 adopts state machines to control the operation of different PHY and continuous DDR3SDRAM thereof.
Figure 10 is a state-transition table.As shown in the figure, when second module reset or state machine when other states get into idle IDLE state, second module is different according to writing of sending here of first module, reading order, and state machine is carried out the different state redirect.
1) when first module 110 is sent write operation < WRITE n>(writing n) here (n is the address), select 1#PHY that the 1#DDR3 that it links to each other is carried out write operation (mark 100 among the figure), write data simultaneously and deposit inner buffer (mark 101 among the figure) in;
2) when the write operation < WRITE n>(writing n) of 1# PHY is not also accomplished; < READ m>(read m when first module 110 was just sent read operation here; Promptly read the address and to write the address different), start and read the 2# DDR3 (mark 102 among the figure) that 2# PHY links to each other, read switching;
3) 2# DDR3 reads after switching accomplishes, and the data of carrying out 2# DDR3 write (mark 105 among the figure), and the content that writes 1# DDR3 is write 2# DDR3, promptly accomplish 1#, 2# DDR3 to write data image synchronous; Write and accomplish back (mark 106 among the figure), entering IDLE state;
4) when the write operation < WRITE n>(writing n) of 1# DDR3 is not also accomplished, when first module 110 is just sent read operation < READ n>(reading n) (promptly read address with write the address identical) here, start and read inner buffer (mark 103 among the figure), read switching; After completion was read, the data that get into 2#DDR3 write (among the figure 105), accomplish 1#, 2# two cover DDR3 to write data image synchronous;
5) when the write operation < WRITE n>(writing n) of 1# DDR3 is accomplished, also do not receive the reading order that first module 110 is sent here, carry out the 2#DDR3 data and write (mark 104 among the figure), promptly accomplish 1#, 2# two cover DDR3 to write data image synchronous; Write and accomplish back (mark 106 among the figure), get into free time < IDLE>state.
According to the SDRAM access rate, second module is selected burst transfer periodic quantity and bit wide, with the reply different demands.
In one embodiment, can increase DDR3 SDRAM memory side bit wide, reduce BL (burst transfer cycle) value, reduce data transmission period, make reading of data switching obtain the more processing time, correctly accomplish switching.
Figure 11 increases bit wide to reduce BL minimizing data transmission period.Shown in figure 11, for example, sdram controller data bit width 8 bit bit wides, burst-length BL=8, CL=3, clock frequency 100MHz, promptly the read command from sdram controller has the 30ns time to sending data back to.DDR3 SDRAM side is taked clock rate 800MHz, CL=10.If BL=8 can not accomplish switching in the 30ns that sdram controller requires, need increase the bit wide of second module and PHY module is that 16 bits, BL are reduced to 4; Reduced data transmission period; Just can in 30ns, accomplish switching, and total data bit number is identical, the correct realization.This way is applicable to the scene that the SDRAM access rate is higher.
In another embodiment, satisfying under the situation of transit time, reducing the bit wide of DDR3 SDRAM storer, increasing the BL value, reducing cost.Figure 12 reduces the synoptic diagram that bit wide increases BL.For example, sdram controller data bit width 32 bit bit wides, BL=4, CL=3, clock frequency 50MHz, promptly the read command from sdram controller has the 60ns time to sending data back to; The DDR3 side is taked clock rate 400MHz, CL=6, and reducing by half bit wide is that 16 bits, BL increase are 8; Add command conversion and data transmission period, still can in the 60ns that sdram controller requires, accomplish switching, and total data bit (bit) number is identical; The correct realization reduced cost.This way is applicable to the scene that the SDRAM access rate is lower.
Figure 13 is the synoptic diagram of the SDRAM bridgt circuit of another embodiment of the present invention.Shown in figure 13, the SDRAM bridgt circuit comprises three module 220 and DDR3 PHY module 130.Compare with SDRAM bridgt circuit shown in Figure 1, first module 110 and second module 120 are replaced by a three module 220.At three module 220, work clock and the enabling pulse with the road clock synchronization with SDRAM is provided, under the control of enabling pulse, gather the sdram controller signal, and directly do not use the SDRAM synchronous clock with this work clock.Three module 220 is resolved the visit order that sdram controller is sent here, and the signal transmitting and receiving between completion and the outside sdram controller.Specifically, three module 220 is resolved visit order under the control of high frequency clock, and the visit order after will resolving and data-switching to be written are acceptable form of DDR3 PHY and sequential.DDR3 PHY module 130 receives the order that three modules 220 send here and writes data, gives outside DDR3 SDRAM storer; Receive the data that read from outside DDR3 SDRAM storer simultaneously, send to three module 220.
The present invention is except that the bridging method of the above-mentioned SDRAM switching DDR3 SDRAM that enumerates; Satisfying under the situation of transit time, be equally applicable to SDRAM and be forwarded to DDR2 SDRAM, DDR SDRAM and be forwarded to the bridge joint that DDR2 SDRAM, DDR SDRAM are forwarded to DDR3 SDRAM.As long as the visit order that sdram controller or DDRPHY see off change to DDR2/DDR3 PHY have time enough to visit DDR2/DDR3 SDRAM accordingly, DDR2/DDR3 PHY reads DDR2/DDR3 SDRAM data and can send back in the time at the CL of sdram controller/DDR PHY agreement, realization bridge joint that just can be correct.
The present invention can let sdram controller pass through this bridgt circuit through a kind of SDRAM bridgt circuit of design, realizes the visit to DDR3 SDRAM, carries out data access; Compare the chip of changing or developing integrated sdram controller again, circuit is changed little, and the construction cycle is short, and cost is low, and well compatible with original system.
Above-described embodiment; The object of the invention, technical scheme and beneficial effect have been carried out further explain, and institute it should be understood that the above is merely embodiment of the present invention; And be not used in qualification protection scope of the present invention; All within spirit of the present invention and principle, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (11)
1. a SDRAM bridgt circuit is characterized in that comprising first module, second module and PHY module; Wherein, The SDRAM visit order that the first module parses controller is sent here; Second module converts the SDRAM visit order the acceptable order of into PHY module, and the PHY module is utilized the acceptable command access storer of said PHY module, and wherein storer has different SDRAM types with controller.
2. SDRAM bridgt circuit as claimed in claim 1, it is characterized in that first module controller with the road clock control under work, second module is worked down in the control of the interface clock of PHY module regulation.
3. SDRAM bridgt circuit as claimed in claim 1; It is characterized in that first module and second module merge into three module; Three module with controller with the control of the work clock of road clock synchronization under resolve visit order, and the visit order after will resolving converts the acceptable order of DDR3PHY into.
4. like the described SDRAM bridgt circuit of one of claim 1-3, it is characterized in that first module carries out command analysis with above-mentioned control signal according to truth table.
5. like the described SDRAM bridgt circuit of one of claim 1-3, it is characterized in that the PHY module comprises a PHY unit.
6. SDRAM bridgt circuit as claimed in claim 5; It is characterized in that the PHY module comprises at least one the 2nd PHY unit and buffer circuit, said second module selects a PHY unit to transfer from a PHY unit and said at least one the 2nd PHY unit.
7. SDRAM bridgt circuit as claimed in claim 6 is characterized in that second module comprises state machine, and second module is coordinated the work of a PHY unit and the 2nd PHY unit according to state machine.
8. SDRAM bridgt circuit as claimed in claim 7 is characterized in that when second module receives the SDRAM visit order of write operation, selects a PHY unit to carry out write operation, writes data simultaneously and deposits inner buffer in; When second module receives the SDRAM visit order that reads the address read operation different with writing the address and said write operation when also not accomplishing, select the 2nd PHY unit to carry out read operation.
9. SDRAM bridgt circuit as claimed in claim 7 is characterized in that when second module receives the SDRAM visit order of write operation, selects a PHY unit to carry out write operation, writes data simultaneously and deposits inner buffer in; When second module receives the SDRAM visit order that reads the address read operation identical with writing the address and said write operation when also not accomplishing, start and read inner buffer; And after completion was read, the data in the inner buffer write the 2nd PHY unit.
10. like the described SDRAM bridgt circuit of one of claim 1-3, it is characterized in that the access rate according to SDRAM, second module is selected burst transfer periodic quantity and bit wide.
11. like the described SDRAM bridgt circuit of one of claim 1-3, it is characterized in that controller is sdram controller or DDR PHY device, storer is DDR2 SDRAM or DDR3 SDRAM.
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| CN201110302138.3A CN102522113B (en) | 2011-09-28 | 2011-09-28 | SDRAM bridge circuit |
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| CN201110302138.3A CN102522113B (en) | 2011-09-28 | 2011-09-28 | SDRAM bridge circuit |
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| CN102522113A true CN102522113A (en) | 2012-06-27 |
| CN102522113B CN102522113B (en) | 2014-09-17 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103761205A (en) * | 2014-01-03 | 2014-04-30 | 北京控制工程研究所 | Storage bridging method suitable for SPARC spatial processor |
| CN104333369A (en) * | 2014-07-08 | 2015-02-04 | 北京芯诣世纪科技有限公司 | DDR3 PHY SSTL15 output drive circuit |
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| CN102177549A (en) * | 2008-10-14 | 2011-09-07 | 莫塞德技术公司 | A composite memory having a bridging device for connecting discrete memory devices to a system |
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| CN103761205A (en) * | 2014-01-03 | 2014-04-30 | 北京控制工程研究所 | Storage bridging method suitable for SPARC spatial processor |
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| CN104333369B (en) * | 2014-07-08 | 2017-08-29 | 北京芯诣世纪科技有限公司 | A kind of DDR3 PHY SSTL15 output driving circuits |
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