CN204886928U

CN204886928U - Small time interval data acquisition device based on PCIE bus

Info

Publication number: CN204886928U
Application number: CN201520691478.3U
Authority: CN
Inventors: 邱春玲; 韩醒之; 徐倩; 王娅男; 郭静
Original assignee: Jilin University
Current assignee: Jilin University
Priority date: 2015-09-09
Filing date: 2015-09-09
Publication date: 2015-12-16
Anticipated expiration: 2025-09-09

Abstract

The utility model relates to a small time interval data acquisition device based on PCIE bus connects measured data buffer unit and signal acquisition translation unit constitution by the host computer respectively through PCIE bus connection FPGA the control unit, FPGA the control unit. The utility model discloses it is not enough to regard as the converter to solve existing data collection system sampling frequency under the high -speed condition with the TDC -GPX chip, and the big problem of data volume is with high costs to and use the TDC who designs based on FPGA lower as the converter technical indicator, the long problem of development period. Communication bus adopts fast -speed PCIE bus, has solved and has regarded as the little clock frequency of the inside time delay of the control unit high with FPGA, and the converter be TDC -GPX time interval measurement chip, and communication bus be PCIE X4 bus, tests read and write speed and can reach 500M byte / more than second, transmission rate height.

Description

The tiny time interval data harvester of Based PC IE bus

Technical field

The utility model relates to a kind of high speed time interval data harvester, particularly a kind of tiny time interval data harvester of time of flight secondary ion massspectrometry instrument TOF-SIMS (Timeoffly-secondaryionmassspectrometry).

Background technology

Current large-scale time of flight secondary ion massspectrometry instrument and a lot of large-scale mass spectrometer are all buy external data acquisition module in time interval collection, not the corresponding data acquisition unit of special development.In time of flight secondary ion massspectrometry instrument (TOF-SIMS), ion detector exports pulse to be needed to complete collection by high-speed data acquiring device, data acquisition unit determines every measurement index of whole instrument to a great extent, therefore has very consequence.

CN104570855A discloses one " a kind of data acquisition unit based on FPGA and method ", this system and method comprises information acquisition module, message processing module, FPGA module, FPGA model is EP1C6Q240C8, digital to analog converter model in message processing module is AD9288 or AD7278, this data acquisition unit and method accurately can complete the collecting work of measurement data, but it is lower for two kinds of AD converter sample frequencys using tiny time interval gathers, large relative to TDC ADC data amount, high to other part requirement of system, EP1C6Q240C8 model FPGA also cannot support the ultrahigh speed buses such as PCIE preferably, cannot communicate with PC to two-forty, therefore the measurement collecting work as high speed tiny time interval required in TOF-SIMS project cannot be applied to.

CN104216279A discloses " a kind of time interval measurement device based on FPGA ", the invention provides a kind of time interval measurement device based on FPGA, the transducer of this device is the TDC at the inner complete design of FPGA, it is comparatively accurate to measure, cost is low, be widely used, but the TDC based on FPGA design compares and uses special TDC-GPX time interval measurement chip, system index is not enough far away and the construction cycle is longer, be difficult to be applied in the field, tiny time interval of change at a high speed, and the aspect such as not mentioned communication module in invention, the measurement collecting work at a complete tiny time interval cannot be completed.

The existing time interval data harvester using FPGA as control unit, transducer mainly contains two schemes, a kind ofly adopt traditional ADC, there is sample frequency deficiency, data volume problem, problem that cost is high,, there is the problem that system index is limited, the construction cycle is long in the another kind of TDC adopted based on FPGA design.And the current scheme in communication interface aspect mostly is RS-232/RS-485 bus, usb bus or pci bus, in a lot of high speed acquisition field, there is the problem that the speed of communications is too low.

Summary of the invention

The purpose of this utility model is for the deficiencies in the prior art, provides a kind of tiny time interval data harvester of Based PC IE bus

The purpose of this utility model is achieved through the following technical solutions:

The tiny time interval data harvester of Based PC IE bus, be connect control system by host computer through PCIE bus, control system connects measurement data buffer unit respectively and signals collecting converting unit is formed.

Control system is connected with SDRAM control module through order data cache module by PCIE bus communication control module, and order data cache module connects and composes through TDC-GPX control module and the preliminary cache module of image data.

Signals collecting converting unit is connected with ion detector through analog signal conditioner module by special time interval measurement chip, and pulse generator and special time interval measurement chip connect and compose.

Measurement data buffer unit is made up of DDR2SDRAM.

Beneficial effect: the utility model solves available data harvester using TDC-GPX chip as transducer, sample frequency deficiency, the large problem of data volume, problem that cost is high is there is in the traditional ADC of many employings as transducer, and use the problem that the TDC designed based on FPGA is lower as converter technology index, the construction cycle is long, communication bus adopts PCIE bus at a high speed, solve the harvester that existing a lot of communication bus is RS-232/RS-485 bus, usb bus or pci bus, under high-speed case, have the problem of transmission rate deficiency.The tiny time interval data harvester of this Based PC IE bus, high as control unit internal delay time clock frequency using FPGA, transducer is TDC-GPX time interval measurement chip, and communication bus is PCIEX4 bus, test reading writing rate can reach more than 500M byte per second, and transmission rate is high

Accompanying drawing explanation

Fig. 1 is the tiny time interval data harvester structured flowchart of Based PC IE bus.

Fig. 2 is the tiny time interval data harvester sequencing control flow chart of Based PC IE bus.

Embodiment

Below in conjunction with drawings and Examples, the utility model is described in further detail:

Measurement data buffer unit is made up of DDR2/SDRAM.

As shown in Figure 1, PC is connected with control system through PCIE bus, and control system is connected with TDC-GPX time interval measurement chip, is connected with SDRAM data buffer storage unit.Control system inside is made up of PCIE bus communication control module, control command cache module, SDRAM control module, the preliminary cache module of image data, TDC-GPX control module, clock is provided through frequency multiplication, frequency division for each several part by FPGA internal clocking, the communication work of harvester and PC is completed by PCIE control module, control system is connected with PC by PCIE bus, and PCIE bus completes control by PCIE bus communication control module in FPGA.Signals collecting converting unit for core, and completes control by TDC-GPX control module in FPGA with the special time interval measurement chip of TDC-GPX.SDRAM data buffer storage unit take DDR2SDRAM as core, and completes control by SDRAM control module in FPGA.

The order that PC is sent to control system through PCIE bus is buffered in order data cache module by order data cache module, TDC-GPX control module reads control command control TDC-GPX time interval measurement chip and gathers tiny time interval from order data cache module, measurement data carries out preliminary buffer memory through gathering preliminary cache module, be stored in SDRAM measurement data buffer unit afterwards, eventually through PCIE bus by data transfer to PC.

START channel signal is generated by pulse generator, for flight initial signal, STOP passage is generated as ion by ion detector and flies in dirft tube end signal, TDC-GPX is by the time interval between STRAT passage and STOP channel signal, obtain the flight time of ion in dirft tube, and export the measurement result of digital signal form to control system.

FPGA Control timing sequence as shown in Figure 2, first initialization is carried out to a harvester parts, afterwards the command packet be sent in order data cache module through PCIE bus is resolved, order is assigned to each module of control system, TDC-GPX detects START passage and STOP channel signal after obtaining acquisition, obtain time interval collection result, after the preliminary cache module buffer memory of image data, write (DDR2SDRAM) in measurement data buffer unit, then read wherein image data by PCIE bus transfer to PC.

The collection at tiny time interval can be stablized, be completed accurately, at high speed to Based PC IE bus as the tiny time interval data harvester of the Based PC IE bus of transducer, as control unit, the special time interval measurement chip of TDC-GPX as communication bus, FPGA.

PC is connected with control system through PCIE bus, and control system is connected with TDC-GPX time interval measurement chip, is connected with SDRAM data buffer storage unit.

Control system inside is made up of PCIE bus communication control module, control command cache module, SDRAM control module, the preliminary cache module of image data, TDC-GPX control module, clock is provided through frequency multiplication, frequency division for each several part by FPGA internal clocking, the communication work of harvester and PC is completed by PCIE control module, control system is connected with PC by PCIE bus, and PCIE bus completes control by PCIE bus communication control module in FPGA.Signals collecting converting unit for core, and completes control by TDC-GPX control module in FPGA with the special time interval measurement chip of TDC-GPX.SDRAM data buffer storage unit take DDR2SDRAM as core, and completes control by SDRAM control module in FPGA.

Claims

1. a tiny time interval data harvester for Based PC IE bus, is characterized in that, is to connect control system by host computer through PCIE bus, and control system connects measurement data buffer unit respectively and signals collecting converting unit is formed.

2. according to the tiny time interval data harvester of Based PC IE bus according to claim 1, it is characterized in that, control system is connected with SDRAM control module through order data cache module by PCIE bus communication control module, and order data cache module connects and composes through TDC-GPX control module and the preliminary cache module of image data.

3. according to the tiny time interval data harvester of Based PC IE bus according to claim 1, it is characterized in that, signals collecting converting unit is connected with ion detector through analog signal conditioner module by special time interval measurement chip, and pulse generator and special time interval measurement chip connect and compose.

4. according to the tiny time interval data harvester of Based PC IE bus according to claim 1, it is characterized in that, measurement data buffer unit is made up of DDR2SDRAM.