CN201540469U - Data acquiring device - Google Patents
Data acquiring device Download PDFInfo
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- CN201540469U CN201540469U CN2009201731475U CN200920173147U CN201540469U CN 201540469 U CN201540469 U CN 201540469U CN 2009201731475 U CN2009201731475 U CN 2009201731475U CN 200920173147 U CN200920173147 U CN 200920173147U CN 201540469 U CN201540469 U CN 201540469U
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Abstract
The utility model provides a data acquiring device, which includes an A/D (analog-to-digital) converter, a controller and a bus interface, wherein an input terminal of the A/D (analog-to-digital) converter is connected with acquired analog signals; an input terminal of the controller is connected with digital signals output by the A/D converter according to the analog signals, and a control terminal of the controller is connected with preset level signals; and an input terminal of a bus interface for outputting digital signals is connected with digital signals output by the controller according to the comparison results of the digital signals and the preset level signals. The data acquiring device of the utility model has the advantages that after the value of the digital signal subject to the A/D conversion is judged, digital signals meeting sending conditions are output, a special DA chip does not need to be used, a user does not need to input reference source signals, the triggering function of analog quantity can be realized, and the cost can be reduced; the use is more convenient for a user; and further, the responding speed is improved and the delay time is reduced.
Description
Technical field
The utility model relates to measurement and control area, relates in particular to a kind of data collector.
Background technology
Along with modern comfort towards digitizing, informationalized high speed development, need lot of data to transmit, and as the preceding continuous step of necessity of the processing of data and transmission, the data collecting card that is used for various types of data is gathered more and more plays a part very important in every field.Data collecting card is by using analog to digital converter (Analog Digital converter, be called for short AD converter), all kinds of simulated datas that collect are converted to the numerical data that computing machine can be discerned, and be uploaded to the computing machine that is attached thereto, thereby make computing machine can realize it is carried out the function of signal analysis.
Usually data collecting card has multiple mode of operation, the triggering of external signal is wherein the most frequently used a kind of mode of operation, simulating signal triggers and digital signal triggers two kinds and the mode of operation of external trigger can be divided into, it is divided according to the dissimilar of trigger source signal, when trigger source signal is digital signal, be referred to as digital signal and trigger, when trigger source signal is simulating signal, is referred to as simulating signal and triggers.Comparatively speaking, the mode that simulating signal triggers is more more complicated than the mode that digital signal triggers, and relates to cooperatively interacting of hardware circuit and software.
In the existing data collecting card, if use the analog quantity trigger mode, after collecting simulating signal, immediately it is not carried out the conversion of modulus signal, analog to digital converter needs just to carry out the transfer process of modulus signal under the triggering command of controller.Fig. 1 is the hardware circuit diagram of data collecting card in the prior art, as shown in Figure 1, after each road simulating signal enters MUX, select one tunnel simulating signal by MUX, after the signal processing and amplifying of signal amplifier, send it in the AD converter, AD converter is not changed it immediately, after receiving the triggering command of controller, be digital signal just only with the analog signal conversion that receives, and deposit first in first out (FirstIn First Out in by controller, abbreviation FIFO) in the storage unit, is transferred to computing machine by bus interface at last.And for controller, its triggering command of sending is determined by the signal comparative result of a comparer that is attached thereto, this comparer is by trigger source signal and digital-to-analog conversion (Digital Analog converter with user's input, abbreviation DA conversion) the triggering level signal of chip generation carries out the high speed simulation relatively, comparative result is sent to controller, controller is judged it, if satisfy trigger condition, then send triggering command to AD converter, make it begin conversion,, then do not instruct to AD converter if do not satisfy trigger condition, continue to wait for, take place up to trigger event.
The inventor finds in the process of invention, there are the following problems at least in the prior art: at first, for comparer, it needs the special DA conversion chip that uses to be used to provide the triggering level signal, thereby make the cost of capture card improve, the area of whole printed circuit board (PCB) increases, and the user need use analog quantity trigger pip (Analog Trigger, being called for short ATR) passage is to import another road reference source signal, and also the use to the user has brought inconvenience; Secondly, AD converter only determines at controller and just begins translation data after trigger event takes place, thereby has brought time-delay for the whole data collection process, has reduced speed.
The utility model content
The purpose of this utility model is to provide a kind of data collector, be used for solving the data collecting card of prior art, need to use special DA conversion chip so that the reference source signal of analog comparator to be provided, thereby the production cost height that causes, and the data collecting card that is used for solving prior art, AD converter needs just to carry out conversion work under the trigger pip of controller, thereby in the process of conversion of signals that causes and transmission time-delay is arranged, problem of slow response realizes that a kind of cost reduces, speed faster data collecting device.
For achieving the above object, the utility model provides a kind of data collector, comprising: analog to digital converter, controller and bus interface;
The input end of described analog to digital converter connects the simulating signal that collects;
The input end of described controller connects the digital signal of described analog to digital converter according to described simulating signal output, and the control end of described controller connects the predetermined level signal;
The input end that is used to export the described bus interface of described digital signal connects the described digital signal that described controller is exported according to the comparative result of described digital signal and described predetermined level signal.
The utility model provides a kind of data collector, by will through the digital signal after the AD conversion directly and the preset trigger level compare, and directly carry out the output of the digital signal after AD changes according to this comparative result, therefore need not to use special DA conversion chip so that the comparative level of analog comparator to be provided, also need not the user is analog comparator input reference source signal by the ATR passage, thereby reduced the production cost of data collector effectively, and for the user, use convenient; Further, AD converter need not just to carry out conversion work under the triggering control of controller, and after controller one was judged the trigger event generation, the digital signal after just directly will changing sent to computing machine, thereby has improved reaction velocity, has reduced delay time.
Description of drawings
Fig. 1 is the hardware circuit diagram of data collecting card in the prior art;
Fig. 2 is the structural representation of the utility model data collector embodiment;
Fig. 3 is the hardware circuit diagram of the utility model data collector embodiment.
Embodiment
Below by drawings and Examples, the technical solution of the utility model is described in further detail.
Fig. 2 is the structural representation of the utility model data collector embodiment.As shown in Figure 2, the data collector of present embodiment comprises: analog to digital converter 1, controller 2 and bus interface 3.Its middle controller 2 is connected with bus interface 3 with analog to digital converter 1 respectively, and the input end of analog to digital converter 1 connects the simulating signal that collects, and is digital signal with the analog signal conversion that receives; The input end connection mode number converter 1 of controller 2 is according to the digital signal of simulating signal output, the control end of controller 2 connects a predetermined level signal, after the digital signal that receives and predetermined level signal compared, whether this digital signal is sent to bus interface 3 according to relatively result's decision; Bus interface 3 is used for the digital signal that receives is exported to the computing machine of connection, and its input end connects the output terminal of controller 2.
Particularly, in the present embodiment, analog to digital converter 1 one receive simulating signal after, do not need to wait for the triggering command of controller 2 transmissions, but be digital signal directly with the analog signal conversion that receives, and send to controller 2, and controller 2 is after receiving this digital signal, size to this digital signal is carried out a judgement, judge whether this digital signal satisfies the requirement that is sent to bus interface 3, when having only the transmission of satisfying its setting when this digital signal to require, controller 2 just sends to the computing machine of connection with the digital signal that receives by bus interface 3, analyzes and handles to be used for computing machine.The concrete deterministic process of controller 2 is: in controller 2, comprise a signal comparator circuit 21 and signal sending circuit 22, this signal comparator circuit 21 is specially a digital signal comparator circuit, it has two input ends, the digital signal and a predetermined level signal of 1 output of difference connection mode number converter, and these two signals are compared, export a compare result signal; The digital signal that the input end connection mode number converter 1 of signal sending circuit 22 sends, its control end connects the compare result signal of signal comparator circuit 21 outputs, and whether the digital signal after 1 conversion of analog to digital conversion converter is sent to the computing machine that is attached thereto by bus interface 3 according to this compare result signal decision that control end receives.
Particularly, the comparative result of signal comparator circuit 21 comprises two kinds of situations: digital signal greater than predetermined level signal or digital signal less than the predetermined level signal, therefore the concrete transmission result of signal sending circuit 22 also comprises two kinds of situations, just digital signal is being sent to bus interface when digital signal during greater than the predetermined level signal, perhaps just digital signal is sent to bus interface during less than the predetermined level signal when digital signal, and specifically under which kind of situation signal sending circuit 22 just digital signal is sent to computing machine, need to decide according to concrete setting to controller 2.According to these two kinds of different settings, correspondingly, in the present embodiment, also signal sending circuit 22 can be divided into two kinds of first signal sending circuit and secondary signal transtation mission circuits.
When controller 2 is set to work as digital signal greater than the predetermined level signal, just with the digital signal output that receives, be that digital signal that controller 2 the is set transmission condition that should satisfy is for this digital signal during greater than the predetermined level signal, signal sending circuit 22 is specially first signal sending circuit, first signal sending circuit will directly send to computing machine with this digital signal by bus interface 3 when the compare result signal of signal comparator circuit 21 outputs is represented digital signal greater than the predetermined level signal; On the contrary, if the compare result signal representative of signal comparator circuit 21 output is that digital signal is during less than the predetermined level signal, first signal sending circuit does not then send digital signal to bus interface, does not promptly satisfy under the situation of transmission condition in digital signal, and this digital signal can not be sent out.
And when controller 2 specifically be set to when digital signal less than default level signal, with the digital signal output that receives, be that digital signal that controller 2 the is set transmission condition that should satisfy is for this digital signal during less than the predetermined level signal, signal sending circuit 22 is specially the secondary signal transtation mission circuit, the secondary signal transtation mission circuit will directly send to computing machine with digital signal by bus interface 3 when the compare result signal of signal comparator circuit 21 outputs is represented digital signal less than the predetermined level signal this moment; On the contrary, if the compare result signal representative of signal comparator circuit 21 output is that digital signal is during greater than the predetermined level signal, the secondary signal transtation mission circuit can not send digital signal to bus interface yet, promptly do not satisfy under the situation of the transmission condition that the secondary signal transtation mission circuit sets in digital signal, this digital signal can not be sent out yet.
So, when the digital signal that controller one is judged reception satisfies the transmission condition, just directly it is passed through the bus interface sending computer, and need not to judge whether to satisfy trigger condition by analog trigger circuitry, and after triggering command sent to analog to digital converter, analog to digital converter just carries out analog-to-digital operation, thus the time-delay that the data that cause send; Further, in the present embodiment, controller directly with the digital signal that receives source signal as a comparison, compares with its default level signal, and this is more specific to be numeral process relatively, thereby saved the DA chip, simplified circuit structure, reduced the power consumption of circuit board, dwindled the size of whole harvester, more reduced production cost, and for the user, used convenient.
The utility model provides a kind of data collector, by will through the digital signal after the AD conversion directly and the preset trigger level compare, and directly carry out the output of the digital signal after AD changes according to this comparative result, therefore need not to use special DA conversion chip so that the comparative level of analog comparator to be provided, also need not the user is analog comparator input reference source signal by the ATR passage, thereby reduced the production cost of data collector effectively, and for the user, use convenient; Further, AD converter need not just to carry out conversion work under the triggering control of controller, and after controller one was judged the trigger event generation, the digital signal after just directly will changing sent to computing machine, thereby has improved reaction velocity, has reduced delay time.
On the basis of technique scheme, further, the data collector of present embodiment also comprises a MUX 4 and signal amplification circuit 5, wherein the input end of MUX 4 connects multichannel analog signals, be used for selecting one the tunnel as the signal of gathering from the multichannel analog signals that receives, and the input end of signal amplification circuit 5 connects one tunnel simulating signal of MUX 4 outputs, be used for the simulating signal that MUX 4 is selected is carried out the signal processing and amplifying, so that the conversion of signals of analog to digital converter.
Fig. 3 is the hardware circuit diagram of the utility model data collector embodiment, as shown in Figure 3, in the present embodiment, MUX 1 ' is selected one tunnel simulating signal from the multi-analog signal after, transmit it in the amplifier 2 ', this simulating signal is behind the amplification of amplifier 2 ', send AD converter 3 ' to, AD converter 3 ' is digital signal with the analog signal conversion that receives and is input in the controller 4 ', controller 4 ' is by comparing this digital signal and the digital signal level of presetting, judge whether to send it to the computing machine of connection, promptly when the result who judges satisfies the condition that sends for digital signal, the digital signal that controller 4 ' will satisfy the transmission condition is temporarily stored in the data buffer 41 ', this data buffer is specifically as follows a FIFO buffer, the last computing machine that is connected with data collector passes through peripheral component interconnect standard (Peripheral Component Interconnect with it, abbreviation PCI) bus interface is read from data buffer 41 ', and it is carried out the operation of computing and data analysis.
Particularly; in the present embodiment; controller 4 ' can be a CPU (central processing unit) (CentralProcessing Unit; be called for short CPU); microprocessor (Micro Controller Unit; be called for short MCU); digital signal processor (Digital Signal Processing; be called for short DSP) or advanced RISC device (Advanced RISCI Machines; be called for short ARM); and can be integrated in field programmable logic array (FPLA) (Field Programmable Logic Array with data buffer FIFO; be called for short FPGA) in; and in the present embodiment; pci bus interface is not limited only to a kind of form of pci interface; it can also be the other forms of bus interface that is connected with computing machine simultaneously; USB (universal serial bus) bus (Universal Serial Bus for example; be called for short USB) interface; the RS232 bus interface; PCI expansion (PCI extensions for Instrumentation towards instrument system; be called for short PXI) bus interface; compact PCI (Compact Peripheral Component Interconnect; abbreviation CPCI) bus interface or PC104 bus interface etc.; present embodiment just illustrates at the data collector of PC bus interface, and the data collector that is applied to other forms of bus interface also belongs within the protection domain of the present utility model.
The data collector of present embodiment, by will through the digital signal after the AD conversion directly and the preset trigger level compare, and directly carry out the output of the digital signal after AD changes according to this comparative result, therefore need not to use special DA conversion chip so that the comparative level of analog comparator to be provided, also need not the user is analog comparator input reference source signal by the ATR passage, thereby reduced the production cost of data collector effectively, and for the user, use convenient; Further, AD converter need not just to carry out conversion work under the triggering control of controller, and after controller one was judged the trigger event generation, the digital signal after just directly will changing sent to computing machine, thereby has improved reaction velocity, has reduced delay time.
It should be noted that at last: above embodiment only in order to the explanation the technical solution of the utility model, is not intended to limit; Although with reference to previous embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of each embodiment technical scheme of the utility model.
Claims (8)
1. a data collector is characterized in that, comprising: analog to digital converter, controller and bus interface;
The input end of described analog to digital converter connects the simulating signal that collects;
The input end of described controller connects the digital signal of described analog to digital converter according to described simulating signal output, and the control end of described controller connects the predetermined level signal;
The input end that is used to export the described bus interface of described digital signal connects the described digital signal that described controller is exported according to the comparative result of described digital signal and described predetermined level signal.
2. data collector according to claim 1 is characterized in that, described controller comprises: signal comparator circuit and signal sending circuit;
Two input ends of described signal comparator circuit connect the digital signal and the described predetermined level signal of described analog to digital converter output respectively;
The input end of described signal sending circuit connects described digital signal, the control end of described signal sending circuit connects described signal comparator circuit according to the comparison to described digital signal and described predetermined level signal, the compare result signal of output, the output terminal of described signal sending circuit connects described bus interface, export described digital signal according to described compare result signal, whether the described compare result signal decision that described signal sending circuit receives according to control end sends to the digital signal after the described analog to digital converter conversion computing machine of connection by described bus interface.
3. data collector according to claim 2 is characterized in that,
Described signal sending circuit is specially first signal sending circuit, and when described compare result signal was represented described digital signal greater than described predetermined level signal, described first signal sending circuit exported described digital signal to described bus interface; When described compare result signal was represented described digital signal less than described predetermined level signal, described first signal sending circuit did not send described digital signal.
4. data collector according to claim 2 is characterized in that,
Described signal sending circuit is specially the secondary signal transtation mission circuit, and when described compare result signal was represented described digital signal less than described predetermined level signal, described secondary signal transtation mission circuit exported described digital signal to described bus interface; When described compare result signal was represented described digital signal greater than described predetermined level signal, described first signal sending circuit did not send described digital signal.
5. according to claim 1 or 3 or 4 described data collectors, it is characterized in that, also comprise: MUX and signal amplification circuit;
The input end of described MUX connects multichannel analog signals;
The input end of described signal amplification circuit connects the road simulating signal that described MUX is selected from described multichannel analog signals, the output terminal of described signal amplification circuit connects the input end of described analog to digital converter, described signal amplification circuit carries out the signal processing and amplifying with the simulating signal that described MUX is selected, so that the conversion of signals of described analog to digital converter.
6. data collector according to claim 1 is characterized in that, described bus interface is specially pci bus interface, usb bus interface, PXI bus interface, cpci bus interface, PCI04 bus interface.
7. data collector according to claim 1 is characterized in that, described controller specifically is CPU (central processing unit), microprocessor, digital signal processor or advanced RISC device.
8. data collector according to claim 2 is characterized in that, described signal comparator circuit is specially a digital signal comparator circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009201731475U CN201540469U (en) | 2009-08-24 | 2009-08-24 | Data acquiring device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009201731475U CN201540469U (en) | 2009-08-24 | 2009-08-24 | Data acquiring device |
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| CN201540469U true CN201540469U (en) | 2010-08-04 |
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| CN2009201731475U Expired - Fee Related CN201540469U (en) | 2009-08-24 | 2009-08-24 | Data acquiring device |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102707653A (en) * | 2012-06-07 | 2012-10-03 | 中国科学院安徽光学精密机械研究所 | High precision intelligent gain multipath data collecting system |
| CN102769457A (en) * | 2011-05-06 | 2012-11-07 | 北京旋极信息技术股份有限公司 | Fault injection method and device of transistor-transistor logic |
| CN104157126A (en) * | 2014-08-26 | 2014-11-19 | 广州华欣电子科技有限公司 | Signal acquisition method and device having multi-channel signal acquisition |
| CN105653105A (en) * | 2014-11-14 | 2016-06-08 | 上海东软载波微电子有限公司 | Touch control chip and data acquisition method thereof |
| CN109188985A (en) * | 2018-10-23 | 2019-01-11 | 国家地质实验测试中心 | Instrument state monitoring device |
| CN109347954A (en) * | 2018-10-18 | 2019-02-15 | 中国人民解放军战略支援部队航天工程大学 | A kind of bullet arrow polymorphic type signal acquisition and processing apparatus based on a variety of buses |
| CN109411436A (en) * | 2018-09-05 | 2019-03-01 | 湖北三江航天险峰电子信息有限公司 | A kind of 64 road analog acquisition chip bgas |
| CN109813520A (en) * | 2019-03-25 | 2019-05-28 | 中国人民解放军国防科技大学 | Flight pneumatic data acquisition system |
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2009
- 2009-08-24 CN CN2009201731475U patent/CN201540469U/en not_active Expired - Fee Related
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102769457A (en) * | 2011-05-06 | 2012-11-07 | 北京旋极信息技术股份有限公司 | Fault injection method and device of transistor-transistor logic |
| CN102769457B (en) * | 2011-05-06 | 2015-03-11 | 北京旋极信息技术股份有限公司 | Fault injection method and device of transistor-transistor logic |
| CN102707653A (en) * | 2012-06-07 | 2012-10-03 | 中国科学院安徽光学精密机械研究所 | High precision intelligent gain multipath data collecting system |
| CN104157126A (en) * | 2014-08-26 | 2014-11-19 | 广州华欣电子科技有限公司 | Signal acquisition method and device having multi-channel signal acquisition |
| CN105653105A (en) * | 2014-11-14 | 2016-06-08 | 上海东软载波微电子有限公司 | Touch control chip and data acquisition method thereof |
| CN109411436A (en) * | 2018-09-05 | 2019-03-01 | 湖北三江航天险峰电子信息有限公司 | A kind of 64 road analog acquisition chip bgas |
| CN109411436B (en) * | 2018-09-05 | 2021-04-30 | 湖北三江航天险峰电子信息有限公司 | 64-channel analog quantity acquisition BGA (ball grid array) packaging chip |
| CN109347954A (en) * | 2018-10-18 | 2019-02-15 | 中国人民解放军战略支援部队航天工程大学 | A kind of bullet arrow polymorphic type signal acquisition and processing apparatus based on a variety of buses |
| CN109347954B (en) * | 2018-10-18 | 2021-08-06 | 中国人民解放军战略支援部队航天工程大学 | Rocket multi-type signal acquisition and processing device based on multiple buses |
| CN109188985A (en) * | 2018-10-23 | 2019-01-11 | 国家地质实验测试中心 | Instrument state monitoring device |
| CN109813520A (en) * | 2019-03-25 | 2019-05-28 | 中国人民解放军国防科技大学 | Flight pneumatic data acquisition system |
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