CN103455452A - Method, device and system for USB (universal serial bus) data acquisition - Google Patents
Method, device and system for USB (universal serial bus) data acquisition Download PDFInfo
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- CN103455452A CN103455452A CN2012101809226A CN201210180922A CN103455452A CN 103455452 A CN103455452 A CN 103455452A CN 2012101809226 A CN2012101809226 A CN 2012101809226A CN 201210180922 A CN201210180922 A CN 201210180922A CN 103455452 A CN103455452 A CN 103455452A
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Abstract
The invention discloses a method for USB (universal serial bus) data acquisition. The method includes the steps S1, storing data constantly acquired into a first SDRAM (synchronous dynamic random access memory) group; S2, judging whether the first SDRAM group is fully loaded or not, if yes, entering the step S3, and otherwise, returning to the step S1; S3, reading back data of the first SDRAM group, meanwhile, storing new data constantly acquired into a second SDRAM group; S4, judging whether the second SDRAM is fully loaded or not, if yes, entering the step S5, and if not, returning to the step S3; S5, reading back the data of the second SDRAM group. The invention further discloses a device and a system for the USB data acquisition. By adopting the SDRAM as a data cache, bandwidth and depth of data storage can be guaranteed, and hardware cost is greatly lowered.
Description
Technical field
The present invention relates to usb data and gather field, be specifically related to method, Apparatus and system that a kind of usb data gathers.
Background technology
USB, be the abbreviation of English Universal Serial BUS (USB (universal serial bus)), and its Chinese is referred to as " logical getting lines crossed, be an external bus standard, for being connected and communication of standard computer and external unit.It is the interfacing that is applied in the PC field.USB adopts quadded cable, and wherein two is for transmitting the serial-port of data, and another two provide power supply for downstream (Downstream) equipment, and at a high speed and need the peripheral hardware of high bandwidth, USB is the transmission data of 12Mbps at full speed; For the low speed peripheral hardware, USB transmits data with the transfer rate of 1.5Mbps.Usb bus can be according to peripheral hardware situation dynamic translation automatically in two kinds of transmission modes.USB is based on the bus of token.Be similar to the bus of token-ring network or FDDI based on token.USB master controller broadcast token, whether the address on bus in the equipment Inspection token conforms to self, by receiving or sending data to main frame, responds.USB manages the usb bus power supply by hang/recovery operation of support.The USB system adopts cascaded star topology, and this topology is comprised of three essential parts: main frame (Host), hub (Hub) and function device.
Existing a lot of ripe usb data acquisition system scheme, as simple use, the MCU with the USB controller can complete the usb data collection, although this scheme is with low cost simple in structure, but because the internal memory of MCU is less, travelling speed is slower, therefore picking rate and transmission are all very limited, are difficult to reply data acquisition demand at a high speed.Usb data acquisition system scheme comparatively commonly used is the structure of fpga chip+USB controller+SRAM, wherein: FPGA (Field-Programmable Gate Array), it is field programmable gate array, it is the product further developed on the basis of the programming devices such as PAL, GAL, CPLD, it occurs as a kind of semi-custom circuit in special IC (ASIC) field, both solve the deficiency of custom circuit, overcome again the limited shortcoming of original programming device gate circuit number; SRAM is the abbreviation of English Static RAM, and it is a kind of internal memory with static access facility, does not need refresh circuit can preserve the data of its storage inside.This scheme can realize data acquisition at a high speed, but, along with improving constantly that storage depth is required, the cost of SRAM will increase with index law.
Summary of the invention
In order to solve above technical matters, the invention provides method, Apparatus and system that a kind of usb data gathers.
The invention discloses a kind of method that usb data gathers, comprising:
The data that S1. will constantly collect are stored in first group of SDRAM;
S2. judge whether described first group of SDRAM is filled with, if, enter step S3, if not, return to step S1;
S3. described first group of SDRAM data are read back,, the new data constantly collected is stored in second group of SDRAM simultaneously;
S4. judge whether described second group of SDRAM is filled with, if, enter step S5, if not, return to step S3;
S5. described second group of SDRAM data are read back.
In the method gathered at usb data of the present invention, also comprise step between described step S2 and S3: first group of SDRAM of S21. set is filled with sign.
In the method gathered at usb data of the present invention, also comprise between described step S3 and S4 that step: S31. removes first group of SDRAM and is filled with sign.
In the method gathered at usb data of the present invention, also comprise step between described step S4 and S5: second group of SDRAM of S41. set is filled with sign.
In the method gathered at usb data of the present invention, also comprise after described step S5 that step: S6. removes second group of SDRAM and is filled with and indicates and return to step S1.
The invention discloses the device that a kind of usb data gathers, comprising:
First group of SDRAM unit: for the data that will constantly collect, be stored in first group of SDRAM;
Whether first group of SDRAM is filled with judging unit: be connected with described first group of SDRAM unit, be filled with for judging described first group of SDRAM;
First group of SDRAM data read back and second group of SDRAM unit, is filled with judging unit with described first group of SDRAM and is connected, and for described first group of SDRAM data are read back,, the new data constantly collected is stored in second group of SDRAM simultaneously;
Whether second group of SDRAM is filled with judging unit, with described first group of SDRAM, reads back and second group of SDRAM unit is connected, for judging described second group of SDRAM, be filled with;
Second group of SDRAM data unit that reads back, be filled with judging unit with described second group of SDRAM and be connected, for described second group of SDRAM data are read back.
In the device gathered at usb data of the present invention, in described first group of SDRAM data, read back and second group of SDRAM unit and first group of SDRAM are filled with between judging unit and also have first group of SDRAM set unit, for set, first group of SDRAM is filled with sign; Read back and second group of SDRAM unit and second group of SDRAM are filled with between judging unit and also have first group of clear bit location of SDRAM in described first group of SDRAM data, for removing first group of SDRAM, be filled with sign.
In the device gathered at usb data of the present invention, described second group of SDRAM is filled with judging unit and second group of SDRAM data and reads back between unit and also have second group of SDRAM set unit, be filled with sign for second group of SDRAM of set, also there is second group of clear bit location of SDRAM after described second group of SDRAM data are read back unit, for removing second group of SDRAM, be filled with and indicate and be back to first group of SDRAM unit.
The invention discloses the system that a kind of usb data gathers, comprise the USB controller, for the usb data controller of controlling data acquisition, storage and transmission, first group of SDRAM, second group of SDRAM, for the signal conditioning circuit of level conversion, described USB controller, first group of SDRAM, second group of SDRAM, signal conditioning circuit all are connected with the usb data controller, the described usb data controling appliance device that the described usb data of requirement 6 gathers of having the right.
In the system gathered at usb data of the present invention, described first group of SDRAM, second group of SDRAM at least comprise a slice SDRAM chip.
Implement method, Apparatus and system that a kind of usb data of the present invention gathers, there is following useful technique effect:
Two groups of SDRAM can alternately store data, the transmission that has guaranteed data acquisition and data does not produce the read/write conflict of SDRAM simultaneously while carrying out, can complete very easily the continuous data collection, the more effective storage resources that utilizes PC, realize long data recording.Owing to adopting SDRAM as data buffer storage, guaranteed on the one hand the bandwidth of data storages and the degree of depth of data storage, greatly reduce on the other hand the cost of hardware.
The accompanying drawing explanation
Fig. 1 is the method flow diagram that embodiment of the present invention usb data gathers;
Fig. 2 is the device block scheme that embodiment of the present invention usb data gathers;
Fig. 3 is the system block diagram that embodiment of the present invention usb data gathers;
The functional block diagram that Fig. 4 is FPGA of the present invention.
Embodiment
By describing technology contents of the present invention, structural attitude in detail, being realized purpose and effect, below in conjunction with embodiment and coordinate accompanying drawing to be explained in detail.
SDRAM:: Synchronous Dynamic Random Access Memory, synchronous DRAM, synchronously refer to Memory need of work synchronous clock, the transmission of inner order and the transmission of data all be take it as benchmark; Dynamically refer to that storage array need to constantly refresh to guarantee that data do not lose; Refer to that at random data are not that linearity is stored successively, but free assigned address carries out reading and writing data.
The structure of this programme is fpga chip+high speed USB 2.0 controllers+two groups of SDRAM; also comprise in addition signal conditioning circuit; wherein FPGA has been used for collection, the storage of data and the bridge joint transmitted with the USB2.0 controller; high speed USB 2.0 controllers are for realizing the USB high speed data transfer between PC and data acquisition system (DAS); two groups of data that SDRAM collects for replacing buffer memory; signal conditioning circuit directly is connected with the input signal of outside; one side is for the protection of the IO of fpga chip, on the other hand for level conversion.
Refer to the method for Fig. 1, the collection of a kind of usb data, comprising:
The data that S1. will constantly collect are stored in first group of SDRAM;
S2. judge whether described first group of SDRAM is filled with, if, enter step S3, if not, return to step S1;
S3. described first group of SDRAM data are read back,, the new data constantly collected is stored in second group of SDRAM simultaneously;
S4. judge whether described second group of SDRAM is filled with, if, enter step S5, if not, return to step S3;
S5. described second group of SDRAM data are read back.
Preferably, also comprise step between described step S2 and S3: first group of SDRAM of S21. set is filled with sign, also comprises between described step S3 and S4 that step: S31. removes first group of SDRAM and is filled with sign.
Preferably, also comprise step between described step S4 and S5: second group of SDRAM of S41. set is filled with sign, also comprises that step: S6. removes second group of SDRAM and is filled with and indicates and return to step S1 after described step S5.
The operation of system is controlled by USB by PC, and PC can read the running state information of acquisition system and collect data by USB, and simultaneously, PC also can send instruction to acquisition system by USB.In data acquisition, at first PC sends startup command to acquisition system, acquisition system receives the data that can arrive to storage of collected in first group of SDRAM after startup command, after first group of SDRAM is filled with, acquisition system meeting set " first group of SDRAM is filled with sign ", then store data in second group of SDRAM, after second group of SDRAM is filled with, acquisition system can set " second group of SDRAM is filled with sign ".Meanwhile, PC can read back the data in first group of SDRAM after inquiring " first group of SDRAM is filled with sign ", then remove " first group of SDRAM is filled with sign ", PC is after inquiring " second group of SDRAM is filled with sign ", data in second group of SDRAM can be read back, then remove " second group of SDRAM is filled with sign ".So repeatedly carry out, if PC inquires " first group of SDRAM is filled with sign " and " second group of SDRAM is filled with sign " simultaneously, mean that the storage speed of data is greater than the transmission speed of USB, PC now can provide miscue.By rational design, as appropriate selection sample frequency, improve the means such as USB transfer efficiency, can avoid the generation of this kind of situation.
In this programme, the collection of data, storage, the control of SDRAM and system complete by FPGA by the logical process work such as mutual between high speed USB 2.0 interfaces and PC, so FPGA is the core of whole system.
Refer to the device of Fig. 2, the collection of a kind of usb data, comprising:
First group of SDRAM unit 10, first group of SDRAM are filled with judging unit 20, first group of SDRAM data are read back and second group of SDRAM unit 30, second group of SDRAM are filled with judging unit 40, the second group of SDRAM data unit 50 that reads back.
First group of SDRAM unit 10: for the data that will constantly collect, be stored in first group of SDRAM;
Whether first group of SDRAM is filled with judging unit 20: be connected with first group of SDRAM unit 10, be filled with for judging described first group of SDRAM;
First group of SDRAM data read back and second group of SDRAM unit 30, is filled with judging unit 20 with first group of SDRAM and is connected, and for described first group of SDRAM data are read back,, the new data constantly collected is stored in second group of SDRAM simultaneously;
Whether second group of SDRAM is filled with judging unit 40, with first group of SDRAM, reads back and second group of SDRAM unit 30 is connected, for judging described second group of SDRAM, be filled with;
Second group of SDRAM data unit 50 that reads back, be filled with judging unit 40 with second group of SDRAM and be connected, for described second group of SDRAM data are read back.
Preferably, first group of SDRAM data, read back and second group of SDRAM unit 30 and first group of SDRAM are filled with between judging unit 20 and also have first group of SDRAM set unit 25, for set, first group of SDRAM is filled with sign; First group of SDRAM data are read back and second group of SDRAM unit 30 and second group of SDRAM are filled with between judging unit 40 and also have first group of clear bit location 35 of SDRAM, for removing first group of SDRAM, are filled with sign.
Preferably, second group of SDRAM is filled with judging unit 40 and second group of SDRAM data and reads back between unit 50 and also have second group of SDRAM set unit 45, be filled with sign for second group of SDRAM of set, also there is second group of clear bit location 60 of SDRAM after second group of SDRAM data read back unit 50, for removing second group of SDRAM, be filled with and indicate and be back to first group of SDRAM unit.
Refer to the system of Fig. 3, the collection of a kind of usb data, comprise USB controller 100, for the usb data controller 200 of controlling data acquisition, storage and transmission, first group of SDRAM300, second group of SDRAM400, for the signal conditioning circuit 500 of level conversion, USB controller 100, first group of SDRAM300, second group of SDRAM400, signal conditioning circuit 500 all are connected with usb data controller 200, and usb data controller 200 has the device that above-mentioned usb data gathers.
Wherein, usb data controller 200 is fpga chip, the collection of data, storage, and the control of SDRAM and system complete by FPGA by the logical process work such as mutual between high speed USB 2.0 interfaces and PC, therefore FPGA is the core of whole system, shown in functional block diagram Fig. 4 of FPGA.
Wherein the effect of USB interface bridge module 201 is by together with the internal logic bridge joint of high speed USB 2.0 controllers and FPGA, thereby host computer is sent to the instruction transformation of getting off, becomes corresponding logical signal, controls the state of the inner modules of FPGA.The effect of waveform sampling module 202 is sampled to input signal with specific sampling rate, and the data that sampling is obtained are delivered to waveform memory module 203.Waveform memory module 203 is for controlling the storage of sampled data.First group of sdram controller 204 and second group of sdram controller 205 are for sequential such as the refreshing of the outer two groups of independence SDRAM of control strip, precharge, reading and writing.
To sum up, the structure that this programme is fpga chip+high speed USB 2.0 controllers+two groups of SDRAM, FPGA can realize various digital units circuit efficiently, flexibly, and fpga chip can reshuffle, system upgrade is very convenient.High speed USB 2.0 controllers can be with the transfer rate of 480Mbps by the data transmission that collects to PC, two groups of SDRAM can alternately store data, the transmission that has guaranteed data acquisition and data does not produce the read/write conflict of SDRAM simultaneously while carrying out, can complete very easily consecutive data set, the more effective storage resources that utilizes PC, realize long data recording.Owing to adopting SDRAM as data buffer storage, guaranteed on the one hand the bandwidth of data storages and the degree of depth of data storage, greatly reduce on the other hand the hardware cost of scheme.
The characteristics of the technical program design are:
1, the characteristics that notebook data acquisition scheme structure is " fpga chip+high speed USB 2.0 controllers+two groups of SDRAM " two groups of SDRAM are that address bus, data bus and the control signal of these two groups of SDRAM are all independently, every group of SDRAM can independently control and access, one group of SDRAM may be a slice SDRAM chip, may be also multi-disc SDRAM chip.
2, the working method of notebook data acquisition system is, hocket data storage and reading of two groups of SDRAM, the data where data acquisition system (DAS) is organized in SDRAM by " first group of SDRAM is filled with sign " and " second group of SDRAM is filled with sign " sign can be read by PC, PC need to read by these two sign judgements the data of where organizing in SDRAM, after PC has read the data in SDRAM, can removing will be indicated accordingly.
3, the operation of notebook data acquisition system is controlled and to be completed by high speed USB 2.0 interfaces by PC, and the data that collect are read by high speed USB 2.0 interfaces by PC, and the further analytical work of the data that collect is completed by PC.
Implement method, Apparatus and system that a kind of usb data of the present invention gathers, there is following useful technique effect:
Two groups of SDRAM can alternately store data, the transmission that has guaranteed data acquisition and data does not produce the read/write conflict of SDRAM simultaneously while carrying out, can complete very easily consecutive data set, the more effective storage resources that utilizes PC, realize long data recording.Owing to adopting SDRAM as data buffer storage, the bandwidth of data storages and the degree of depth of data storage have been guaranteed on the one hand, the hardware cost greatly reduced on the other hand.
The above is described embodiments of the invention by reference to the accompanying drawings; but the present invention is not limited to above-mentioned embodiment; above-mentioned embodiment is only schematic; rather than restrictive; those of ordinary skill in the art is under enlightenment of the present invention; not breaking away from the scope situation that aim of the present invention and claim protect, also can make a lot of forms, within these all belong to protection scope of the present invention.
Claims (10)
1. the method that usb data gathers, is characterized in that, comprising:
The data that S1. will constantly collect are stored in first group of SDRAM;
S2. judge whether described first group of SDRAM is filled with, if, enter step S3, if not, return to step S1;
S3. described first group of SDRAM data are read back,, the new data constantly collected is stored in second group of SDRAM simultaneously;
S4. judge whether described second group of SDRAM is filled with, if, enter step S5, if not, return to step S3;
S5. described second group of SDRAM data are read back.
2. the method that usb data according to claim 1 gathers is characterized in that also comprise step between described step S2 and S3: first group of SDRAM of S21. set is filled with sign.
3. the method that usb data according to claim 2 gathers, is characterized in that, also comprises between described step S3 and S4 that step: S31. removes first group of SDRAM and is filled with sign.
4. the method that usb data according to claim 1 gathers is characterized in that also comprise step between described step S4 and S5: second group of SDRAM of S41. set is filled with sign.
5. the method that usb data according to claim 4 gathers, is characterized in that, also comprises after described step S5 that step: S6. removes second group of SDRAM and is filled with and indicates and return to step S1.
6. the device that usb data gathers, is characterized in that, comprising:
First group of SDRAM unit: for the data that will constantly collect, be stored in first group of SDRAM;
Whether first group of SDRAM is filled with judging unit: be connected with described first group of SDRAM unit, be filled with for judging described first group of SDRAM;
First group of SDRAM data read back and second group of SDRAM unit, is filled with judging unit with described first group of SDRAM and is connected, and for described first group of SDRAM data are read back,, the new data constantly collected is stored in second group of SDRAM simultaneously;
Whether second group of SDRAM is filled with judging unit, with described first group of SDRAM, reads back and second group of SDRAM unit is connected, for judging described second group of SDRAM, be filled with;
Second group of SDRAM data unit that reads back, be filled with judging unit with described second group of SDRAM and be connected, for described second group of SDRAM data are read back.
7. the device that usb data according to claim 6 gathers, it is characterized in that, in described first group of SDRAM data, read back and second group of SDRAM unit and first group of SDRAM are filled with between judging unit and also have first group of SDRAM set unit, for set, first group of SDRAM is filled with sign; Read back and second group of SDRAM unit and second group of SDRAM are filled with between judging unit and also have first group of clear bit location of SDRAM in described first group of SDRAM data, for removing first group of SDRAM, be filled with sign.
8. the device that usb data according to claim 6 gathers, it is characterized in that, described second group of SDRAM is filled with judging unit and second group of SDRAM data and reads back between unit and also have second group of SDRAM set unit, be filled with sign for second group of SDRAM of set, also there is second group of clear bit location of SDRAM after described second group of SDRAM data are read back unit, for removing second group of SDRAM, be filled with and indicate and be back to first group of SDRAM unit.
9. the system that a usb data gathers, comprise the USB controller, for the usb data controller of controlling data acquisition, storage and transmission, first group of SDRAM, second group of SDRAM, for the signal conditioning circuit of level conversion, described USB controller, first group of SDRAM, second group of SDRAM, signal conditioning circuit all are connected with the usb data controller, it is characterized in that the described usb data controling appliance device that the described usb data of requirement 6 gathers of having the right.
10. the system that usb data according to claim 9 gathers is characterized in that described first group of SDRAM, second group of SDRAM at least comprise a slice SDRAM chip.
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| CN101404760A (en) * | 2008-10-28 | 2009-04-08 | 大连理工大学 | Self-perception portable image wireless monitoring equipment and use method thereof |
| CN101408902A (en) * | 2008-10-06 | 2009-04-15 | 南京大学 | Method for acquiring and transporting high speed data based on FPGA and USB bus |
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| CN101185580A (en) * | 2006-11-15 | 2008-05-28 | 深圳迈瑞生物医疗电子股份有限公司 | Method and apparatus for gathering ultrasonic diagnosis system high-speed radio-frequency echo wave data |
| CN101408902A (en) * | 2008-10-06 | 2009-04-15 | 南京大学 | Method for acquiring and transporting high speed data based on FPGA and USB bus |
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