CN101345201A - 晶片的加工方法 - Google Patents
晶片的加工方法 Download PDFInfo
- Publication number
- CN101345201A CN101345201A CNA200810128063XA CN200810128063A CN101345201A CN 101345201 A CN101345201 A CN 101345201A CN A200810128063X A CNA200810128063X A CN A200810128063XA CN 200810128063 A CN200810128063 A CN 200810128063A CN 101345201 A CN101345201 A CN 101345201A
- Authority
- CN
- China
- Prior art keywords
- wafer
- recess
- back side
- grinding
- wiring layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000003672 processing method Methods 0.000 title claims abstract description 12
- 238000000227 grinding Methods 0.000 claims abstract description 79
- 238000012545 processing Methods 0.000 claims abstract description 29
- 238000005530 etching Methods 0.000 claims abstract description 24
- 230000015572 biosynthetic process Effects 0.000 claims description 42
- 229910052751 metal Inorganic materials 0.000 claims description 33
- 239000002184 metal Substances 0.000 claims description 33
- 238000000034 method Methods 0.000 claims description 23
- 239000004065 semiconductor Substances 0.000 abstract description 49
- 235000012431 wafers Nutrition 0.000 description 105
- 230000000149 penetrating effect Effects 0.000 description 17
- 239000004575 stone Substances 0.000 description 14
- 239000000463 material Substances 0.000 description 11
- 229910001651 emery Inorganic materials 0.000 description 10
- 238000009826 distribution Methods 0.000 description 9
- 238000005520 cutting process Methods 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 230000007246 mechanism Effects 0.000 description 7
- 230000002093 peripheral effect Effects 0.000 description 7
- 229920005989 resin Polymers 0.000 description 6
- 239000011347 resin Substances 0.000 description 6
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 238000005259 measurement Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- ZZUFCTLCJUWOSV-UHFFFAOYSA-N furosemide Chemical compound C1=C(Cl)C(S(=O)(=O)N)=CC(C(O)=O)=C1NCC1=CC=CO1 ZZUFCTLCJUWOSV-UHFFFAOYSA-N 0.000 description 3
- 238000009434 installation Methods 0.000 description 3
- 238000011068 loading method Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000001179 sorption measurement Methods 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 238000004512 die casting Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 241001391944 Commicarpus scandens Species 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 239000004698 Polyethylene Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000006061 abrasive grain Substances 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000007767 bonding agent Substances 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000002788 crimping Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- -1 polyethylene Polymers 0.000 description 1
- 229920000573 polyethylene Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- QQONPFPTGQHPMA-UHFFFAOYSA-N propylene Natural products CC=C QQONPFPTGQHPMA-UHFFFAOYSA-N 0.000 description 1
- 125000004805 propylene group Chemical group [H]C([H])([H])C([H])([*:1])C([H])([H])[*:2] 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Grinding And Polishing Of Tertiary Curved Surfaces And Surfaces With Complex Shapes (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
本发明提供一种晶片的加工方法,其在背面具有再配线层的半导体芯片等器件的制造过程中,确保了单片化为器件之前的薄晶片的刚性。此外,在晶片的阶段,在芯片的背面精确地形成再配线层。通过磨削和蚀刻仅使晶片(1)背面的、与形成有半导体芯片(3)的器件形成区域(4)对应的区域变薄,以在背面形成凹部(11)。通过凹部(11)周围的环状凸部(12)确保了晶片(1)的刚性,可安全且容易地进行移送到在背面侧形成再配线层(40)的工序时的处理。
Description
技术领域
本发明涉及在从形成多个具有贯穿的金属电极的半导体芯片等器件的晶片获得器件时对晶片实施的加工方法,特别涉及在背面形成再配线层的技术。
背景技术
在近年的半导体器件技术中,被称为CSP(芯片尺寸封装)的与半导体芯片大致相同尺寸的半导体封装在实现高密度化和小型化、薄型化方面被有效利用。作为此类半导体封装的制造方法有这样的方法:在被称为内插板的封装基板上层叠半导体芯片,在进行将内插板和半导体芯片的电极之间用金属线电连接起来的引线接合之后,将半导体芯片树脂模铸在内插板上。有时在半导体芯片的表面(器件元件面)上形成再配线层,该再配线层在作为半导体芯片的集合体的晶片阶段针对各半导体芯片进行设置。
在用引线接合将电极之间连接起来的情况下,存在在封入模铸用的树脂时金属线变形而发生断线或短路、或者残留在模铸树脂中的空气在加热时膨胀而导致破损的问题。于是,开发了这样的技术:在半导体芯片上设置贯穿厚度方向的与自身的电极导通的贯穿电极,在半导体芯片的层叠的同时接合贯穿电极进行电连接(参照专利文献1)。此外,半导体芯片是将表面侧朝向内插板等按压来进行层叠,所以存在形成于表面的再配线层受到压力而受到压坏等损害的危险。因此,提出了不是在表面而是在背面形成再配线层以减轻作用在再配线层上的载荷的技术(参照专利文献2)。
专利文献1:日本特开2005-136187号公报
专利文献2:日本特开2003-017495号公报
但是,为了如上述那样实现小型化、薄型化,半导体芯片在晶片阶段加工得极薄。因此,当在薄化后将晶片移送到再配线层形成工序,或者移送到其后的分割工序时,晶片的处理非常困难,而且,由于易于破裂,还存在成品率下降的问题。
发明内容
因此,本发明的目的是提供一种晶片的加工方法,其在背面具有再配线层的半导体芯片等器件的制造过程中,使单片化为器件之前的阶段中的薄晶片的处理变得容易,能够顺利地在工序之间进行移送,能够在晶片的阶段在器件的背面精确地形成再配线层,并由此实现生产率和成品率的提高。
本发明是一种在晶片背面形成再配线层的晶片的加工方法,上述晶片在表面具有形成有多个器件的大致圆形形状的器件形成区域、和围绕该器件形成区域的外周剩余区域,其特征在于,上述晶片的加工方法具有以下工序:电极埋设工序,在器件形成区域将多个金属电极从器件的表面埋设到大于等于器件厚度的深度处;背面凹部形成工序,仅使上述晶片背面的与器件形成区域对应的区域变薄,以在该背面形成凹部,从而使金属电极从该凹部的底面露出,并且在外周剩余区域形成向背面侧突出的环状凸部;以及再配线层形成工序,在凹部底面的除了所露出的金属电极之外的部分形成绝缘膜,并且形成再配线层。在本发明的背面凹部形成工序中进行的针对晶片背面的凹部形成手段可举出磨削加工及蚀刻加工,也有时采用这些手段中的一方或将两方组合来进行加工。
根据本发明,在背面凹部形成工序中,仅使与需要薄化的器件形成区域对应的背面部分变薄,并且其周围的外周剩余区域在保留原厚度的状态下形成环状凸部,由此,得到虽然已变薄但通过环状凸部确保了刚性的晶片。因此,能安全且容易地进行背面凹部形成工序之后的将晶片移送到再配线层形成工序时的处理、和该再配线层形成工序本身。其结果为,能够在晶片的阶段在器件背面精确地形成再配线层,并且可防止晶片破裂所致的成品率的下降。此外,可安全且容易地进行再配线层形成工序以后的直到将晶片分割而单片化为各器件为止的工序之间的处理以及这些工序本身,因此,可实现器件的生产率和成品率的提高。
根据本发明,仅对与器件形成区域对应的区域进行晶片的薄化,将周围的外周剩余区域形成为较厚的环状凸部,由此能够确保晶片的刚性,其结果为,具有能够在背面精确地形成再配线层,并且可实现器件的生产率和成品率的提高。
附图说明
图1是利用本发明的一个实施方式方法加工的晶片的立体图,放大部分表示金属电极露出于半导体芯片的表面的状态。
图2是以(a)~(h)的顺序表示用一个实施方式的方法加工的晶片的剖视图。
图3是通过保护带粘贴工序在表面粘贴有保护带的晶片的图,(a)是立体图,(b)是侧视图。
图4是在背面凹部形成工序中使用的磨削装置的立体图。
图5是表示上述磨削装置的磨削单元的图,(a)是立体图,(b)是侧视图。
图6是形成有凹部的晶片背面的立体图,(a)表示精磨削后,(b)表示蚀刻后。
图7是表示蚀刻出凹部的晶片的背面侧的俯视图,放大部分表示贯穿电极(背面侧电极部)露出于半导体芯片的表面的状态。
图8是表示层叠有半导体芯片的半导体封装的示例的剖视图。
标号说明
1:半导体晶片;3:半导体芯片(器件);4:器件形成区域;5:外周剩余区域;8:金属电极;8A:贯穿电极;8a:背面侧电极部;11:凹部;11a:凹部的底面;12:环状凸部;20:表面侧再配线层;30:背面侧绝缘膜;40:背面侧再配线层;60:磨削装置。
具体实施方式
下面参照附图来说明本发明的一个实施方式。
(1)半导体晶片
图1中的标号1表示作为半导体芯片的原材料的圆盘状的半导体晶片。该晶片1是硅晶片等,厚度为例如600μm左右。在晶片1的表面,由格子状的分割预定线2划分有多个矩形形状的半导体芯片(器件)3。在这些半导体芯片3的表面,形成有IC和LSI等未图示的电子电路。
多个半导体芯片3形成在与晶片1同心的大致圆形形状的器件形成区域4中。器件形成区域4占据晶片1的大部分,在该器件形成区域4周围的晶片1的外周部成为不形成半导体芯片3的环状的外周剩余区域5。此外,在晶片1周面的固定部位,形成有表示半导体的结晶方位的V字状的切口(凹口)6。该凹口6形成在外周剩余区域5内。如图1中右侧的放大图所示,在各半导体芯片3的预定部位埋设有露出于表面的多个金属电极8。
下面对下述方法进行说明:在晶片1中埋设金属电极8后,对晶片1进行薄化加工,使金属电极8的端部露出于背面而成为贯穿电极,并在该贯穿电极上连接再配线。
(2)金属电极埋设工序
在形成于图2(a)所示的晶片1上的半导体芯片3的表面,如图2(b)所示,形成多个金属电极8,使它们与晶片1的表面大致共面,而且比半导体芯片3的厚度t略深。这些金属电极8这样形成:在穿孔设置于晶片1表面的通孔9的内表面上形成绝缘膜,在该通孔9内,埋设铜等电极用金属。通孔9通过在用抗蚀图形形成了掩模的晶片1的表面上实施等离子蚀刻的方法、或激光照射等方法而形成。金属电极8通过利用CVD(Chemical Vapor Deposition:化学气相沉积)的成膜法等而形成在通孔9内。
接着,如图2(c)所示,在晶片1的表面上形成表面侧再配线层20。表面侧再配线层20由金属制的配线21、将晶片1的表面及配线21覆盖的绝缘膜22构成,上述金属制的配线21由将所选择的金属电极彼此连接起来的铝等形成。在形成表面侧再配线层20时,首先,通过利用CVD的成膜法等来实施配线21,接着形成绝缘膜22。绝缘膜22的材料适于使用聚酰亚胺等绝缘性树脂、SOG(Spin On Glass:旋涂玻璃)、BPSG(Boron Phosphorous Silicate Glass:硼磷硅玻璃)等玻璃系氧化膜。在树脂或SOG的情况下,通过这样的旋涂法来形成:在旋转的晶片表面的中心滴下液体材料,借助于离心力使液体材料遍及整个表面。此外,BPSG通过CVD等成膜法形成。绝缘膜22的厚度为例如5~10μm左右。
(3)保护带粘贴工序
接着,对于如上述那样形成有表面侧再配线层20的晶片1,实施如下加工:将背面侧除去预定厚度,使晶片1变薄至与目标厚度即制造出的半导体芯片3的厚度相当。在薄化加工时,如图3所示,预先在晶片1的表面上粘贴保护带10。作为保护带10,优选使用例如在厚度为大约100~200μm的聚乙烯等基材的单面上涂抹有大约10~20μm的丙烯系等的粘接剂的带等。粘贴保护带10的目的是为了在下面的背面凹部形成工序中防止晶片1表面侧的半导体芯片3的电子电路和表面侧再配线层20受到损伤。
(4)背面凹部形成工序
本实施方式中的晶片1的薄化不是将整个背面除去预定厚度来使整体变薄,而是仅对与器件形成区域4对应的区域进行。因此,在晶片1的背面,如图6所示,在器件形成区域4形成凹陷的凹部11的同时,在该凹部11周围的外周剩余区域5,形成了保留原晶片厚度的环状凸部12。在本实施方式中,凹部11的形成主要通过磨削加工来进行,通过蚀刻加工来除去剩余的一点厚度。
如图2(d)所示,晶片背面的磨削量并未到达金属电极8的下端(晶片背面侧的端部),而为这样的程度:在金属电极8的下端与背面即凹部11的底面11a之间留有一点厚度,在该阶段不使金属电极8露出于背面。接下来,如图2(e)所示,对凹部11的底面11a进行蚀刻加工,使金属电极8的下端从底面11a稍微突出。由此,使金属电极8成为贯穿晶片1表面和背面的贯穿电极8A。贯穿电极8A向背面侧的突出量为例如5μm左右,该突出部分成为背面侧电极部8a。
(4-1)背面磨削
在仅对晶片背面的与器件形成区域4对应的区域进行磨削以形成凹部11时,优选使用图4所示的磨削装置60的横向进给磨削加工。通过该磨削装置60,使形成有表面侧再配线层20的表面侧吸附在真空卡盘式的卡盘工作台70的吸附面上,以保持晶片1,并通过两个磨削单元(粗磨削用和精磨削用)80A、80B对晶片背面依次进行粗磨削和精磨削。
磨削装置60的构成及动作如下所述。
磨削装置60具有长方体状的基座61,多个晶片1以表面侧朝上的状态层叠收纳在供给盒62内,供给盒62可自由装卸地设置在该基座61上的预定部位。用输送机械手63从该供给盒62拉出一块晶片1,该晶片1以表背颠倒、使背面朝上的状态装载于定位工作台64上,并在这里定位于固定的位置。
在基座61上,设有在R方向上被驱动旋转的旋转工作台73,再有,在该旋转工作台73的外周部分在周向上隔开相等间隔地配置有多个(该情况下为三个)圆盘状的卡盘工作台70。这些卡盘工作台70被支撑成能够以Z方向(铅直方向)为旋转轴自由旋转,并且由未图示的驱动机构驱动旋转。
在定位工作台64上进行了定位的晶片1通过供给臂65被从定位工作台64举起,并以粘贴有保护带10的表面侧朝下的状态呈同心状地装载于真空运转的一个卡盘工作台70上。如图5(b)所示,卡盘工作台70在框体71的中央上部形成有由多孔质部件构成的圆形的吸附部72,晶片1以保护带10紧贴且背面露出的状态吸附、保持于该吸附部72的上表面。因此,晶片1的表面侧的半导体芯片3的电子电路和表面侧再配线层20由保护带10保护,可防止受到损伤。
通过旋转工作台73向R方向旋转预定角度,保持于卡盘工作台70上的晶片1被送至粗磨削用磨削单元80A下方的一次加工位置,在该位置由磨削单元80A对背面进行粗磨削。接着,再次通过旋转工作台73向R方向旋转预定角度,晶片1被送至精磨削用磨削单元80B下方的二次加工位置,在该位置处由磨削单元80B对背面进行精磨削。
各磨削单元80A、80B分别安装在立设于基座61里侧端部上的、并列于X方向上的立柱66A、66B的前表面。各磨削单元80A、80B相对于各立柱66A、66B的安装构造相同,并且在X方向上左右对称。因此,参照图4以精磨削侧为代表来说明其安装构造。
精磨削侧立柱66B的前表面66b是相对于基座61的上表面垂直的面,但形成为随着从X方向的中央朝向端部而向里侧以预定角度倾斜地后退的斜度面。该斜度面66b(在粗磨削侧的立柱66A中为斜度面66a)的水平方向即倾斜方向,设定为与将定位于一次加工位置的卡盘工作台70的旋转中心和旋转工作台73的旋转中心连接起来的线平行。
在斜度面66b(66a)上设有与其倾斜方向平行的上下一对导引部91,在该导引部91上可自由滑动地安装有X轴滑动体92。该X轴滑动体92,通过由伺服电动机93驱动的未图示的滚珠丝杠式进给机构,而沿导引部91往复移动。X轴滑动体92的往复方向与导引部91的延伸方向、即斜度面66b(66a)的倾斜方向平行。
X轴滑动体92的前表面是沿X·Z方向的面,各磨削单元80A、80B可分别在Z方向(铅直方向)上自由升降地设置在其前表面上。这些磨削单元80A、80B通过Z轴滑动体95可自由滑动地安装在导引部94上,导引部94设置于X轴滑动体92的前表面,并且沿Z方向延伸。而且,各磨削单元80A、80B,通过由伺服电动机96驱动的滚珠丝杠式进给机构97,而通过Z轴滑动体95在Z方向上升降。
各磨削单元80A、80B为相同构成,安装的磨石通过为不同的粗磨削用和精磨削用而被区别开来。如图5所示,磨削单元80A、80B具有:轴向在Z方向上延伸的圆筒状的主轴壳体81;同轴且可自由旋转地支撑在该主轴壳体81内的主轴82;固定在主轴壳体81的上端部、且驱动主轴82旋转的电动机83;以及同轴地固定在主轴82的下端的圆盘状的凸缘84。而且,在凸缘84上安装有磨轮85。
磨轮85通过在环状、且下表面形成为圆锥状的框架86的下表面,呈环状地排列并紧固多个磨石87而构成。作为磨石87的下端面的刀头设定成与主轴82的轴向正交。磨石87例如使用在玻璃质的结合材料中混合金刚石磨粒而成形并进行烧结而成的磨石。
在粗磨削用的磨削单元80A上安装的磨石87使用含有例如粒度为大约320#~400#的较粗磨粒的磨石。此外,在精磨削用的磨削单元80B上安装的磨石87使用含有例如粒度为大约2000#~8000#的较细磨粒的磨石。在各磨削单元80A、80B上设有磨削水供给机构(省略图示),该磨削水供给机构供给用于磨削面的冷却和润滑或者磨削屑的排出的磨削水。
磨轮85的磨削外径、即环状地排列的多个磨石87的外周缘的直径,设定为比晶片1的半径稍小、与器件形成区域4的半径相等的程度。该尺寸设定是为了:使磨石87的刀头通过呈同心状地保持在旋转的卡盘工作台70上的晶片1的旋转中心,且该刀头的外周缘与器件形成区域4的外周缘(器件形成区域4和外周剩余区域5的分界)一致地通过器件形成区域4的外周缘,从而能够仅磨削与器件形成区域4对应的区域,以形成图6所示的凹部11。
如上所述,将定位于上述一次加工位置及二次加工位置的各卡盘工作台70的旋转中心和旋转工作台73的旋转中心之间连接起来的方向(下面称为轴间方向)设定为分别与立柱66A、66B的前表面66a、66b的倾斜方向、即导引部91的延伸方向平行。而且,各磨削单元80A、80B以下述方式进行位置设定:磨轮85的旋转中心(主轴82的轴心)分别正落在将定位于对应的加工位置(在粗磨削单元80A中为一次加工位置,在精磨削单元80B中为二次加工位置)的卡盘工作台70的旋转中心和旋转工作台73的旋转中心连接起来的轴间方向上。因此,磨削单元80A、80B设定成当通过每个X轴滑动体92沿导引部91移动时,磨轮85的旋转中心沿轴间方向移动。
晶片1在一次加工位置由粗磨削单元80A进行背面磨削,并且在二次加工位置由精磨削单元80B进行背面磨削。背面磨削首先通过使X轴滑动体92移动来调整磨削单元80A(80B)的轴间方向位置,与晶片1的背面相对的磨轮85的磨削外径定位于与晶片1的器件形成区域4的半径对应的凹部形成位置。该凹部形成位置是磨石87的刀头通过晶片1的旋转中心附近和器件形成区域4的外周缘的位置,该情况下,该凹部形成位置比晶片1的旋转中心靠向旋转工作台73的外周侧。晶片1的背面磨削通过以下方式进行:在这样将磨轮85保持在凹部形成位置后,使卡盘工作台70旋转以使晶片1自转,通过进给机构97使磨削单元80A(80B)向下方进给,同时将旋转的磨轮85的磨石87压靠在晶片1的背面上。磨轮85的转速大约为2000~5000rpm。
在粗磨削单元80A所进行的粗磨削中,仅磨削晶片1背面的与器件形成区域4对应的区域,如图5所示,磨削部分形成为凹部11,在该凹部11的周围,在外周剩余区域5的厚度保留原样的情况下形成了环状凸部12。在粗磨削中磨削的器件形成区域4变薄至例如精磨削后的厚度+大约20~40μm的厚度。然后,在精磨削中磨削剩余的厚度,晶片1的与器件形成区域4对应的区域变薄至目标厚度。
在粗磨削后的晶片1中,如图5(a)所示,在凹部11的底面11a上,残留有磨削条痕14a,该磨削条痕14a呈放射状地描绘很多弧的图案。该磨削条痕14a是磨石87中的磨粒进行破碎加工的轨迹,是含有微裂纹等的机械损伤层。虽然粗磨削所致的磨削条痕14a会通过精磨削除去,但如图6(a)所示,在凹部11的底面11a上通过精磨削而残留有新的磨削条痕14b。
在晶片1的背面磨削时,粗磨削和精磨削皆通过在各加工位置附近设置的厚度测定量规75来测定晶片厚度,同时,根据该测定值来控制磨削量。厚度测定量规75由基准侧高度量规76和可动侧高度量规77的组合构成,基准侧高度量规76的探头接触卡盘工作台70的框体71的上表面,可动侧高度量规77的探头接触被磨削面(该情况下为晶片1的凹部11的底面11a),通过比较两个高度量规76、77的高度测定值,来逐一测定背面磨削中的晶片1的厚度。晶片1的背面磨削是一边利用厚度测定量规75来测定晶片1的厚度来一边进行的,且根据该测定值来控制进给机构97对磨轮85的进给量。
在从粗磨削经精磨削将晶片1的器件形成区域4变薄至目标厚度之后,如下述那样转移至晶片1的回收。首先,精磨削单元80B上升以从晶片1退避,另一方面,通过使旋转工作台73向R方向旋转预定角度,使晶片1从供给臂65回到装载在卡盘工作台70上的装卸位置。在该装卸位置停止卡盘工作台70的真空运转,接着,晶片1通过回收臂67输送到旋转式清洗装置68进行清洗、干燥处理,然后,由输送机械手63移送收纳到回收盒69内。
(4-2)背面蚀刻
在如上述那样在晶片1的背面形成凹部11、仅使与器件形成区域4对应的区域变薄之后,接着对所形成的凹部11实施蚀刻来除去凹部11的底面11a的很小的厚度。由此,如图2(e)所示,使金属电极8向背面侧突出而成为贯穿电极8A,并且形成背面侧电极部8a。作为蚀刻的方法,优选使用了使硅等晶片材料发生反应而除去、而金属电极8(贯穿电极8A)不反应不被除去的气体的等离子蚀刻。
等离子蚀刻通过使放入晶片1的容器内成为通常公知的硅蚀刻用气体(例如CF4、SF6等氟系气体)氛围、并进行等离子放电来进行。在进行等离子蚀刻时,如果保护带10具有足够的耐热性,则保护带10可原样地粘贴在晶片1的表面上,但如果没有足够的耐热性,则要事先剥离保护带10。
通过此类对凹部11的蚀刻加工,如图2(e)及图7所示,贯穿电极8A从晶片1的凹部11的底面11a突出,从而形成背面侧电极部8a。此外,与此同时,如图6(b)所示,除去伴有在精磨削后仍残留在背面的磨削条痕14b的机械损伤层。机械损伤层会导致应力集中而引起破裂和破损,但由于机械损伤层被除去,所以不易发生此类不良情况,晶片1或单片化的半导体芯片3的强度提高。再有,作为使金属电极8向晶片背面突出,并且用于除去凹部11的底面11a的磨削条痕14b的蚀刻,并不限于上述等离子蚀刻,也可实施通常公知的湿式蚀刻。
(5)背面侧再配线层的形成工序
(5-1)背面侧绝缘膜的形成
接下来,在晶片1的背面形成再配线层。如图2(f)所示,首先在凹部11的底面11a上形成背面侧绝缘膜30。背面侧绝缘膜30可通过与上述表面侧再配线层20的绝缘膜22同样的材料及方法来形成。背面侧绝缘膜30覆盖凹部11的底面11a的、除了背面侧电极部8a之外的整个面,而且形成为背面侧电极部8a的至少端面会露出的厚度。因此,背面侧绝缘膜30的厚度根据背面侧电极部8a的高度而为大约5~10μm。
(5-2)背面侧再配线层的层叠
在形成背面侧绝缘膜30之后,接着在该背面侧绝缘膜30上形成背面侧再配线层40进行层叠。形成背面侧再配线层40的要领与表面侧再配线层20一样,首先,如图2(g)所示,用配线41将所选择的背面侧电极部8a之间连接起来,接下来,如图2(h)所示,形成绝缘膜42,并覆盖配线41和背面侧绝缘膜30,从而形成由配线41和绝缘膜42构成的背面侧再配线层40。背面侧再配线层40形成为一层,或者根据需要而形成为多层(在图2(h)中为两层)。
(6)凸起的形成工序
在如此般形成背面侧再配线层40之后,接下来如图2(h)所示那样设置与背面侧再配线层40的配线41导通、并从凹部11的底面11a突出的多个凸起15。凸起15通过例如焊锡球的压接来设置。
(7)半导体芯片
以上单片化为半导体芯片3之前进行的对晶片1的加工结束,然后,在将晶片1的保护带10剥离之后,利用切割机或激光加工等手段切断分割预定线2,使全部的半导体芯片3被单片化。要分割晶片1可举出这样的方法:将粘贴有保护带10的表面侧保持于卡盘工作台等保持构件上,使形成有凹部11的背面露出,从该背面侧利用红外线显微镜等来识别分割预定线2,沿分割预定线2从背面侧进行切割或照射激光来进行切断。根据该方法,由于将平坦的表面侧保持在保持构件上,所以可使晶片相对于保持构件的保持构造与以往一样,具有比吸附形成有凹部11的背面侧简便的优点。单片化而成的半导体芯片3例如层叠在内插板上或者将半导体芯片3彼此层叠,来制造出层叠型的半导体封装。
图8表示将晶片1分割而得到的一个半导体芯片3层叠在内插板16上、并用树脂17模铸而成的半导体封装的构成例。通过一边对埋设在内插板16中的贯穿电极施加超声波振动一边压紧凸起15,半导体芯片3在电连接的同时进行层叠状态的固定。在内插板16的背面形成有凸起18作为针对未图示的基板的电接点。
(8)实施方式的作用效果
根据上述实施方式的晶片的加工方法,在背面凹部形成工序中,仅使与需要薄化的器件形成区域4对应的背面部分变薄,其周围的外周剩余区域5在保留原厚度的状态下形成环状凸部12。由此,虽然晶片1的器件形成区域4变薄,但通过环状凸部12确保了刚性。因此,可安全且容易地进行将晶片1移送到背面凹部形成工序后的向再配线层形成工序时的处理、和该再配线层形成工序本身。其结果为,可在晶片阶段在半导体芯片3的背面精确地形成背面侧再配线层40,并可防止晶片1破裂所致的成品率的下降。
此外,还可安全且容易地进行背面侧再配线层的形成工序以后的、直到分割晶片1以单片化为各半导体芯片3为止的工序间的处理、以及这些工序本身,因此,可实现半导体芯片3的生产率和成品率的提高。
在上述实施方式中,在晶片背面形成凹部11是利用磨削装置60的磨削加工和蚀刻加工的组合,起初通过磨削加工形成大部分的深度,通过接下来的蚀刻加工来除去些许厚度以使背面侧电极部8a突出。本发明除了此类磨削加工和蚀刻加工的组合之外,还包括仅使用磨削加工或仅使用蚀刻加工来在晶片背面形成凹部。
在仅用磨削加工形成凹部11的情况下,由于被磨削面平坦,所以即便能使贯穿电极8A的下端面与凹部11的底面11a共面地露出,却不能形成从底面11a突出的背面侧电极部8a。因此,在通过磨削加工使贯穿电极8A的下端面露出之后,在除了该贯穿电极8A以外的底面11a上形成背面侧绝缘膜30,接下来,在由该背面侧绝缘膜30所包围的、底部为贯穿电极8A的露出面的孔内,通过CVD或蒸镀、溅射、镀等手段来埋设成为背面侧电极部的金属,从而能够形成与贯穿电极8A导通的背面侧电极部8a。
此外,在仅通过蚀刻加工形成凹部11的情况下,有这样的方法:使用将晶片1的材料和金属电极8两者都蚀刻掉、并且通过使晶片1的蚀刻速度快可形成突出的背面侧电极部8a的蚀刻气体或蚀刻液。此外,通过下述方法也可形成背面侧电极部8a突出的凹部11:先使用晶片1的材料和金属电极8的蚀刻速度相同的第一蚀刻材料来形成凹部11的大部分的深度之后,替换为仅将晶片1蚀刻数μm的第二蚀刻材料。
Claims (2)
1.一种晶片的加工方法,其是在晶片的背面形成再配线层的方法,上述晶片在表面具有形成有多个器件的大致圆形形状的器件形成区域、和围绕该器件形成区域的外周剩余区域,其特征在于,上述晶片的加工方法具有以下工序:
电极埋设工序,在器件形成区域将多个金属电极从器件的表面埋设到大于等于器件厚度的深度处;
背面凹部形成工序,仅使上述晶片背面的与上述器件形成区域对应的区域变薄,以在该背面形成凹部,从而使上述金属电极从该凹部的底面露出,并且在上述外周剩余区域形成向背面侧突出的环状凸部;以及
再配线层形成工序,在上述凹部底面的除了所露出的上述金属电极之外的部分形成绝缘膜,并且形成再配线层。
2.根据权利要求1所述的晶片的加工方法,其特征在于,
在上述背面凹部形成工序中进行的针对晶片背面的凹部形成手段是磨削加工和/或蚀刻加工。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007-183935 | 2007-07-13 | ||
JP2007183935A JP2009021462A (ja) | 2007-07-13 | 2007-07-13 | ウェーハの加工方法 |
JP2007183935 | 2007-07-13 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101345201A true CN101345201A (zh) | 2009-01-14 |
CN101345201B CN101345201B (zh) | 2012-10-17 |
Family
ID=40247160
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200810128063XA Active CN101345201B (zh) | 2007-07-13 | 2008-07-10 | 晶片的加工方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7816264B2 (zh) |
JP (1) | JP2009021462A (zh) |
CN (1) | CN101345201B (zh) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102299065A (zh) * | 2010-05-21 | 2011-12-28 | 株式会社迪思科 | 晶片的加工方法 |
CN103219281A (zh) * | 2013-05-03 | 2013-07-24 | 华进半导体封装先导技术研发中心有限公司 | 一种tsv背面露头工艺 |
CN103383919A (zh) * | 2012-05-02 | 2013-11-06 | 英飞凌科技股份有限公司 | 用于制造芯片封装件的方法 |
CN103811536A (zh) * | 2014-01-24 | 2014-05-21 | 南通富士通微电子股份有限公司 | 圆片级封装工艺晶圆减薄结构 |
CN107104117A (zh) * | 2012-07-30 | 2017-08-29 | 索尼公司 | 固态成像装置、制造固态成像装置的方法以及电子设备 |
CN107639541A (zh) * | 2016-07-22 | 2018-01-30 | 株式会社迪思科 | 磨削装置 |
CN109719374A (zh) * | 2017-10-31 | 2019-05-07 | 株式会社迪思科 | 被加工物的加工方法 |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5718342B2 (ja) * | 2009-10-16 | 2015-05-13 | エンパイア テクノロジー ディベロップメント エルエルシー | 半導体ウェーハにフィルムを付加する装置および方法ならびに半導体ウェーハを処理する方法 |
JP2011091293A (ja) * | 2009-10-26 | 2011-05-06 | Disco Abrasive Syst Ltd | ウエーハの加工方法 |
JP2011108746A (ja) | 2009-11-13 | 2011-06-02 | Disco Abrasive Syst Ltd | ウエーハの加工方法 |
JP5578936B2 (ja) * | 2010-05-21 | 2014-08-27 | 株式会社ディスコ | ウエーハの加工方法 |
JP2011243901A (ja) * | 2010-05-21 | 2011-12-01 | Disco Abrasive Syst Ltd | ウエーハの加工方法 |
JP5780828B2 (ja) * | 2011-05-18 | 2015-09-16 | 株式会社ディスコ | ウエーハの加工方法 |
JP5995599B2 (ja) * | 2012-08-06 | 2016-09-21 | 株式会社ディスコ | ウエーハの加工方法 |
JP5995598B2 (ja) * | 2012-08-06 | 2016-09-21 | 株式会社ディスコ | ウエーハの加工方法 |
JP5995596B2 (ja) * | 2012-08-06 | 2016-09-21 | 株式会社ディスコ | ウエーハの加工方法 |
JP5995597B2 (ja) * | 2012-08-06 | 2016-09-21 | 株式会社ディスコ | ウエーハの加工方法 |
US9553021B2 (en) * | 2012-09-03 | 2017-01-24 | Infineon Technologies Ag | Method for processing a wafer and method for dicing a wafer |
US9355882B2 (en) | 2013-12-04 | 2016-05-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Transfer module for bowed wafers |
KR102258739B1 (ko) * | 2014-03-26 | 2021-06-02 | 삼성전자주식회사 | 하이브리드 적층 구조를 갖는 반도체 소자 및 그 제조방법 |
JP6332556B2 (ja) * | 2015-04-20 | 2018-05-30 | 三菱電機株式会社 | 半導体装置の製造方法 |
JP6561966B2 (ja) * | 2016-11-01 | 2019-08-21 | トヨタ自動車株式会社 | 半導体装置の製造方法 |
JP2021005621A (ja) * | 2019-06-26 | 2021-01-14 | 株式会社ディスコ | ウエーハの加工方法 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11312680A (ja) * | 1998-04-30 | 1999-11-09 | Nec Corp | 配線の形成方法 |
JP3792954B2 (ja) * | 1999-08-10 | 2006-07-05 | 株式会社東芝 | 半導体装置の製造方法 |
JP2002299196A (ja) * | 2001-03-30 | 2002-10-11 | Toshiba Corp | 半導体製造用基板 |
JP2003017495A (ja) | 2001-07-04 | 2003-01-17 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP3895987B2 (ja) * | 2001-12-27 | 2007-03-22 | 株式会社東芝 | 半導体装置およびその製造方法 |
US6884717B1 (en) * | 2002-01-03 | 2005-04-26 | The United States Of America As Represented By The Secretary Of The Air Force | Stiffened backside fabrication for microwave radio frequency wafers |
TWI229435B (en) * | 2002-06-18 | 2005-03-11 | Sanyo Electric Co | Manufacture of semiconductor device |
TWI227550B (en) * | 2002-10-30 | 2005-02-01 | Sanyo Electric Co | Semiconductor device manufacturing method |
JP2004221350A (ja) * | 2003-01-15 | 2004-08-05 | Seiko Epson Corp | 半導体チップ、半導体ウエハ、半導体装置及びその製造方法、回路基板並びに電子機器 |
JP2004281551A (ja) * | 2003-03-13 | 2004-10-07 | Toshiba Corp | 半導体基板及びその製造方法、半導体装置及びその製造方法、半導体パッケージ |
JP4340517B2 (ja) | 2003-10-30 | 2009-10-07 | Okiセミコンダクタ株式会社 | 半導体装置及びその製造方法 |
US7276787B2 (en) * | 2003-12-05 | 2007-10-02 | International Business Machines Corporation | Silicon chip carrier with conductive through-vias and method for fabricating same |
JP4307284B2 (ja) * | 2004-02-17 | 2009-08-05 | 三洋電機株式会社 | 半導体装置の製造方法 |
CN2779615Y (zh) * | 2005-01-25 | 2006-05-10 | 威盛电子股份有限公司 | 晶片封装体 |
JP2006269968A (ja) * | 2005-03-25 | 2006-10-05 | Sharp Corp | 半導体装置およびその製造方法 |
JP4579066B2 (ja) * | 2005-06-27 | 2010-11-10 | 株式会社ディスコ | ウエーハの加工方法 |
US7488680B2 (en) * | 2005-08-30 | 2009-02-10 | International Business Machines Corporation | Conductive through via process for electronic device carriers |
JP4927484B2 (ja) * | 2006-09-13 | 2012-05-09 | 株式会社ディスコ | 積層用デバイスの製造方法 |
-
2007
- 2007-07-13 JP JP2007183935A patent/JP2009021462A/ja active Pending
-
2008
- 2008-07-07 US US12/168,321 patent/US7816264B2/en active Active
- 2008-07-10 CN CN200810128063XA patent/CN101345201B/zh active Active
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102299065A (zh) * | 2010-05-21 | 2011-12-28 | 株式会社迪思科 | 晶片的加工方法 |
CN102299065B (zh) * | 2010-05-21 | 2015-08-19 | 株式会社迪思科 | 晶片的加工方法 |
CN103383919A (zh) * | 2012-05-02 | 2013-11-06 | 英飞凌科技股份有限公司 | 用于制造芯片封装件的方法 |
CN103383919B (zh) * | 2012-05-02 | 2016-12-28 | 英飞凌科技股份有限公司 | 用于制造芯片封装件的方法 |
CN107104117B (zh) * | 2012-07-30 | 2020-12-18 | 索尼公司 | 固态成像装置、制造固态成像装置的方法以及电子设备 |
CN107104117A (zh) * | 2012-07-30 | 2017-08-29 | 索尼公司 | 固态成像装置、制造固态成像装置的方法以及电子设备 |
CN103219281A (zh) * | 2013-05-03 | 2013-07-24 | 华进半导体封装先导技术研发中心有限公司 | 一种tsv背面露头工艺 |
CN103219281B (zh) * | 2013-05-03 | 2015-10-14 | 华进半导体封装先导技术研发中心有限公司 | 一种tsv背面露头工艺 |
CN103811536A (zh) * | 2014-01-24 | 2014-05-21 | 南通富士通微电子股份有限公司 | 圆片级封装工艺晶圆减薄结构 |
CN107639541A (zh) * | 2016-07-22 | 2018-01-30 | 株式会社迪思科 | 磨削装置 |
CN107639541B (zh) * | 2016-07-22 | 2021-05-25 | 株式会社迪思科 | 磨削装置 |
CN109719374A (zh) * | 2017-10-31 | 2019-05-07 | 株式会社迪思科 | 被加工物的加工方法 |
CN109719374B (zh) * | 2017-10-31 | 2022-11-04 | 株式会社迪思科 | 被加工物的加工方法 |
Also Published As
Publication number | Publication date |
---|---|
CN101345201B (zh) | 2012-10-17 |
US7816264B2 (en) | 2010-10-19 |
JP2009021462A (ja) | 2009-01-29 |
US20090017623A1 (en) | 2009-01-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101345201B (zh) | 晶片的加工方法 | |
JP2009010178A (ja) | ウェーハの加工方法 | |
JP4927484B2 (ja) | 積層用デバイスの製造方法 | |
JP5138325B2 (ja) | ウェーハの加工方法 | |
JP5755043B2 (ja) | 半導体ウエーハの加工方法 | |
JP2009004406A (ja) | 基板の加工方法 | |
JP2011096767A (ja) | ウエーハの加工方法 | |
TWI557790B (zh) | Wafer processing method | |
JP2011054808A (ja) | ウエーハの加工方法及び該加工方法により加工されたウエーハ | |
JP2011108746A (ja) | ウエーハの加工方法 | |
CN112071746B (zh) | 晶圆键合方法 | |
JP5441587B2 (ja) | ウエーハの加工方法 | |
JP2009094247A (ja) | ウェーハの洗浄装置および研削装置 | |
JP2011071288A (ja) | ウエーハの加工方法 | |
TWI805872B (zh) | 晶圓的加工方法 | |
JP2014053351A (ja) | ウエーハの加工方法 | |
JP2011071287A (ja) | ウエーハの加工方法 | |
JP7313775B2 (ja) | ウェーハの加工方法 | |
JP2007203432A (ja) | 基板の研削装置および研削方法 | |
JP2011071289A (ja) | ウエーハの加工方法 | |
JP2010093005A (ja) | ウエーハの加工方法 | |
JP2014053350A (ja) | ウエーハの加工方法 | |
JP2014053348A (ja) | ウエーハの加工方法 | |
JP2014053357A (ja) | ウエーハの加工方法 | |
CN116169034A (zh) | 封装器件的制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |