CN100585875C - Ldmos晶体管 - Google Patents
Ldmos晶体管 Download PDFInfo
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Abstract
一种LDMOS半导体晶体管结构,包括:具有第一导电类型的外延层(150)的基板(160);从该外延层表面延伸的第二导电类型的源极区域(114);在该外延层内的第二导电类型的轻掺杂漏极区域(136);正好位于该源极和漏极区域之间的沟道(118);以及布置在该沟道上方的在绝缘层内的栅极(120),其中该轻掺杂漏极区域包括第一导电类型的袋区(138),其中该袋区(138)从该外延层的表面延伸到该外延层内,覆盖毗邻该栅极的轻掺杂漏极区域的端部。
Description
技术领域
本发明涉及LDMOS晶体管结构。
背景技术
LDMOS晶体管结构被广泛用作诸如高压MOS场效应晶体管的许多类型的晶体管应用的半导体器件。LDMOS晶体管包括轻掺杂漏区以增强击穿电压。由于漏极内的轻掺杂区域,LDMOS因此包含更高的导通电阻。
图1示出了一种典型的LDMOS晶体管。晶片包括例如其顶部上沉积了外延层1的p型基板13。层1包括注入到表面内以分别提供源极和漏极区域的n型导电类型区域2、4、15。外延层1通常覆盖有例如氧化硅的绝缘介电层7,其中多晶硅栅极8布置成覆盖漏极4、15和源极2之间的沟道。本示例LDMOS晶体管中的漏极包括第一区域15,该第一区域为n+掺杂并包括通过绝缘体层7内的窗口与布置在区域15上方的漏电极12的连接。该n+型区域被较轻掺杂的n-型区域4包围,该n-型区域4延伸至栅极8下方,从而定义源极和漏极区域之间的沟道。在该晶体管的源极侧上提供了p+掺杂的下沉(sink)14,该p+掺杂的下沉14从外延层1的表面向下延伸到基板以提供背侧源极接触。接触11将源极区域2与下沉14连接。
击穿电压和导通电阻之间的相互关系涉及需要保持在半导体的临界电场以下以避免击穿的由pn结定义的最大电场。该最大电场是由例如NMOS场效应晶体管中n-掺杂漏极的掺杂水平定义。此外,在晶体管在大部分时间内被驱动为导通的应用中,长时间导通状态会引起显著的热载流子注入,导致DC参数漂移。对于LDMOS晶体管结构而言,这是非常普遍的问题,因为在LDD晶体管中n型注入剂量增大以降低导通电阻,由此导致随时间出现更高的结电场和热电子注入。
发明内容
根据本申请,引入了一种新的晶体管结构。例如,LDMOS半导体晶体管结构包括具有第一导电类型的外延层的基板、从该外延层表面延伸的为第二导电类型的源极区域、在该外延层内的为第二导电类型的轻掺杂漏极区域、位于该源极和漏极区域之间的沟道、以及布置在该沟道上方的在绝缘层内的栅极,其中第一导电类型的注入区域被提供为从外延层的表面延伸到外延层内,覆盖毗邻栅极的轻掺杂漏极区域的端部。
该轻掺杂漏极区域可包括漏极接触下方的第一区域和从该第一重掺杂区域沿朝向栅极的方向延伸的第二区域,其中第二区域的掺杂轻于第一区域。该半导体晶体管结构可进一步包括包围该第一重掺杂区域的第三区域,其中该第三区域的掺杂轻于该第一重掺杂区域但重于该第二区域。该半导体晶体管结构可进一步包括从源极区域延伸到外延层底部的第一导电类型的下沉结构。该基板可以是重掺杂的。注入区域可具有约0.5μm的近似水平长度。该注入区域可具有约0.6μm的峰值浓度近似垂直长度。该注入区域可以与轻掺杂漏极区域部分交叠。该半导体晶体管可进一步包含至少部分包围源极区域并在沟道内延伸的第一导电类型的阱。该注入区域可与该阱部分交叠。第一导电类型可以是p型且该第二导电类型为n型,或者相反。该注入区域可以横向扩散。轻掺杂漏极区域可包含:第二导电类型的第一区域,用于建立与电极的接触;掺杂轻于第一区域的第二导电类型的第二区域,掩埋在该外延层内并从该第一区域沿着朝向栅极的方向水平地延伸;第二导电类型的第三区域,掺杂轻于第二区域,从外延层表面垂直地并从该第二区域水平地延伸直到栅极下方;第一导电类型的顶层,从该外延层的表面延伸到第二区域;以及第一导电类型的底层,从该第二区域延伸到该外延层内。该第三区域可包括从该第二区域水平地朝该栅极延伸的第二导电类型的第一子区域,以及从该外延层表面垂直地并从该第一子区域水平地延伸直到栅极下方的第二导电类型的第二子区域。该第一子区域的掺杂可以轻于第二区域,第二子区域的掺杂轻于该第一子区域。该第一子区域的掺杂可以轻于第二区域,第一和第二子区域交叠,且第一子区域部分地掺杂轻于第二子区域。该半导体晶体管结构可进一步包括从漏电极延伸较第一区域更深入外延层的第二导电类型的电压终端。该第二区域可具有0.5-3μm的近似水平长度。该半导体晶体管结构可进一步包括布置在漏电极和栅电极之间位于绝缘层顶部上的场电极(field plate),该场电极至少部分覆盖该栅电极。
LDMOS半导体晶体管结构还可包括用于形成具有外延层的基板的第一导电类型的装置、用于形成从外延层表面延伸的源极的第二导电类型的装置、用于在所述外延层内形成轻掺杂漏极区域的第二导电类型的装置、位于所述用于形成漏极的装置和所述用于形成源极的装置之间的沟道、用于在绝缘层内形成布置在所述沟道上方的栅极的装置、以及用于形成从外延层表面延伸到外延层内、与毗邻该栅极的该轻掺杂漏极区域端部交叠并在所述沟道一部分内延伸的第一导电类型的注入区域的装置。
该轻掺杂漏极区域可进一步包括用于形成漏极接触下方的第一重掺杂区域的装置,以及用于形成从所述第一区域沿朝向该栅极的方向延伸的第二区域的装置,其中该第二区域的掺杂轻于该第一区域。该注入区域可以与用于形成第二区域的装置部分交叠。该半导体晶体管可进一步包括用于形成所述第一导电类型的阱的装置,该装置至少部分包围所述用于形成该源极的装置并在所述沟道内延伸。该注入区域可以与所述阱部分交叠。用于形成该注入区域的装置可导致所述注入的横向扩散。
一种LDMOS晶体管结构的制造方法,该晶体管结构具有基板和第一导电类型的外延层,包括步骤:在外延层内形成第二导电类型的源极区域和轻掺杂漏极区域,至少形成覆盖该源极和轻掺杂漏极区域之间的沟道的栅电极,形成覆盖该晶体管结构的表面的光致抗蚀剂层,在该光致抗蚀剂层内打开露出毗邻栅极的轻掺杂漏极区域端部的窗口,以及通过该窗口注入第一导电类型的袋区。
该窗口可以露出部分栅电极。该窗口可以具有约0.5μm的优选水平尺寸。该注入步骤可以产生峰值浓度垂直长度为0.6μm的袋。该漏极区域可包括漏极接触下方的第一重掺杂区域,以及从该第一重掺杂区域沿朝向栅极的方向延伸的第二区域,其中该第二区域的掺杂轻于该第一重掺杂区域。该轻掺杂漏极区域还可包括包围该第一重掺杂区域的第三区域,其中该第三区域的掺杂轻于该第一重掺杂区域但重于该第二区域。该袋区可部分交叠第二轻掺杂漏极区域。该袋区还可以在栅极下方横向扩散。该方法可进一步包括形成第一导电类型的阱的步骤,该阱至少部分包围该源极区域并在所述沟道内延伸。该注入区域可部分交叠该阱。第一导电类型的下沉结构可以形成于该外延层内,从该源极区域延伸到外延层底部。该基板可以是重掺杂。第一导电类型可以是p型,第二导电类型为n型,或者相反。
此外,LDMOS半导体结构可包括具有第一导电类型的外延层的基板;第二导电类型的从该外延层表面延伸的源极区域;包括漏极接触下方的第一区域和从该第一区域沿着朝向栅极的方向延伸的第二区域的第二导电类型的该外延层内的轻掺杂漏极区域,其中该第二区域的掺杂轻于该第一区域;位于该漏极和源极区域之间的沟道;以及布置在该沟道上方的绝缘层内的栅极,其中该轻掺杂漏极区域包括从该外延层的表面延伸到该外延层内,覆盖毗邻该栅极的轻掺杂漏极区域端部的第一导电类型的注入区域。
该半导体晶体管结构可进一步包括包围该第一区域的第三区域,其中该第三区域的掺杂轻于该第一区域但重于该第二区域。该半导体晶体管结构可进一步包括从源极区域延伸到外延层底部的第一导电类型的下沉结构。基板可以是重掺杂。注入区域可具有约0.5μm的近似水平长度。该注入区域可具有约0.6μm的峰值浓度近似垂直长度。第一导电类型可以是p型且该第二导电类型为n型,或者相反。该半导体晶体管结构可进一步包括布置在漏电极和栅电极之间位于绝缘层顶部上的场电极,该场电极至少部分覆盖该栅电极。该注入区域可以与该第二区域部分交叠。该半导体晶体管结构可进一步包括至少包围该源极区域并在该沟道内延伸的第一导电类型的阱。该注入区域可与该阱部分交叠。
本公开的其他技术优点通过下述图示、说明书和权利要求对于本领域技术人员而言将变得显而易见。本申请的各种实施例仅获得所述优点的子集。并非所有优点对于这些实施例而言都是必不可少的。
附图说明
通过参考结合附图进行的下述描述,可以获得对本公开及其优点的更彻底的理解,附图中相同的参考数字表示相同的特征,其中:
图1为包括根据现有技术的晶体管结构的半导体晶片的局部剖面视图;
图2为包括根据本申请的晶体管结构的半导体晶片的局部剖面视图;
图3A-3B为根据本申请的晶体管结构制造工艺的示例性步骤;
图4示出了根据本发明的另一个实施例的局部剖面视图;
图5示出了根据本申请的晶体管结构的工艺模拟的曲线图;
图6示出了根据本发明的又一个实施例的局部剖面视图;以及
图7示出了根据本发明的再一个实施例的局部剖面视图。
具体实施方式
参照图示,现在将描述本申请的示例性实施例。图2描述根据本发明示例性实施例的改进的晶体管结构。在p+基板160顶部上布置有p-外延层150。例如,该基板可以重掺杂有1018至1019/cm3,外延层可较轻掺杂有1014至1015/cm3。沿着外延层150的顶面,源极区域114从栅极120的源极侧横向地延伸到电极或金属互连110。该源极区域可以嵌入在p阱118内,如图2所示。接触110连接相反掺杂的源极区域114和p+下沉区域112。p+下沉区域112从源极区域114到达p+基板160。源极金属接触(未示出)可以沿晶片整个背侧放置。此外,绝缘体层140置于外延层150的顶面上,并包括栅极120以及分别用于漏极和源极电极130、110的窗口。在绝缘体层140的顶部上通常沉积有钝化层(未示出)。
该改进的晶体管结构包括具有LDD区域的漏极区域,该LDD区域包含从栅极120下方延伸到漏电极130下方的重掺杂区域132的第一轻掺杂区域136,如图2所示。LDD区域的其他实施例也是可能的。区域136的注入剂量例如可以为2E1012/cm2,对于区域132,例如可以为5E1015/cm2。
可以使用其他类型的LDD晶体管,例如诸如图4所示的具有多个渐变层的晶体管。该实施例与图2所示实施例类似。因此,相似区域使用相同数字。在该示范性实施例中,渐变结由多层结构形成。n-掺杂的第一区域136从栅极120下方延伸靠近漏极接触电极130。从该n-掺杂区域136以及在漏极接触电极130下方还跟随有n+掺杂区域132,该n+掺杂区域132大约与层136一样深延伸到外延层内。然而,在另一个实施例中,n-掺杂区域134可包围n+区域132,并更深入外延层150。区域132的注入剂量例如可以是5E1015/cm2,区域134为4E1012/cm2,区域136可以同样例如为2E1012/cm2。
此外,对该示例性实施例,p型掺杂袋注入138从外延层150顶面延伸到外延层150内。该p型掺杂袋注入138与在面向漏电极130的栅极120那侧上的第一漏极区域136的端部交叠。p型掺杂袋注入138的另一侧到达被栅极120覆盖的沟道。对于低频类型的晶体管以及对于具有长的栅极/沟道长度的晶体管,该p型掺杂袋注入138可以深入沟道内,直至接触p型阱118或者甚至与该p型阱118交叠。然而,如虚线所示,在高频类型应用中以及对于具有短的栅极/沟道长度的晶体管,该p型掺杂袋注入138在优选实施中实际上可以与该p型阱118交叠。该袋注入138更深入外延层150,由此形成阻挡。该注入138可以补偿10-20%的N-LDD剂量136,局部抑制了漏极到沟道结电场以及热电子注入(injection),由此减小沟道长度调制以及任意类型的DC偏置电流随时间的漂移。热电子注入是一种局域化效应,通常发生在栅极的漏极侧0.5μm距离之内。该注入区域可进一步具有约0.6μm的峰值浓度近似垂直长度。电阻Rdson为在漏极尺度的几个微米上的分布值。通过优化p型袋注入条件,例如通过使用5E1011/cm2的注入剂量和180KeV硼或任意其他合适的p型注入物并通过将区域136的n型注入LDD注入剂量增大到例如>2E1012/cm2,则可以实现功率LDMOS晶体管的Rdson显著减小以及RF性能改善,而不增大DC偏置电流随时间的漂移。由于硼的扩散特性和高的注入能量,这种类型的注入尤其可以实现更横向的扩散分布。
图5示出了一种可能的示例性深袋注入垂直分布。该深的P型袋注入掺杂分布补偿10-20%的N-LDD剂量,且与P型外延层/N-LDD结相比,将P型袋/N-LDD结移至更靠近表面。该深的P型袋注入将在栅极的漏极侧下方横向扩散,以抑制随着漏极偏压Vds增大耗尽区生长到沟道内,因此抑制沟道长度调制和DC参数漂移。
p型袋138可以使用例如图3a-b所示的自对准工艺有利地注入。图3a示出了例如具有注入漏极区域136的LDD晶体管的一些部分。在后续步骤期间,可以形成源极和漏极金属接触110和130以及栅极120(未示出)。因此,薄氧化物层覆盖外延层150的表面。在下一个步骤中,在覆盖栅极120和金属接触110及130的光致抗蚀剂层300内形成如图3b所示的窗口。该窗口优选地不覆盖栅极120的一小部分,在该示例中该部分形成后续注入步骤的左阻挡。然而,该窗口还可以仅延伸到栅极的左边缘。该窗口具有约0.5μm的优选水平尺寸。因此,该袋将最少地影响Rdson,同时仍通过减小结电场有效抑制热电子注入。
图6示出了类似图4所示实施例的又一个实施例。此外,类似元件使用相同数字。除了图4所示结构之外,该实施例另外包括布置为至少部分覆盖栅电极的场电极(field plate)170。为此,该场电极170置于覆盖栅电极的氧化物140顶上。在该实施例中,该场电极170还到达栅电极右边以覆盖p型袋138。
图7示出了根据本发明的改进晶体管结构的再一个实施例。p型外延层521布置在p+基板520的顶部上。同样,基板可以重掺杂例如1019/cm3,且该外延层可较轻掺杂1015/cm3。沿着外延层521的顶面,源极区域523从栅极526源极侧横向地延伸到电学浮置电极或金属互连524。该电学浮置接触524连接相反掺杂的源极区域523和p+下沉区域522。p+下沉区域522从源极区域523到达p+基板520。源极金属接触(未示出)沿晶片整个背侧放置。同样,绝缘体层525置于外延层521的顶面上,并包括栅极526以及分别用于漏极和源极电极524、534的窗口。在绝缘体层525的顶部上通常沉积有钝化层(未示出)。
该改进的晶体管结构包括具有多层布置的漏极区域,如图7所示。在该示例性实施例中,渐变超级结(superjunction)由该多层结构形成。n-掺杂的第一相对短的形成区域(resulting region)533从栅极526下方延伸到漏极接触电极534。第二n-掺杂区域532位于该短的n-掺杂区域533和漏极接触电极534之间,该第二n-掺杂区域532延伸到外延层521中更深处。在一个实施例中,获得了掺杂浓度增大的从区域533到区域528的渐变掺杂浓度。然而,其他实施也是可能的。在一个优选实施例中,区域532的最大掺杂浓度不必大于区域533的最大掺杂浓度。区域532的注入剂量可以小于区域533的注入剂量。然而,区域532注入与区域533注入交叠,且被区域531注入部分地补偿。区域532和533之间的掺杂交叠导致了在532的交叠区域部分内较区域533更高的掺杂浓度,并且导致区域532剩余部分内更低的掺杂浓度。这是因为区域533的掺杂浓度随着距顶面的垂直距离而降低。在该具体实施例中,区域532因此具有两个功能。区域532的交叠部分用于承载电流,而该区域的较轻掺杂部分用于减轻电场。因此,可以形成从区域533到区域530的不同渐变结,这仍落在本申请的范围之内。
此外,在本实施例中,区域532没有到达外延层521的表面。然而,取决于掺杂浓度,该层也可以到达外延层521的顶面。相对长(约1-3μm)的n型掺杂导电条530在第二n-掺杂区域532和漏极接触电极534之间延伸,该n型掺杂导电条530将n-掺杂区域532与重掺杂n+区域528耦合,该重掺杂n+区域528从漏电极534延伸到外延层521内。因此,漏极从电极534开始于重掺杂n+区域528,逐渐结束于栅极526下方的轻掺杂n-区域533。该n型掺杂导电条可具有1-3μm的近似水平长度,且基本上被从n+重掺杂区域528水平地朝栅极526延伸基本上n型掺杂导电层530的长度的注入p型掺杂顶层531和底层529所遮挡。在从漏电极534下方开始的漏极区域的中心,n+掺杂终端(termination)区域527被注入,该n+掺杂终端区域527从表面深入到外延层521内。区域528的掺杂重于区域527。此外,区域527的掺杂重于区域529。为避免漏极接触534和区域529之间的击穿,这是必要的。
靠近栅极526的轻掺杂n-区域533使电场保持为低,从而抑制热载流子注入到栅极内,同时避免该结构过早击穿。此外,该区域533使栅极和漏极之间的反馈电容Cdg保持为低。第二或中间n-掺杂区域532可以被提供用于在导通电阻、晶体管结构的击穿、热载流子注入、以及反馈电容Cdg之间进行折衷。例如可以通过0度偏移注入掩模或者倾斜角自对准注入掩模,产生该中间n-掺杂注入区域532。具有垂直交替层531、530、529以及渐变区域533、532、528和527的这种结构形成超级结和渐变结的新组合。这种概念的优点在于,重掺杂导电层既从顶部也从底部被耗尽,因此也实现高的击穿电压,尽管该n型导电条的掺杂浓度较高。通过引入靠近栅极526的横向渐变结533、532和529,影响射频性能的多个关键参数的优化变得可能。除了导通电阻和击穿电压的优化之外,渐变结在栅极氧化物处保持低的电场以抑制热载流子注入(低的漂移),这对于LDMOS晶体管而言是一个重要的课题。此外,临界反馈电容Cdg可以保持在低的值。在右侧,深的高能量注入527防止在漏极接触534和区域529之间出现击穿。
所有区域可以通过离子注入形成。n型导电条可以形成为掩埋层,并分别通过层531和529从顶部和底部耗尽。具体而言,注入的p型层529从底部耗尽该n型导电条530,这使得可能增大该n型导电条的掺杂浓度。顶部p型层531从上方耗尽该n型导电条。轻掺杂n-区域533靠近栅极氧化物526以保持该关键“角落”周围的电场低。这抑制了热载流子注入到栅极氧化物526内,避免过早击穿,并保持反馈电容Cdg低。中间掺杂的n-注入区域532用作n-区域533和n型导电条530之间的交叠区域。该注入的深度和掺杂浓度用于优化导通电阻、击穿电压、热载流子注入和反馈电容Cdg之间的折衷。
同样,除了多层漏极区域之外,p型掺杂袋注入538从外延层521的顶面延伸到外延层521内。该袋注入538同样更深入外延层521,由此形成阻挡。该注入538因此可以补偿10-20%的N-LDD剂量533;局部地抑制漏极到沟道结电场和沟道长度调制,因此减小热载流子注入以及任何类型的DC偏置电流随时间漂移。同样,热载流子注入是一种局域化效应,通常发生在栅极的漏极侧0.5μm距离之内。电阻Rdson为在漏极尺度的几个微米上的分布值。该p型袋注入可以按照与上述相似的方式优化。
尽管已经示出和描述本发明的具体实施例,但是本发明并不限于该优选实施例,且在不离开仅由所附权利要求及其等同特征定义的本发明的范围的情况下,各种变化和改进对于本领域技术人员而言是显而易见的。例如,基板可以是p型或n型基板。因此,源极和漏极区域将分别为n型或p型。此外,所示实施例的特定特征的其他组合也是可能的。例如,p型阱可以添加到图7所示实施例,或者图2、4和6的实施例中所示的p型阱可以省略。此外,根据本申请的结构可以用于横向和垂直晶体管结构。
Claims (30)
1.一种LDMOS半导体晶体管结构,包括:
具有第一导电类型的外延层的基板;
第二导电类型的从所述外延层表面延伸的源极区域;
第二导电类型的在所述外延层内的轻掺杂漏极区域;
位于所述源极区域和漏极区域之间的沟道;以及
布置在所述沟道上方的在绝缘层内的栅极,
其中提供第一导电类型的注入区域,其从所述外延层的表面延伸到所述外延层内,与毗邻所述栅极的所述轻掺杂漏极区域的端部交叠并在所述沟道的一部分内延伸。
2.如权利要求1所述的半导体晶体管结构,其中所述第一导电类型的注入区域与所述源极区域分隔开。
3.如权利要求1所述的半导体晶体管结构,其中所述轻掺杂漏极区域包括漏极接触下方的第一重掺杂区域和从所述第一重掺杂区域沿朝向所述栅极的方向延伸的第二区域,其中所述第二区域的掺杂轻于所述第一重掺杂区域。
4.如权利要求3所述的半导体晶体管结构,还包括包围所述第一重掺杂区域的第三区域,其中所述第三区域的掺杂轻于所述第一重掺杂区域但重于所述第二区域。
5.如权利要求1所述的半导体晶体管结构,还包括从所述源极区域延伸到所述外延层底部的所述第一导电类型的下沉结构。
6.如权利要求1所述的半导体晶体管结构,其中所述注入区域具有0.5μm的近似水平长度。
7.如权利要求1所述的半导体晶体管结构,其中所述注入区域具有0.6μm的峰值浓度近似垂直长度。
8.如权利要求3所述的半导体晶体管结构,其中所述注入区域与所述第二区域部分交叠。
9.如权利要求1所述的半导体晶体管结构,还包含至少部分包围所述源极区域并在所述沟道内延伸的所述第一导电类型的阱。
10.如权利要求9所述的半导体晶体管结构,其中所述注入区域与所述阱部分交叠。
11.如权利要求1所述的半导体晶体管结构,其中所述注入区域横向扩散。
12.如权利要求1所述的半导体晶体管结构,其中所述轻掺杂漏极区域包含:
所述第二导电类型的第一区域,用于建立与电极的接触;
掺杂轻于所述第一区域的所述第二导电类型的第二区域,掩埋在所述外延层内并从所述第一区域沿着朝向所述栅极的方向水平地延伸;
所述第二导电类型的第三区域,掺杂轻于所述第二区域,并从所述外延层表面垂直地以及从所述第二区域水平地延伸直到所述栅极下方;
所述第一导电类型的顶层,从所述外延层的表面延伸到所述第二区域;以及
所述第一导电类型的底层,从所述第二区域延伸到所述外延层内。
13.如权利要求12所述的半导体晶体管结构,其中所述第三区域包括:从所述第二区域水平地向所述栅极延伸的所述第二导电类型的第一子区域;以及从所述外延层表面垂直地并从所述第一子区域水平地延伸直到所述栅极下方的所述第二导电类型的第二子区域。
14.如权利要求13所述的半导体晶体管结构,其中所述第一子区域的掺杂轻于所述第二区域,所述第二子区域的掺杂轻于所述第一子区域。
15.如权利要求13所述的半导体晶体管结构,其中所述第一子区域的掺杂轻于所述第二区域,所述第一和第二子区域交叠,且所述第一子区域局部掺杂轻于所述第二子区域。
16.如权利要求12所述的半导体晶体管结构,还包括从所述漏电极较所述第一区域更深地延伸到所述外延层中的第二导电类型的电压终端。
17.如权利要求12所述的半导体晶体管结构,其中所述第二区域具有1-3μm的近似水平长度。
18.如权利要求1所述的半导体晶体管结构,还包括布置在所述漏极和栅极之间、位于所述绝缘层顶部上的场电极,所述场电极至少部分覆盖所述栅极。
19.如权利要求12所述的半导体晶体管结构,还包括布置在所述漏极和栅极之间、位于所述绝缘层顶部上的场电极,所述场电极至少部分覆盖所述栅极。
20.一种制造LDMOS晶体管结构的方法,该结构具有基板和第一导电类型的外延层,该方法包括步骤:
在所述外延层内形成第二导电类型的源极区域和轻掺杂漏极区域;
至少形成覆盖所述源极区域和轻掺杂漏极区域之间的沟道的栅电极;
形成覆盖所述晶体管结构的表面的光致抗蚀剂层;
在所述光致抗蚀剂层内打开窗口,该窗口暴露毗邻所述栅极的所述轻掺杂漏极区域的端部;以及
通过所述窗口注入所述第一导电类型的袋区。
21.如权利要求20所述的方法,其中所述窗口露出部分栅电极。
22.如权利要求20所述的方法,其中所述窗口具有0.5μm的优选水平尺寸。
23.如权利要求20所述的方法,其中所述注入步骤产生峰值浓度垂直长度为0.6μm的袋。
24.如权利要求20所述的方法,其中所述漏极区域包括漏极接触下方的第一重掺杂区域,以及从所述第一重掺杂区域沿朝向所述栅极的方向延伸的第二区域,其中所述第二区域的掺杂轻于所述第一重掺杂区域。
25.如权利要求24所述的方法,其中所述轻掺杂漏极区域还包括包围所述第一重掺杂区域的第三区域,其中所述第三区域的掺杂轻于所述第一重掺杂区域但重于所述第二区域。
26.如权利要求24所述的方法,其中所述袋区与所述第二轻掺杂漏极区域部分交叠。
27.如权利要求24所述的方法,其中所述袋区在栅极下方横向扩散。
28.如权利要求27所述的方法,还包括形成所述第一导电类型的阱的步骤,所述阱至少部分包围所述源极区域并在所述沟道内延伸。
29.如权利要求28所述的方法,其中所述袋区与所述阱部分交叠。
30.如权利要求20所述的方法,其中在所述外延层内形成所述第一导电类型的下沉结构,该结构从所述源极区域延伸到所述外延层底部。
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US11/031,784 US7365402B2 (en) | 2005-01-06 | 2005-01-06 | LDMOS transistor |
US11/031,784 | 2005-01-06 |
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CN (1) | CN100585875C (zh) |
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DE112006000156B4 (de) | 2017-07-13 |
CN101099242A (zh) | 2008-01-02 |
WO2006072575A2 (en) | 2006-07-13 |
DE112006000156T5 (de) | 2008-04-17 |
US20060145250A1 (en) | 2006-07-06 |
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US7365402B2 (en) | 2008-04-29 |
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