CN100346478C - 半导体装置 - Google Patents
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- 229910052796 boron Inorganic materials 0.000 description 1
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 description 1
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Abstract
一种半导体装置,消减BiCMOS工艺的工序数量。在P型半导体衬底1的表面较深地形成第一N阱3A、第二N阱3B。在第一N阱3A中形成第一P阱4A,并在该第一P阱4A中形成N沟道型MOS晶体管10。第二N阱3B被用于纵型NPN双极晶体管30的集电极。在第二N阱3B中形成第二P阱4B。第二P阱4B和第一P阱4A被同时形成。该第二P阱4B被用于纵型NPN双极晶体管30的基极。在第二P阱4B的表面形成纵型NPN双极晶体管30的N+型发射极层31、P+型基极电极层32。
Description
技术领域
本发明涉及一种半导体装置,特别是涉及在同一半导体衬底上设有MOS晶体管和双极晶体管的半导体装置。
背景技术
近年来,集成化模拟电路和数字电路的模拟数字混合LSI正在被开发。在这种LSI中,模拟电路主要由双极晶体管构成,数字电路由MOS晶体管构成。当在同一半导体衬底上形成MOS晶体管和双极晶体管时,通常使用组合了双向工艺和CMOS工艺的BiCMOS工艺。
在现有的BiCMOS工艺中,由于相对CMOS工艺工序数量大幅地增加,因而招致LSI的制造成本及制造天数大幅地增加。对此,在专利文献1中记载了:通过形成使用所谓的三重阱CMOS工艺的双极晶体管谋求减少工序数的技术。
专利文献1:特开2000-3972号公报
发明内容
但是,双极晶体管的基极利用特别追加的工序形成,因此,工序数增加。
因此,本发明中,使用三重阱CMOS工艺,而不追加特别的工序,形成各种型号的双极晶体管。其主要的结构特征是,在P型半导体衬底的表面形成N阱,并在其中形成P沟道型晶体管。而在N阱中形成P阱,并在其中形成N沟道型晶体管。而后,将N阱作为纵型NPN双极晶体管的集电极使用。
并且,将P阱作为纵型NPN双极晶体管或横型NPN双极晶体管的基极使用。
附图说明
图1是本发明实施例的半导体装置的剖面图;
图2是本发明实施例的半导体装置的剖面图;
图3是本发明实施例的纵型NPN双极晶体管的特性图。
具体实施方式
下面参照附图详细说明本发明实施例的半导体装置。图1及图2是本发明实施例的半导体装置的剖面图。图1显示N沟道型MOS晶体管10、P沟道型MOS晶体管20、纵型NPN双极晶体管(Vertical NPN BJT)30,图2显示横型NPN双极晶体管(Lateral NPN BJT)40、横型PNP双极晶体管(Lateral PNP BJT)50、纵型PNP双极晶体管(Vertical PNP BJT)60。这两种类型的MOS晶体管及四种类型的双极晶体管都在同一半导体衬底1中形成。
其次,参照图1详细说明N沟道型MOS晶体管10、P沟道型MOS晶体管20、纵型NPN双极晶体管30的构造及其制造方法。
在P型半导体衬底1的表面形成用于将这些晶体管电分离的场绝缘膜2。在P型半导体衬底1的表面利用同一工序同时较深地形成第一N阱3A及第二N阱3B。其深度为例如自P型半导体衬底1表面起4um左右。在第一N阱3A中形成P阱4A,并在其中形成N沟道型MOS晶体管10。第一P阱4A比第一N阱3A浅,其深度为例如1um~2um。在第一P阱4A的表面形成N沟道型MOS晶体管10的N+的源极层11、N+型的漏极层12、栅极绝缘膜、栅极绝缘膜上的栅电极13及P阱4A的电位设定用P+层14。
另一方面,第二N阱3B被用于纵型NPN双极晶体管30的集电极。另外,在第二N阱3B中形成第二P阱4B。第二P阱4B和第一P阱4A同时由同一工序形成。该第二P阱4B被用于纵型NPN双极晶体管30的基极。在第二P阱4B的表面形成N+型发射极层31、P+型基极电极32。
另外,介由栅极绝缘膜在发射极层21和基极电极层32之间形成栅电极33。栅电极33和发射极层31连接。在第二N阱3B的表面形成N+型集电极层34。由于发射极层31和基极电极层32利用将栅电极33作为掩膜的离子注入形成,故基极电极层32和发射极层31的距离由栅电极33的长度决定。
在第一N阱3A中形成第4N阱5A。而后,在其中形成P沟道型MOS晶体管20。第4N阱5A比第一N阱3A浅,其深度为例如1um~2um。在第4N阱5A的表面形成P沟道型MOS晶体管20的P+的源极层21、P+型漏极层22、栅极绝缘膜、栅极绝缘膜上的栅电极23及第4N阱5A的电位设定用N+层24。
其次,参照图2详细说明横型NPN双极晶体管40、横型PNP双极晶体管50、纵型PNP双极晶体管60的构造及其制造方法。
在P型半导体衬底1的表面形成用于将这些晶体管电分离的场绝缘膜2。首先,说明横型NPN双极晶体管40。在P型半导体衬底1的表面形成第三N阱3C。该第三N阱3C和所述的第一N阱3A及第二N阱3B同时由同一工序形成。在第三N阱3C中形成第三P阱4C。该第三P阱4C也和所述的第一P阱4A及第二P阱4B同时由同一工序形成。在第三N阱3C中形成横型NPN双极晶体管40。第三P阱4C被用于横型NPN双极晶体管40的基极。在第三P阱4C的表面形成N+型发射极层41、N+型集电极层42。
另外,介由栅极绝缘膜在发射极层41和集电极层42之间形成栅电极43。栅电极43和发射极层41连接。然后,在第三P阱4C的表面形成P+型基极层44。由于发射极层41和基极层42利用将栅电极43作为掩膜的离子注入形成,故发射极层41和集电极层42的距离,也就是基极宽度由栅电极43的长度决定。另外,在第三N阱3C的表面形成第三N阱3C的电位设定用N+层45。
其次,说明横型PNP双极晶体管50。第五N阱5B和第四N阱5A同时由同一工序形成,并作为该晶体管的基极使用。
在第五N阱5B的表面形成P+型发射极层51、P+型集电极层52。介由栅极绝缘膜在发射极层51和集电极层52之间形成栅电极53。栅电极53和发射极层51连接。然后,在第五N阱5B的表面形成N+型基极层54。由于发射极层51和集电极层52利用将栅电极53作为掩膜的离子注入形成,故发射极层51和集电极层52的距离,也就是基极宽度由栅电极53的长度决定。另外,在和第五N阱5B邻接的P型半导体衬底1表面形成衬底电极设定用P+层55。
其次,说明纵型PNP双极晶体管60。第六N阱5C和第四N阱5A及第五N阱5B同时由同一工序形成,并作为该晶体管的基极使用。
在第六N阱5C的表面形成P+型发射极层61、N+型基极电极层62。介由栅极绝缘膜在发射极层61和基极电极层62之间形成栅电极63。栅电极63和发射极层61连接。由于发射极层61和基极电极层62利用将栅电极63作为掩膜的离子注入形成,故发射极层61和基极电极层62的距离由栅电极63的长度决定。另外,在和第六N阱5C邻接的P型半导体衬底1的表面形成P+型集电极层64。
其次,说明本发明实施例的半导体装置的制造方法。首先,在例如P型硅衬底等半导体衬底1表面形成第一N阱3A、第二N阱3B、第三N阱3C。该工序利用例如磷的离子注入和其后的热扩散进行。
其次,使用LOCOS法(Local Oxidation Of Silicon)形成场绝缘膜2。然后,形成第一P阱4A、第二P阱4B、第三P阱4C、第四N阱5A、第五N阱5B、第六N阱5C。P阱群4A、4B、4C和N阱群5A、5B、5C由各自的离子注入工序形成并进行热扩散。可以同时进行热扩散,也可以在各自的离子注入工序后分别进行。
而后,利用热氧化形成栅极绝缘膜,根据需要,进行N沟道型MOS晶体管10及P沟道型MOS晶体管20的沟道离子注入。然后,在栅极绝缘膜上形成栅电极12、23、33、43、53、63。这些栅电极利用多晶硅层或多侧面层形成。
之后,利用磷或砷这样的N型杂质的离子注入进行N+层的形成。N+层包括:所述的N沟道型MOS晶体管10的源极层11、漏极层、P沟道型MOS晶体管20的N+层24、纵型NPN双极晶体管30的发射极层31、集电极层34、横型NPN双极晶体管40的发射极层41、集电极层42、N+层45、横型PNP双极晶体管50的基极层54、纵型PNP双极晶体管60的基极电极层62。
另外,利用硼或二氟化硼这样的P型杂质的离子注入进行P+层的形成。P+层包括:所述的N沟道型MOS晶体管10的P+层14、P沟道型MOS晶体管20的源极层21、漏极层22、纵型NPN双极晶体管30的基极电极层32、横型NPN双极晶体管40的基极层44、横型PNP双极晶体管50的发射极层51、集电极层52、纵型PNP双极晶体管60的发射极层61、发射极层64。
通过本实施例,使用CMOS三重阱工艺,不需要特别的追加工序,而可在CMOS的基础上,在同一半导体衬底1上形成四种类型的双极晶体管,即:纵型NPN双极晶体管30、横型NPN双极晶体管40、横型PNP双极晶体管50、纵型PNP双极晶体管60。
图3是显示所述的纵型NPN双极晶体管30的特性的图,横轴表示集电极电流,纵轴表示电流放大系数hFE。由该特性图可知,可得到电流放大系数hFE为100,截止频率为1GHz这样的不逊色于双向工艺的优良的特性。
根据本实施例,通过将三重阱CMOS工艺的各种阱用于双极晶体管的基极或集电极,可大幅地消减BiCMOS工艺的工序数量。
Claims (4)
1、一种半导体装置,其特征在于,其包括:P型半导体衬底;第一N阱,其被形成在所述半导体衬底表面,并在其中形成P沟道型晶体管;第一P阱,其被形成在所述第一N阱中,并在其中形成N沟道型晶体管;第二N阱,其在所述半导体衬底上和所述第一N阱分离形成,所述第二N阱被作为纵型NPN双极晶体管的集电极使用,所述第一N阱和所述第二N阱同时由同一工序形成;
在所述第二N阱中形成的第二P阱,该第二P阱和所述第一P阱同时由同一工序形成,该第二P阱作为所述纵型NPN双极晶体管的基极使用。
2、如权利要求1所述的半导体装置,其特征在于,在所述半导体衬底表面具有:第三N阱,其和所述第一及第二N阱同时由同一工序形成;在该第三N阱中形成的第三P阱,该第三P阱和所述第一P阱同时由同一工序形成,将所述第三P阱作为横型NPN双极晶体管的基极使用。
3、如权利要求1所述的半导体装置,其特征在于,在所述第一N阱中形成比该第一N阱浅的第四N阱,并在该第四N阱中形成所述P沟道型晶体管,在所述半导体衬底上还具有和所述第四N阱同时由同一工序形成的第五N阱,所述第五N阱作为横型PNP双极晶体管的基极使用。
4、如权利要求1所述的半导体装置,其特征在于,在所述第一N阱中形成比该第一N阱浅的第四N阱,并在该第四N阱中形成所述P沟道型晶体管,在所述半导体衬底上还具有和所述第四N阱同时由同一工序形成的第六N阱,所述第六N阱作为纵型PNP双极晶体管的基极使用。
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Application Number | Priority Date | Filing Date | Title |
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JP2003102692A JP2004311684A (ja) | 2003-04-07 | 2003-04-07 | 半導体装置 |
JP102692/03 | 2003-04-07 | ||
JP102692/2003 | 2003-04-07 |
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CN1536667A CN1536667A (zh) | 2004-10-13 |
CN100346478C true CN100346478C (zh) | 2007-10-31 |
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CNB2004100334155A Expired - Lifetime CN100346478C (zh) | 2003-04-07 | 2004-04-07 | 半导体装置 |
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US (1) | US6924534B2 (zh) |
JP (1) | JP2004311684A (zh) |
CN (1) | CN100346478C (zh) |
TW (1) | TWI236136B (zh) |
Families Citing this family (11)
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US7723803B2 (en) * | 2005-03-07 | 2010-05-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Bipolar device compatible with CMOS process technology |
KR100731087B1 (ko) * | 2005-10-28 | 2007-06-22 | 동부일렉트로닉스 주식회사 | 바이씨모스 소자 및 그의 제조방법 |
JP5259246B2 (ja) | 2008-05-09 | 2013-08-07 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US8450672B2 (en) * | 2009-06-30 | 2013-05-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | CMOS image sensors formed of logic bipolar transistors |
WO2012139633A1 (en) * | 2011-04-12 | 2012-10-18 | X-Fab Semiconductor Foundries Ag | Bipolar transistor with gate electrode over the emitter base junction |
JP5755939B2 (ja) * | 2011-05-24 | 2015-07-29 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | 半導体装置及びその製造方法 |
US20140266393A1 (en) * | 2013-03-14 | 2014-09-18 | Linear Technology Corporation | Bipolar transistor with lowered 1/f noise |
US20160087529A1 (en) * | 2014-09-19 | 2016-03-24 | Sanken Electric Co., Ltd. | Bootstrap Circuit |
CN104392995B (zh) * | 2014-10-30 | 2017-09-22 | 京东方科技集团股份有限公司 | 一种晶体管、驱动电路及其驱动方法、显示装置 |
TWI615965B (zh) * | 2016-11-28 | 2018-02-21 | 新唐科技股份有限公司 | 半導體元件 |
CN108447901B (zh) * | 2018-02-28 | 2021-03-23 | 西安微电子技术研究所 | 一种抗总剂量辐射pnp晶体管结构 |
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Also Published As
Publication number | Publication date |
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TW200425473A (en) | 2004-11-16 |
US20040256678A1 (en) | 2004-12-23 |
CN1536667A (zh) | 2004-10-13 |
JP2004311684A (ja) | 2004-11-04 |
US6924534B2 (en) | 2005-08-02 |
TWI236136B (en) | 2005-07-11 |
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