CA2043172A1 - Methode et structure pour interconnecter differentes zones de polysiilcium sur des substrats de semiconducteur dans les circuits integres - Google Patents
Methode et structure pour interconnecter differentes zones de polysiilcium sur des substrats de semiconducteur dans les circuits integresInfo
- Publication number
- CA2043172A1 CA2043172A1 CA2043172A CA2043172A CA2043172A1 CA 2043172 A1 CA2043172 A1 CA 2043172A1 CA 2043172 A CA2043172 A CA 2043172A CA 2043172 A CA2043172 A CA 2043172A CA 2043172 A1 CA2043172 A1 CA 2043172A1
- Authority
- CA
- Canada
- Prior art keywords
- regions
- etch
- integrated circuits
- silicon
- stop material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US54590990A | 1990-06-28 | 1990-06-28 | |
US545,909 | 1990-06-28 |
Publications (2)
Publication Number | Publication Date |
---|---|
CA2043172A1 true CA2043172A1 (fr) | 1991-12-29 |
CA2043172C CA2043172C (fr) | 1996-04-09 |
Family
ID=24178023
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA002043172A Expired - Fee Related CA2043172C (fr) | 1990-06-28 | 1991-05-24 | Methode et structure pour interconnecter differentes zones de polysiilcium sur des substrats de semiconducteur dans les circuits integres |
Country Status (5)
Country | Link |
---|---|
US (2) | US5453400A (fr) |
EP (1) | EP0463458B1 (fr) |
JP (1) | JP2757927B2 (fr) |
CA (1) | CA2043172C (fr) |
DE (1) | DE69123884T2 (fr) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4339919C2 (de) * | 1993-11-23 | 1999-03-04 | Siemens Ag | Herstellverfahren für eine aus Silizid bestehende Anschlußfläche für ein Siliziumgebiet |
GB2290167B (en) * | 1994-06-08 | 1999-01-20 | Hyundai Electronics Ind | Method for fabricating a semiconductor device |
US5554549A (en) * | 1995-07-03 | 1996-09-10 | Taiwan Semiconductor Manufacturing Company Ltd. | Salicide process for FETs |
US5629235A (en) * | 1995-07-05 | 1997-05-13 | Winbond Electronics Corporation | Method for forming damage-free buried contact |
AU6689296A (en) * | 1995-08-03 | 1997-03-05 | Micron Technology, Inc. | Low cost local interconnect process |
US5869391A (en) | 1996-08-20 | 1999-02-09 | Micron Technology, Inc. | Semiconductor method of making electrical connection between an electrically conductive line and a node location, and integrated circuitry |
US5956585A (en) * | 1997-02-19 | 1999-09-21 | Winbond Electronics Corporation | Method of forming a self-aligned damage-free buried contact |
US6060404A (en) * | 1997-09-05 | 2000-05-09 | Advanced Micro Devices, Inc. | In-situ deposition of stop layer and dielectric layer during formation of local interconnects |
US6153933A (en) * | 1997-09-05 | 2000-11-28 | Advanced Micro Devices, Inc. | Elimination of residual materials in a multiple-layer interconnect structure |
US5920796A (en) * | 1997-09-05 | 1999-07-06 | Advanced Micro Devices, Inc. | In-situ etch of BARC layer during formation of local interconnects |
US6114235A (en) * | 1997-09-05 | 2000-09-05 | Advanced Micro Devices, Inc. | Multipurpose cap layer dielectric |
US6060328A (en) * | 1997-09-05 | 2000-05-09 | Advanced Micro Devices, Inc. | Methods and arrangements for determining an endpoint for an in-situ local interconnect etching process |
DE19822749A1 (de) * | 1998-05-20 | 1999-12-02 | Siemens Ag | Verfahren zur Erzeugung metallhaltiger Schichten |
US6335294B1 (en) | 1999-04-22 | 2002-01-01 | International Business Machines Corporation | Wet cleans for cobalt disilicide processing |
US6372668B2 (en) | 2000-01-18 | 2002-04-16 | Advanced Micro Devices, Inc. | Method of forming silicon oxynitride films |
US6468899B1 (en) * | 2001-06-27 | 2002-10-22 | Agere Systems Guardian Corp. | Contactless local interconnect process utilizing self-aligned silicide |
FR2828766B1 (fr) * | 2001-08-16 | 2004-01-16 | St Microelectronics Sa | Circuit integre comprenant des elements actifs et au moins un element passif, notamment des cellules memoire dram et procede de fabrication |
US6559043B1 (en) * | 2002-01-11 | 2003-05-06 | Taiwan Semiconductor Manufacturing Company | Method for electrical interconnection employing salicide bridge |
EP2450945B1 (fr) * | 2010-11-08 | 2013-05-29 | Imec | Procédé de production d'une structure de mémoire à grille flottante |
CN103730468B (zh) * | 2012-10-16 | 2017-12-01 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法、sram存储单元、sram存储器 |
US9634006B2 (en) | 2014-02-28 | 2017-04-25 | International Business Machines Corporation | Third type of metal gate stack for CMOS devices |
Family Cites Families (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4102733A (en) * | 1977-04-29 | 1978-07-25 | International Business Machines Corporation | Two and three mask process for IGFET fabrication |
JPS5748246A (en) * | 1980-08-13 | 1982-03-19 | Fujitsu Ltd | Manufacture of semiconductor device |
JPS57192079A (en) * | 1981-05-22 | 1982-11-26 | Hitachi Ltd | Semiconductor device |
US4374700A (en) * | 1981-05-29 | 1983-02-22 | Texas Instruments Incorporated | Method of manufacturing silicide contacts for CMOS devices |
US4476482A (en) * | 1981-05-29 | 1984-10-09 | Texas Instruments Incorporated | Silicide contacts for CMOS devices |
JPS584924A (ja) * | 1981-07-01 | 1983-01-12 | Hitachi Ltd | 半導体装置の電極形成方法 |
DE3132809A1 (de) * | 1981-08-19 | 1983-03-10 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum herstellen von integrierten mos-feldeffekttransistoren, insbesondere von komplementaeren mos-feldeffekttransistorenschaltungen mit einer aus metallsiliziden bestehenden zusaetzlichen leiterbahnebene |
JPS58100451A (ja) * | 1981-12-10 | 1983-06-15 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
EP0085777A3 (fr) * | 1982-02-01 | 1985-01-23 | Texas Instruments Incorporated | Fabrication de dispositifs comprenant la formation sélective de disiliciure de titanium par réaction directe |
JPS58175846A (ja) * | 1982-04-08 | 1983-10-15 | Toshiba Corp | 半導体装置の製造方法 |
US4463491A (en) * | 1982-04-23 | 1984-08-07 | Gte Laboratories Incorporated | Method of fabricating a monolithic integrated circuit structure |
JPH0618213B2 (ja) * | 1982-06-25 | 1994-03-09 | 松下電子工業株式会社 | 半導体装置の製造方法 |
JPS59100520A (ja) * | 1982-11-30 | 1984-06-09 | Fujitsu Ltd | 半導体装置の製造方法 |
JPS59175726A (ja) * | 1983-03-25 | 1984-10-04 | Fujitsu Ltd | 半導体装置の製造方法 |
JPH0638496B2 (ja) * | 1983-06-27 | 1994-05-18 | 日本電気株式会社 | 半導体装置 |
FR2555365B1 (fr) * | 1983-11-22 | 1986-08-29 | Efcis | Procede de fabrication de circuit integre avec connexions de siliciure de tantale et circuit integre realise selon ce procede |
US4519126A (en) * | 1983-12-12 | 1985-05-28 | Rca Corporation | Method of fabricating high speed CMOS devices |
JPS60130155A (ja) * | 1983-12-17 | 1985-07-11 | Toshiba Corp | 半導体装置 |
JPS60134466A (ja) * | 1983-12-23 | 1985-07-17 | Hitachi Ltd | 半導体装置およびその製造方法 |
US4873204A (en) * | 1984-06-15 | 1989-10-10 | Hewlett-Packard Company | Method for making silicide interconnection structures for integrated circuit devices |
FR2578272B1 (fr) * | 1985-03-01 | 1987-05-22 | Centre Nat Rech Scient | Procede de formation sur un substrat d'une couche de siliciure de tungstene, utilisable notamment pour la realisation de couches d'interconnexion des circuits integres. |
JPS6220374A (ja) * | 1985-07-19 | 1987-01-28 | Hitachi Ltd | 半導体集積回路装置 |
US4745081A (en) * | 1985-10-31 | 1988-05-17 | International Business Machines Corporation | Method of trench filling |
JPS63227045A (ja) * | 1987-03-17 | 1988-09-21 | Matsushita Electric Ind Co Ltd | Mos型半導体装置およびその製造方法 |
JPS63313855A (ja) * | 1987-06-17 | 1988-12-21 | Seiko Epson Corp | 半導体装置 |
JPS6415753A (en) * | 1987-07-10 | 1989-01-19 | Mitsui Toatsu Chemicals | Electrophotographic dry toner |
JPS6457523A (en) * | 1987-08-26 | 1989-03-03 | Mitsubishi Metal Corp | Manufacture of working member for superconducting ceramics |
US4873205A (en) * | 1987-12-21 | 1989-10-10 | International Business Machines Corporation | Method for providing silicide bridge contact between silicon regions separated by a thin dielectric |
JPH01281755A (ja) * | 1988-05-07 | 1989-11-13 | Seiko Epson Corp | 半導体装置 |
WO1989011732A1 (fr) * | 1988-05-24 | 1989-11-30 | Micron Technology, Inc. | Interconnexions locales tisi2 |
US5418179A (en) * | 1988-05-31 | 1995-05-23 | Yamaha Corporation | Process of fabricating complementary inverter circuit having multi-level interconnection |
JPH027531A (ja) * | 1988-06-27 | 1990-01-11 | Nec Corp | 半導体装置の製造方法 |
JPH039524A (ja) * | 1989-06-07 | 1991-01-17 | Fujitsu Ltd | 半導体装置 |
US5294822A (en) * | 1989-07-10 | 1994-03-15 | Texas Instruments Incorporated | Polycide local interconnect method and structure |
US5223456A (en) * | 1990-05-02 | 1993-06-29 | Quality Semiconductor Inc. | High density local interconnect in an integrated circit using metal silicide |
US5124280A (en) * | 1991-01-31 | 1992-06-23 | Sgs-Thomson Microelectronics, Inc. | Local interconnect for integrated circuits |
-
1991
- 1991-04-02 JP JP3094895A patent/JP2757927B2/ja not_active Expired - Fee Related
- 1991-05-24 CA CA002043172A patent/CA2043172C/fr not_active Expired - Fee Related
- 1991-06-11 DE DE69123884T patent/DE69123884T2/de not_active Expired - Fee Related
- 1991-06-11 EP EP91109554A patent/EP0463458B1/fr not_active Expired - Lifetime
-
1993
- 1993-01-19 US US08/006,662 patent/US5453400A/en not_active Expired - Fee Related
-
1996
- 1996-08-26 US US08/702,863 patent/US5672901A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE69123884D1 (de) | 1997-02-13 |
CA2043172C (fr) | 1996-04-09 |
JPH04233230A (ja) | 1992-08-21 |
US5453400A (en) | 1995-09-26 |
JP2757927B2 (ja) | 1998-05-25 |
EP0463458B1 (fr) | 1997-01-02 |
EP0463458A1 (fr) | 1992-01-02 |
US5672901A (en) | 1997-09-30 |
DE69123884T2 (de) | 1997-07-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CA2043172A1 (fr) | Methode et structure pour interconnecter differentes zones de polysiilcium sur des substrats de semiconducteur dans les circuits integres | |
EP0400821A3 (fr) | Interconnexion locale pour circuits intégrés | |
MY115056A (en) | Semiconductor integrated circuit device for connecting semiconductor region and electrical wiring metal via titanium silicide layer and method of fabrication thereof | |
EP0342796A3 (fr) | Transistor à couche mince | |
EP0057258A3 (en) | Process of manufacturing polysilicon structures having 1 micron dimensions on silicon substrates comprising integrated circuits using plasma etching | |
KR960019784A (ko) | 반도체장치 및 그의 제조방법 | |
EP0869557A3 (fr) | Cellule de mémoire ferroélectrique et son procédé de fabrication | |
KR940020531A (ko) | 콘택홀에 금속플러그 제조방법 | |
US5770487A (en) | Method of manufacturing a device, by which method a substrate with semiconductor element and conductor tracks is glued to a support body with metallization | |
EP0404372A3 (fr) | Procédé pour la fabrication de contacts en silicium polycristallin | |
US4937657A (en) | Self-aligned metallization for semiconductor device and process using selectively deposited tungsten | |
EP0081226A3 (fr) | Procédé pour la fabrication d'un dispositif semi-conducteur | |
EP0851490A3 (fr) | Dispositif semi-conducteur et procédé pour fabriquer celui-ci | |
EP0124960A3 (fr) | Dispositifs semi-conducteurs comportant de siliciures | |
JPS6441240A (en) | Semiconductor integrated circuit device | |
SE9504150D0 (sv) | Förfarande vid tillverkning av en halvledaranordning | |
JPS57155764A (en) | Manufacture of semiconductor device | |
WO1996030940A3 (fr) | Procede de fabrication d'un dispositif a semiconducteur dote d'un circuit bicmos | |
KR930022481A (ko) | 다결정 실리콘 게이트를 평탄화하는 집적 회로 제조방법 | |
JPS55113344A (en) | Electrode wiring and its manufacture | |
TW332928B (en) | Producing method of semiconductor device | |
JPS6489539A (en) | Manufacture of semiconductor device | |
JPS5363986A (en) | Production of semiconductor device | |
JPS6425481A (en) | Manufacture of semiconductor device | |
EP0115287A3 (fr) | Dispositif semi-conducteur comportant une siliciure métallique |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
EEER | Examination request | ||
MKLA | Lapsed |