AU6689296A - Low cost local interconnect process - Google Patents

Low cost local interconnect process

Info

Publication number
AU6689296A
AU6689296A AU66892/96A AU6689296A AU6689296A AU 6689296 A AU6689296 A AU 6689296A AU 66892/96 A AU66892/96 A AU 66892/96A AU 6689296 A AU6689296 A AU 6689296A AU 6689296 A AU6689296 A AU 6689296A
Authority
AU
Australia
Prior art keywords
low cost
local interconnect
interconnect process
cost local
low
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU66892/96A
Inventor
H. Monte Manning
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of AU6689296A publication Critical patent/AU6689296A/en
Abandoned legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895Local interconnects; Local pads, as exemplified by patent document EP0896365
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53271Conductive materials containing semiconductor material, e.g. polysilicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
AU66892/96A 1995-08-03 1996-08-05 Low cost local interconnect process Abandoned AU6689296A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US51081195A 1995-08-03 1995-08-03
PCT/US1996/012695 WO1997006560A1 (en) 1995-08-03 1996-08-05 Low cost local interconnect process
US510811 2000-02-23

Publications (1)

Publication Number Publication Date
AU6689296A true AU6689296A (en) 1997-03-05

Family

ID=24032302

Family Applications (1)

Application Number Title Priority Date Filing Date
AU66892/96A Abandoned AU6689296A (en) 1995-08-03 1996-08-05 Low cost local interconnect process

Country Status (2)

Country Link
AU (1) AU6689296A (en)
WO (1) WO1997006560A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6576544B1 (en) * 2001-09-28 2003-06-10 Lsi Logic Corporation Local interconnect

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56134757A (en) * 1980-03-26 1981-10-21 Nec Corp Complementary type mos semiconductor device and its manufacture
JPS6010673A (en) * 1983-06-30 1985-01-19 Fujitsu Ltd Semiconductor device
US4821085A (en) * 1985-05-01 1989-04-11 Texas Instruments Incorporated VLSI local interconnect structure
EP0239825B1 (en) * 1986-03-21 1993-08-25 Siemens Aktiengesellschaft Method for producing a bipolar transistor structure for very high speed switchings
JP2757927B2 (en) * 1990-06-28 1998-05-25 インターナショナル・ビジネス・マシーンズ・コーポレイション Method of interconnecting spaced silicon regions on a semiconductor substrate
JP3252518B2 (en) * 1993-03-19 2002-02-04 ソニー株式会社 Dry etching method
US5545584A (en) * 1995-07-03 1996-08-13 Taiwan Semiconductor Manufacturing Company Unified contact plug process for static random access memory (SRAM) having thin film transistors

Also Published As

Publication number Publication date
WO1997006560A1 (en) 1997-02-20

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