WO2023273554A1 - 读出电路结构 - Google Patents

读出电路结构 Download PDF

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Publication number
WO2023273554A1
WO2023273554A1 PCT/CN2022/088701 CN2022088701W WO2023273554A1 WO 2023273554 A1 WO2023273554 A1 WO 2023273554A1 CN 2022088701 W CN2022088701 W CN 2022088701W WO 2023273554 A1 WO2023273554 A1 WO 2023273554A1
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Prior art keywords
bit line
sense amplifier
transistor
tube
voltage
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PCT/CN2022/088701
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English (en)
French (fr)
Inventor
池性洙
金书延
张凤琴
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长鑫存储技术有限公司
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Priority to US17/847,825 priority Critical patent/US20230005522A1/en
Publication of WO2023273554A1 publication Critical patent/WO2023273554A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out

Definitions

  • the present disclosure relates to, but is not limited to, a readout circuit structure.
  • Dynamic Random Access Memory is a semiconductor storage device commonly used in computers, consisting of many repeated storage units. Each memory cell usually includes a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then through the bit line Read the data information stored in the capacitor, or write the data information into the capacitor through the bit line for storage.
  • DRAM can be divided into double rate synchronous (Double Data Rate, DDR) dynamic random access memory, graphics double rate synchronous (Graphics Double Data Rate, GDDR) dynamic random access memory, low power double rate synchronous (Low Power Double Data Rate) , LPDDR) dynamic random access memory.
  • DDR Double Data Rate
  • GDDR Graphics Double Data Rate
  • LPDDR Low Power Double Data Rate
  • An embodiment of the present disclosure provides a readout circuit structure, which is arranged in the gap of the memory array, including: a first sense amplifier circuit and a second sense amplifier circuit, which are adjacently arranged along the extending direction of the bit line, and are used for sensing the voltage of the memory cell and output a logic 1 or 0 corresponding to the voltage, wherein the first sense amplifier circuit couples one of the adjacent memory arrays through the first bit line, and couples the adjacent memory array through the first complementary bit line
  • the second sense amplifier circuit is coupled to a memory array in the adjacent memory array through the second bit line, and is coupled to another memory array in the adjacent memory array through the second complementary bit line;
  • the first equalization one of the source or the drain is connected to the first bit line;
  • the second equalization tube is one of the source or the drain is connected to the first complementary bit line;
  • the first equalization tube and the second equalization tube are used for balancing Signal, precharge the voltage of the first bit line and the voltage of the first complementary bit line to the preset voltage; the third
  • FIG. 1 is a schematic structural diagram of a 1 ⁇ 2 readout circuit structure provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a 2 ⁇ 2 readout circuit structure provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic circuit structure diagram of a first sense amplifier circuit and a third sense amplifier circuit provided by an embodiment of the present disclosure
  • FIG. 4 is a schematic circuit structure diagram of a second sense amplifier circuit and a fourth sense amplifier circuit provided by an embodiment of the present disclosure
  • FIG. 5 is a layout diagram of a first sense amplifier circuit, a second sense amplifier circuit, a third sense amplifier circuit and a fourth sense amplifier circuit provided by an embodiment of the present disclosure.
  • the current sense amplifier with offset compensation function includes the conduction process of the switching transistor in the process of precharging the bit line and the complementary bit line, resulting in insufficient charging speed for the bit line and the complementary bit line Fast, with the further shrinking of the transistor size, the saturation current of the switching transistor decreases, which is more serious, which is not conducive to improving the read and write performance of the memory.
  • an embodiment of the present disclosure provides a readout circuit structure disposed in the gap of the memory array, including: a first sense amplifier circuit and a second sense amplifier circuit arranged adjacently along the extending direction of the bit line , for sensing the voltage of the memory cell and outputting a logic 1 or 0 corresponding to the voltage, wherein the first sense amplifier circuit is coupled to one of the adjacent memory arrays through the first bit line, and the first complementary bit line is coupled to Coupling another storage array in the adjacent storage array, the second sense amplifier circuit couples one storage array in the adjacent storage array through the second bit line, and couples another storage array in the adjacent storage array through the second complementary bit line array; the first balance tube, one of the source or the drain is connected to the first bit line; the second balance tube, one of the source or the drain is connected to the first complementary bit line; the first balance tube and the second The balance tube is used to precharge the voltage of the first bit line and the voltage of the first complementary bit line to a preset voltage according to the balance signal; the third balance tube
  • Figure 1 is a schematic structural diagram of the 1 ⁇ 2 readout circuit structure provided by this embodiment
  • Figure 2 is a schematic structural diagram of a 2 ⁇ 2 readout circuit structure provided by this embodiment
  • Figure 3 is a first sensing circuit structure provided by this embodiment
  • Fig. 4 is the circuit structure diagram of the second sense amplifier circuit and the fourth sense amplifier circuit provided by this embodiment
  • Fig. 5 is the first sense amplifier circuit provided by this embodiment
  • the layout of the sense amplifier circuit, the second sense amplifier circuit, the third sense amplifier circuit and the fourth sense amplifier circuit, the structure of the readout circuit provided by this embodiment will be further described in detail below in conjunction with the accompanying drawings:
  • the readout circuit structure is arranged in the gap of the storage array 101, including:
  • each memory cell is used to store 1bit (bit) data, that is, a memory array 101 can store n ⁇ m bit data, and in the data readout process, specific storage unit, so as to read the data stored in the storage unit, or write data in the storage unit.
  • bit 1bit
  • the first sense amplifier circuit 113 and the second sense amplifier circuit 123 are arranged adjacently along the extending direction of the bit line, and are used to sense the voltage of the memory cell and output a logic 1 or 0 corresponding to the voltage; wherein, the first sense The amplifying circuit 113 is coupled to one storage array 101 in the adjacent storage array 101 through the first bit line BL1, and is coupled to another storage array 101 in the adjacent storage array 101 through the first complementary bit line BLB1; the second sense amplifier circuit 123 One memory array 101 among the adjacent memory arrays 101 is coupled through the second bit line BL2 , and the other memory array 101 among the adjacent memory arrays 101 is coupled through the second complementary bit line BLB2 .
  • the memory array 101 connected to the first sense amplifier circuit 113 through the first bit line BL1 is referred to as "the second memory array 101".
  • the readout circuit structure further includes: a read/write conversion circuit 102, configured to write external data into the memory cells of the memory array 101, or read out data from the memory cells.
  • the read-write conversion circuit 102 is arranged between the first sense amplifier circuit 113 and the second sense amplifier circuit 123; in other embodiments, the read-write conversion circuit can also be arranged between the first sense amplifier circuit between the circuit and the storage array or between the second sense amplifier circuit and the storage array.
  • the first equalization transistor ⁇ N1> one of the source or the drain is connected to the first bit line BL1, which is used to precharge the voltage of the first bit line BL1 to a preset voltage according to the equalization signal;
  • the second equalization transistor ⁇ N2 > one of the source or the drain is connected to the first complementary bit line BLB1, which is used to precharge the voltage of the first complementary bit line BL1 to the preset voltage according to the equalization signal;
  • the third equalization transistor ⁇ N3> the source Either one of the drain or the second bit line BL2 is used to precharge the voltage of the second bit line BL2 to a preset voltage according to the equalization signal;
  • the fourth equalization transistor ⁇ N4> one of the source or the drain The other is connected to the second complementary bit line BLB2 for precharging the voltage of the second complementary bit line BLB2 to a preset voltage according to the equalization signal.
  • One end of the source or drain of the first equalizing transistor ⁇ N1> is directly connected to the first bit line BL1 for direct precharging of the first bit line BL1, and one end of the source or drain of the second equalizing transistor ⁇ N2> is directly connected to the first bit line BL1.
  • one end of the source or drain of the third equalization transistor ⁇ N3> is directly connected to the second bit line BL2 for charging the second bit line BL2 is directly precharged
  • one end of the source or drain of the fourth equalization transistor ⁇ N4> is directly connected to the second complementary bit line BLB2 for direct precharging of the second complementary bit line BLB2, that is, directly connected to the bit line/
  • the complementary bit line directly charges the bit line and the complementary bit line, avoiding the conduction of the switching transistor in the precharging process to precharge the bit line/complementary bit line, thereby speeding up the charging speed of the bit line and the complementary bit line.
  • preset voltage is the voltage required for pre-charging in the pre-charging phase of the memory.
  • the specific voltage is set according to the pre-charging voltage required for the normal operation of the memory. This embodiment does not Constitutes a limit to the "preset voltage” value.
  • first equalizer tube ⁇ N1> and the third equalizer tube ⁇ N3> are set on the side of the first sense amplifier circuit 113 away from the second sense amplifier circuit 123, that is, the first equalizer tube ⁇ N1> and the third equalizer tube ⁇ N1>
  • the tube ⁇ N3> is set between the first sense amplifier circuit 113 and the "first storage array"
  • the second equalizer tube ⁇ N2> and the fourth equalizer tube ⁇ N4> are set in the second sense amplifier circuit 123 away from the first One side of the sense amplifier circuit 113 , that is, the second equalizer transistor ⁇ N2> and the fourth equalizer transistor ⁇ N4> are disposed between the second sense amplifier circuit 123 and the “second memory array”.
  • the first equalization tube ⁇ N1> and the third equalization tube ⁇ N3> for precharging the first sense amplifier circuit 113 are respectively arranged on both sides of the first sense amplifier circuit 113;
  • the second equalization transistor ⁇ N2> and the fourth equalization transistor ⁇ N4> pre-charged by the sense amplifier circuit 123 are disposed on two sides of the second sense amplifier circuit 123 respectively.
  • the third equalization transistor ⁇ N3> for precharging the second bit line BL2 connected to the second sense amplifier circuit 123 is provided on a side of the first sense amplifier circuit 113 away from the second sense amplifier circuit 123 side, and the first equalization tube ⁇ N1> was originally set on the side of the first sense amplifier circuit 113 away from the second sense amplifier circuit 123, that is, the third equalizer tube ⁇ N3> was set on the side where the first equalizer tube ⁇ N1> was located In the area gap, the layout area required for the layout of the original third equalization transistor ⁇ N3> is reduced; the second equalization transistor ⁇ N2> is set for precharging the first complementary bit line BLB1 connected to the first sense amplifier circuit 113 On the side of the second sense amplifier circuit 123 away from the first sense amplifier circuit 113 , and the fourth equalizer tube ⁇ N4> is originally arranged on the side of the second sense amplifier circuit 123 away from the first sense amplifier circuit 113 , That is, the second equalization transistor ⁇ N
  • the first complementary bit line BLB1 passes through the area where the second sense amplifier circuit 123 is located and is coupled to the first sense amplifier circuit 113, and is not electrically connected to the second sense amplifier circuit 123;
  • the second bit line BL2 passes through The area where the first sense amplifier circuit 113 is located is coupled to the second sense amplifier circuit 123 and is not electrically connected to the first sense amplifier circuit 113 .
  • the first complementary bit line BLB1 is coupled to the first sense amplifier circuit 113 through the area where the second sense amplifier circuit 123 is located, that is, the first complementary bit line BLB1 does not need to occupy an additional layout area to complete the wiring, thereby further reducing the structure of the readout circuit layout area
  • the second bit line BL2 passes through the area where the first sense amplifier circuit 113 is located and is coupled with the second sense amplifier circuit 123, that is, the second bit line BL2 does not need to occupy an additional layout area to complete the wiring, thereby further reducing the readout The layout area of the circuit structure.
  • the first balance tube ⁇ N1> and the second balance tube ⁇ N2> are arranged symmetrically based on the read-write conversion circuit 102
  • the third balance tube ⁇ N3> and the fourth balance tube ⁇ N4> are arranged based on the read-write conversion circuit 102.
  • the write switching circuits 102 are arranged symmetrically.
  • the balanced signal includes a first balanced signal and a second balanced signal, and the first balanced tube ⁇ N1> and the third balanced tube ⁇ N3> share the same gate for receiving the first balanced signal; the second balanced tube ⁇ N2> and the fourth equalization transistor ⁇ N4> share the same gate for receiving the second equalization signal. That is, the first equalized signal is used to precharge the first bit line BL1 connected to the first sense amplifier circuit 113 and the second bit line BL2 connected to the second sense amplifier circuit 123, and the second equalized signal is used to precharge the first bit line connected to the first sense amplifier circuit 123.
  • the sense amplifier circuit 113 and the first complementary bit line BLB1 and the second complementary bit line BLB2 connected to the second sense amplifier circuit 123 are pre-charged through the first equalizing transistor ⁇ N1> and the third equalizing transistor ⁇ N3> shares the gate, and the first equalizer ⁇ N1> and the third equalizer ⁇ N3> share the same gate, thereby further reducing the active area of the first equalizer ⁇ N1> and the third equalizer ⁇ N3>
  • the spacing between the active regions, thereby reducing the area occupied by the first equalizing tube ⁇ N1> and the third equalizing tube ⁇ N3>; the second equalizing tube ⁇ N2> and the fourth equalizing tube ⁇ N4> set in the same area are shared Grid, share the same gate with the second equalizer transistor ⁇ N2> and the fourth equalizer transistor ⁇ N4>, thereby further reducing the active area of the second equalizer transistor ⁇ N2> and the active area of the fourth equalizer transistor ⁇ N4> The space between them,
  • the first equalized signal and the second equalized signal are the same equalized signal. That is, the equalization tubes used for precharging the first sense amplifier circuit 113 and the second sense amplifier circuit 123 are controlled by the same signal.
  • a plurality of sense amplifier circuits are arranged in the extending direction of the word line (wherein, the extending direction of the word line is perpendicular to the extending direction of the bit line).
  • this embodiment is further described with a 2 ⁇ 2 sense amplifier circuit layout
  • the layout of the sense amplifier circuit and the equalization transistor provided in this embodiment, in the word line extension direction, other sense amplifier circuit structures are consistent with the layout of the 2 ⁇ 2 sense amplifier circuit shown in the figure.
  • the third sense amplifier circuit 133 is coupled to the "first memory array” through the third bit line BL3, and is coupled to the "second memory array” through the third complementary bit line BLB3, wherein , the fifth equalizing transistor ⁇ N5> is used for precharging the third bit line BL3, and the sixth equalizing transistor ⁇ N6> is used for precharging the third complementary bit line BLB3.
  • the fourth sense amplifier circuit 143 is coupled to the "first memory array” through the fourth bit line BL4, and is coupled to the "second memory array” through the fourth complementary bit line BLB4, wherein , the seventh equalizing transistor ⁇ N7> is used for precharging the fourth bit line BL4, and the eighth equalizing transistor ⁇ N8> is used for precharging the fourth complementary bit line BLB4.
  • the fifth equalizing tube ⁇ N5> and the seventh equalizing tube ⁇ N7> are arranged on the side of the third sense amplifier circuit 133 away from the fourth sense amplifier circuit 143
  • the sixth equalizer tube ⁇ N6> and the eighth equalizer tube ⁇ N8> is disposed on a side of the fourth sense amplifier circuit 143 away from the third sense amplifier circuit 133 .
  • the preset voltages include a first pre-charging voltage, a second pre-charging voltage, a third pre-charging voltage and a fourth pre-charging voltage.
  • the gate of the first equalization transistor ⁇ N1> is used to receive the first equalization signal EQ1, one of the source or the drain is used to receive the first precharge voltage, and the other is connected to the first bit line BL1;
  • the second equalization The gate of the tube ⁇ N2> is used to receive the second equalization signal EQ2, one of the source or the drain is used to receive the second precharge voltage, and the other is connected to the first complementary bit line BLB1;
  • the third equalization tube ⁇ N3> The gate is used to receive the first equalization signal EQ1, one of the source or the drain is used to receive the third precharge voltage, and the other is connected to the second bit line BL2;
  • the gate of the fourth equalization transistor ⁇ N4> is used to receive One of the source and the drain of the second equalization signal EQ2 is used
  • the first pre-charge voltage and the third pre-charge voltage are the same pre-charge voltage
  • the second pre-charge voltage and the fourth pre-charge voltage are the same pre-charge voltage, that is, the voltage used to pre-charge the bit line
  • the voltage used to precharge the complementary bit line is the same precharge voltage.
  • the first pre-charge voltage, the second pre-charge voltage, the third pre-charge voltage and the fourth pre-charge voltage are the same pre-charge voltage, which is used to pre-charge the sense amplifier circuit
  • the first sense amplifier circuit 113 is taken as an example to describe in detail below.
  • the first sense amplifier circuit 113 (refer to FIG. 2 ),include:
  • the sense amplifier module is connected to the first bit line BL1 through the read bit line SABL, and connected to the first complementary bit line BLB1 through the complementary read bit line SABLB, for sensing the voltage of the memory cell and outputting a logic 1 or corresponding to the voltage. 0.
  • the sense amplifier module includes: the first sense amplifier N transistor ⁇ N1400>, the gate is connected to the first bit line BL1, the drain is connected to the complementary readout bit line SABLB, and the source is connected to the second signal terminal NCS.
  • the sense amplifier module is in the amplification stage, the second signal terminal NCS is electrically connected to the voltage corresponding to logic 0; the second sense amplifier N-tube ⁇ N1405>, the gate is connected to the first complementary bit line BLB1, and the drain is connected to the read bit line SABL, the source is connected to the second signal terminal NCS;
  • the first sense amplifier P transistor ⁇ P1401> the gate is connected to the read bit line SABL, the drain is connected to the complementary read bit line SABLB, and the source is connected to the first signal terminal PCS,
  • the first signal terminal PCS is electrically connected to the voltage corresponding to logic 1; the second sense amplifier P transistor ⁇ P1400>, the gate is connected to the complementary readout bit line SA
  • An isolation module connected between the complementary read bit line SABLB and the first complementary bit line BLB1, and connected between the read bit line SABL and the first bit line BL1, for isolating the first bit line BL1 according to the isolation signal ISO 1. Signal interaction between the first complementary bit line BLB1 and the sense bit line SABL and complementary sense bit line SABLB.
  • the isolation module includes: the first isolation transistor ⁇ N1402>, the gate is used to receive the isolation signal ISO, the source is connected to the first bit line BL1, the drain is connected to the read bit line SABL, and the second isolation transistor ⁇ N1403> , the gate is used to receive the isolation signal ISO, the source is connected to the first complementary bit line BLB1, and the drain is connected to the complementary read bit line SABLB.
  • the offset elimination module is connected between the read bit line SABL and the first complementary bit line BLB1, and is connected between the complementary sense bit line SABLB and the first bit line BL1, and is used for adjusting the sense according to the offset cancel signal OC Measure the source-drain conduction difference between NMOS or PMOS transistors in the amplifier module.
  • the "source-drain conduction difference" mentioned above refers to: due to changes in the manufacturing process, temperature, etc., the first sense amplifier N-tube ⁇ N1400> and the second sense amplifier N-tube ⁇ N1405> and The first sense amplifier P-tube ⁇ P1401> and the second sense amplifier P-tube ⁇ P1400> may have different threshold voltages from each other.
  • the sense amplifier module may be due to the first sense amplifier P tube ⁇ P1401> and the second sense amplifier P tube ⁇ P1400> and the first sense amplifier N tube ⁇ N1400> and the second sense amplifier
  • the difference between the threshold voltages of the N-tube ⁇ N1405> causes offset noise.
  • the offset elimination module includes: a first offset elimination transistor ⁇ N1401>, the gate is used to receive the offset elimination signal OC, the source is connected to the first bit line BL1, and the drain is connected to the complementary readout bit line SABLB;
  • the gate of the second offset canceling transistor ⁇ N1404> is used to receive the offset canceling signal OC, the source is connected to the first complementary bit line BLB1, and the drain is connected to the read bit line SABL.
  • the structure of the third sense amplifier circuit 133 is the same as that of the first sense amplifier circuit 113 , and the above description is also applicable after the features of the corresponding structure are replaced.
  • the corresponding structure includes: the first bit line BL1 corresponds to BL3, the first complementary bit line BLB1 corresponds to BLB3, the first equalization transistor ⁇ N1> corresponds to ⁇ N5>, and the third equalization transistor ⁇ N3> corresponds to ⁇ N7 >, the first sense amplifier N tube ⁇ N1400> corresponds to ⁇ N1410>, the second sense amplifier N tube ⁇ N1405> corresponds to ⁇ N1415>, the first sense amplifier P tube ⁇ P1401> corresponds to ⁇ P1411>, The second sense amplifier P tube ⁇ P1400> corresponds to ⁇ P1410>, the first isolation tube ⁇ N1402> corresponds to ⁇ N1412>, the second isolation tube ⁇ N1403> corresponds to ⁇ N1413>,
  • the second sense amplifier circuit 123 is taken as an example to describe in detail below, and the second sense amplifier circuit 123 (refer to FIG. 2 ),include:
  • the sense amplifier module is connected to the second bit line BL2 through the read bit line SABL, and connected to the second complementary bit line BLB2 through the complementary read bit line SABLB, for sensing the voltage of the memory cell and outputting a logic 1 or corresponding to the voltage. 0.
  • the sense amplifier module includes: the third sense amplifier N transistor ⁇ N1425>, the gate is connected to the second bit line BL2, the drain is connected to the complementary readout bit line SABLB, and the source is connected to the second signal terminal NCS.
  • the sense amplifier module is in the amplification stage, the second signal terminal NCS is electrically connected to the voltage corresponding to logic 0;
  • the fourth sense amplifier N-tube ⁇ N1420> the gate is connected to the second complementary bit line BLB2, and the drain is connected to the read bit line SABL, the source is connected to the second signal terminal NCS;
  • the third sense amplifier P transistor ⁇ P1421> the gate is connected to the read bit line SABL, the drain is connected to the complementary read bit line SABLB, and the source is connected to the first signal terminal PCS,
  • the first signal terminal PCS is electrically connected to the voltage corresponding to logic 1;
  • the fourth sense amplifier P transistor ⁇ P1420> the gate is connected to the complementary readout bit line SA
  • An isolation module connected between the complementary read bit line SABLB and the second complementary bit line BLB2, and connected between the read bit line SABL and the second bit line BL2, for isolating the second bit line BL2 according to the isolation signal ISO 1. Signal interaction between the second complementary bit line BLB2 and the sense bit line SABL and complementary sense bit line SABLB.
  • the isolation module includes: the first isolation transistor ⁇ N1423>, the gate is used to receive the isolation signal ISO, the source is connected to the second bit line BL2, the drain is connected to the read bit line SABL, and the second isolation transistor ⁇ N1422> , the gate is used to receive the isolation signal ISO, the source is connected to the second complementary bit line BLB2, and the drain is connected to the complementary read bit line SABLB.
  • the offset elimination module is connected between the read bit line SABL and the second complementary bit line BLB2, and is connected between the complementary sense bit line SABLB and the second bit line BL2, and is used for adjusting the sense according to the offset cancel signal OC Measure the source-drain conduction difference between NMOS or PMOS transistors in the amplifier module.
  • the "source-drain conduction difference" mentioned above refers to: due to changes in the manufacturing process, temperature, etc., the third sense amplifier N-tube ⁇ N1425> and the fourth sense amplifier N-tube ⁇ N1420> and The third sense amplifier P-tube ⁇ P1421> and the fourth sense amplifier P-tube ⁇ P1420> may have different threshold voltages from each other.
  • the sense amplifier module may be due to the third sense amplifier P tube ⁇ P1421> and the fourth sense amplifier P tube ⁇ P1420> and the third sense amplifier N tube ⁇ N1445> and the fourth sense amplifier
  • the difference between the threshold voltages of the N-tube ⁇ N1420> causes offset noise.
  • the offset elimination module includes: a third offset elimination transistor ⁇ N1424>, the gate of which is used to receive the offset elimination signal OC, the source connected to the second bit line BL2, and the drain connected to the complementary readout bit line SABLB;
  • the gate of the fourth offset canceling transistor ⁇ N1421> is used to receive the offset canceling signal OC, the source is connected to the second complementary bit line BLB2, and the drain is connected to the read bit line SABL.
  • the structure of the fourth sense amplifier circuit 143 is the same as that of the second sense amplifier circuit 123 , and the above description is also applicable after replacing the features of the corresponding structure.
  • the corresponding structure includes: the second bit line BL2 corresponds to BL4, the second complementary bit line BLB2 corresponds to BLB4, the second equalizing transistor ⁇ N2> corresponds to ⁇ N6>, and the fourth equalizing transistor ⁇ N4> corresponds to ⁇ N8 >, the third sense amplifier N tube ⁇ N1425> corresponds to ⁇ N1435>, the fourth sense amplifier N tube ⁇ N1420> corresponds to ⁇ N1430>, the third sense amplifier P tube ⁇ P1421> corresponds to ⁇ P1431>, The fourth sense amplifier P tube ⁇ P1420> corresponds to ⁇ P1430>, the third isolation tube ⁇ N1423> corresponds to ⁇ N1433>, the fourth isolation tube ⁇ N1422> corresponds to ⁇ N1432>, and
  • the left side is the layout of the first sense amplifier circuit 113 (refer to FIG. 2 ) and the third sense amplifier circuit 133 (refer to FIG. 2 ), and the right side is the second sense amplifier circuit 123 (refer to FIG. 2 ). and the layout of the fourth sense amplifier circuit 143 (refer to FIG. 2 ).
  • the oblique frame area is the layout of the active layer
  • the white frame area is the layout of the gate layer
  • the shaded area is the layout of the contact layer.
  • the solid arrows pass through the layout of the contact layer, indicating that the structure represented by the solid arrows is in contact with the contact layer; any region passed by the dotted arrows does not contact each other.
  • balanced structure layout For the layout on the left, from top to bottom are: balanced structure layout, first sense amplification N tube layout, first offset isolation layout, first sense amplification P tube layout, second sense amplification P tube layout, The second offset isolation layout and the second sense amplifying N-pipe layout.
  • the gate structure of the first sense amplifier N transistor ⁇ N1400>, the gate structure of the second sense amplifier N transistor ⁇ N1405>, the first sense amplifier P transistor ⁇ P1401> The grid structure of the MOS transistor in the isolation module extends in the same direction as the gate structure of the second sense amplifier P transistor ⁇ P1400>, and the gate structure of the MOS transistor in the isolation module extends in the same direction as The gate structure of a sense amplifier N transistor ⁇ N1400> and the gate structure of the MOS transistor in the isolation module are perpendicular to each other.
  • the first sense amplifier P-tube ⁇ P1401>, the second sense amplifier P-tube ⁇ P1400>, the isolation module and the offset elimination module are arranged on the first sense amplifier N-tube ⁇ N1400> > and the second sense amplifier N tube ⁇ N1405>.
  • the balanced structure layout includes the first balanced tube ⁇ N1>, the third balanced tube ⁇ N3>, the fifth balanced tube ⁇ N5> and the seventh balanced tube ⁇ N7>.
  • the first balanced tube ⁇ N1 >, the third balance tube ⁇ N3>, the fifth balance tube ⁇ N5> and the seventh balance tube ⁇ N7> are used to receive the same pre-charge voltage VBLP, that is, the first balance tube is connected to the part of the active area of the first pre-charge voltage , the second equalizing tube is connected to the part of the active area of the second pre-charging voltage, the third equalizing tube is connected to the part of the active area of the third pre-charging voltage, and the fourth equalizing tube is connected to the part of the active area of the fourth pre-charging voltage.
  • the second pre-charging voltage and the fourth pre-charging voltage are the same pre-charging voltage; Part of the active area of a pre-charging voltage is connected to the part of the active area of the third equalizing tube connected to the third pre-charging voltage; the second equalizing tube is connected to the part of the active area of the second pre-charging voltage and the fourth equalizing tube is connected to the first Partial active regions of the four pre-charged voltages are connected.
  • the source of the first isolation transistor ⁇ N1402> is connected to the source of the first offset elimination transistor ⁇ N1401>, and is connected to the first bit line BL1;
  • the source of the isolation transistor ⁇ N1403> is connected to the source of the second offset canceling transistor ⁇ N1404>, and is connected to the first complementary bit line BLB1.
  • balanced structure layout For the layout on the right, from top to bottom are: balanced structure layout, the third sense amplification N tube layout, the third offset isolation layout, the fourth sense amplification P tube layout, the fourth sense amplification P tube layout, The third offset isolation layout and the third sense amplification N-tube layout.
  • the gate structure of the third sense amplifier N transistor ⁇ N1425>, the gate structure of the fourth sense amplifier N transistor ⁇ N1420>, the third sense amplifier P transistor ⁇ P1421> The grid structure of the MOS transistor in the isolation module extends in the same direction as the gate structure of the fourth sense amplifier P transistor ⁇ P1420>, and the gate structure of the MOS transistor in the isolation module extends in the same direction as the grid structure of the MOS transistor in the offset elimination module, and the first The gate structure of the three-sensing amplifier N transistor ⁇ N1425> and the gate structure of the MOS transistor in the isolation module are perpendicular to each other.
  • the third sense amplifier P-tube ⁇ P1421>, the fourth sense amplifier P-tube ⁇ P1420>, the isolation module and the offset elimination module are arranged on the third sense amplifier N-tube ⁇ N1425 > and the fourth sense amplifier N tube ⁇ N1420>.
  • the balanced structure layout includes the second balanced tube ⁇ N2>, the fourth balanced tube ⁇ N4>, the sixth balanced tube ⁇ N6> and the eighth balanced tube ⁇ N8>.
  • the second balanced tube ⁇ N2> >, the fourth balance tube ⁇ N4>, the sixth balance tube ⁇ N6> and the eighth balance tube ⁇ N8> are used to receive the same pre-charge voltage VBLP, that is, the part where the second balance tube ⁇ N2> is connected to the first pre-charge voltage
  • the active area, the fourth equalizing transistor ⁇ N4> is connected to the part of the active area of the second pre-charging voltage, the sixth equalizing transistor ⁇ N6> is connected to the part of the active area of the third pre-charging voltage, and the eighth equalizing transistor ⁇ N8> is connected to Part of the active regions of the fourth precharge voltage are connected.
  • the second pre-charging voltage and the fourth pre-charging voltage are the same pre-charging voltage; Part of the active area of a pre-charging voltage is connected to the part of the active area of the third equalizing tube connected to the third pre-charging voltage; the second equalizing tube is connected to the part of the active area of the second pre-charging voltage and the fourth equalizing tube is connected to the first Partial active regions of the four pre-charged voltages are connected.
  • the source of the third isolation transistor ⁇ N1423> is connected to the source of the third offset elimination transistor ⁇ N1424>, and is connected to the second bit line BL2; the fourth The source of the isolation transistor ⁇ N1422> is connected to the source of the fourth offset canceling transistor ⁇ N1421>, and is connected to the second complementary bit line BLB2.
  • one end of the source or drain of the first equalizing tube is directly connected to the first bit line for direct precharging of the first bit line
  • one end of the source or drain of the second equalizing tube is directly connected to the first bit line.
  • the complementary bit line is used to directly precharge the first complementary bit line
  • one end of the source or drain of the third equalizing tube is directly connected to the second bit line, which is used to directly precharge the second bit line
  • the source of the fourth equalizing tube One end of the electrode or the drain is directly connected to the second complementary bit line, which is used to directly precharge the second complementary bit line, that is, directly connects the bit line/complementary bit line through the equalization tube, and directly charges the bit line and the complementary bit line, avoiding
  • the precharge process requires the conduction of the switch transistor to precharge the bit line/complementary bit line, thus speeding up the charging speed of the bit line and the complementary bit line; in addition, for the second bit line connected to the second sense amplifier circuit
  • the pre-charged third equalization tube is
  • one end of the source or the drain of the first equalization transistor is directly connected to the first bit line for directly precharging the first bit line
  • one end of the source or drain of the second equalization transistor is directly connected to the first bit line.
  • the complementary bit line is used to directly precharge the first complementary bit line
  • one end of the source or drain of the third equalizing tube is directly connected to the second bit line, which is used to directly precharge the second bit line
  • the source of the fourth equalizing tube One end of the electrode or the drain is directly connected to the second complementary bit line, which is used to directly precharge the second complementary bit line, that is, directly connects the bit line/complementary bit line through the equalization tube, and directly charges the bit line and the complementary bit line, avoiding
  • the precharge process requires the conduction of the switch transistor to precharge the bit line/complementary bit line, thus speeding up the charging speed of the bit line and the complementary bit line; in addition, for the second bit line connected to the second sense amplifier circuit

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Abstract

一种读出电路结构，包括：第一感测放大电路（113）和第二感测放大电路（123），沿位线延伸方向相邻设置，第一感测放大电路（113）通过第一位线耦合相邻存储阵列中的一存储阵列（101），通过第一互补位线耦合相邻存储阵列中的另一存储阵列（101），第二感测放大电路（123）通过第二位线耦合相邻存储阵列中的一存储阵列（101），通过第二互补位线耦合相邻存储阵列中的另一存储阵列（101）；第一均衡管连接第一位线，第二均衡管连接第一互补位线，第三均衡管连接第二位线，第四均衡管连接第二互补位线；第一均衡管和第三均衡管设置在第一感测放大电路（113）远离第二感测放大电路（123）的一侧，第二均衡管和第四均衡管设置在第二感测放大电路（123）远离第一感测放大电路（113）的一侧。

Description

读出电路结构
相关申请的交叉引用
本公开要求在2021年07月02日提交中国专利局、申请号为202110751254.7、申请名称为“读出电路结构”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及但不限于一种读出电路结构。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。每个存储单元通常包括电容器和晶体管，晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连，字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。
DRAM可以分为双倍速率同步(Double Data Rate，DDR)动态随机存储器、图形用双倍速率同步(Graphics Double Data Rate，GDDR)动态随机存储器、低功耗双倍速率同步(Low Power Double Data Rate，LPDDR)动态随机存储器。随着DRAM应用的领域越来越多，如DRAM越来越多的应用于移动领域，用户对于DRAM功耗指标的要求越来越高。
然而，目前的DRAM性能仍有待提高。
发明内容
本公开实施例提供了一种读出电路结构，设置在存储阵列的间隙中，包括：第一感测放大电路和第二感测放大电路，沿位线延伸方向相邻设置，用于感测 存储单元的电压并输出对应于电压的逻辑1或0，其中，第一感测放大电路通过第一位线耦合相邻存储阵列中的一存储阵列，通过第一互补位线耦合相邻存储阵列中的另一存储阵列，第二感测放大电路通过第二位线耦合相邻存储阵列中的一存储阵列，通过第二互补位线耦合相邻存储阵列中的另一存储阵列；第一均衡管，源极或漏极的其中一者连接第一位线；第二均衡管，源极或漏极的其中一者连接第一互补位线；第一均衡管和第二均衡管用于根据均衡信号，预充第一位线的电压和第一互补位线的电压至预设电压；第三均衡管，源极或漏极的其中一者连接第二位线；第四均衡管，源极或漏极的其中一者连接第二互补位线；第三均衡管和第四均衡管用于根据均衡信号，预充第二位线的电压和第二互补位线的电压至预设电压；其中，第一均衡管和第三均衡管设置在第一感测放大电路远离第二感测放大电路的一侧，第二均衡管和第四均衡管设置在第二感测放大电路远离第一感测放大电路的一侧。
附图说明
图1为本公开实施例提供的1×2读出电路结构的结构示意图；
图2为本公开实施例提供的2×2读出电路结构的结构示意图；
图3为本公开实施例提供的第一感测放大电路和第三感测放大电路的电路结构示意图；
图4为本公开实施例提供的第二感测放大电路和第四感测放大电路的电路结构示意图；
图5为本公开实施例提供的第一感测放大电路、第二感测放大电路、第三感测放大电路和第四感测放大电路的版图。
具体实施方式
由背景技术可知，现有技术的DRAM性能仍有待提高。
经申请人发现，现有具备失调补偿功能的感测放大器在对位线和互补位线的预充电过程中，包含了开关晶体管的导通过程，导致对位线和互补位线的充 电速度不够快，随着晶体管尺寸进一步微缩，开关晶体管的饱和电流减小，这种情况更加严重，不利于提高存储器的读写性能。
为解决上述问题，本公开实施例提供了一种读出电路结构，设置在存储阵列的间隙中，包括：第一感测放大电路和第二感测放大电路，沿位线延伸方向相邻设置，用于感测存储单元的电压并输出对应于电压的逻辑1或0，其中，第一感测放大电路通过第一位线耦合相邻存储阵列中的一存储阵列，通过第一互补位线耦合相邻存储阵列中的另一存储阵列，第二感测放大电路通过第二位线耦合相邻存储阵列中的一存储阵列，通过第二互补位线耦合相邻存储阵列中的另一存储阵列；第一均衡管，源极或漏极的其中一者连接第一位线；第二均衡管，源极或漏极的其中一者连接第一互补位线；第一均衡管和第二均衡管用于根据均衡信号，预充第一位线的电压和第一互补位线的电压至预设电压；第三均衡管，源极或漏极的其中一者连接第二位线；第四均衡管，源极或漏极的其中一者连接第二互补位线；第三均衡管和第四均衡管用于根据均衡信号，预充第二位线的电压和第二互补位线的电压至预设电压；其中，第一均衡管和第三均衡管设置在第一感测放大电路远离第二感测放大电路的一侧，第二均衡管和第四均衡管设置在第二感测放大电路远离第一感测放大电路的一侧。
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开所要求保护的技术方案。以下各个实施例的划分是为了描述方便，不应对本公开的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合，相互引用。
图1为本实施例提供的1×2读出电路结构的结构示意图，图2为本实施例提供的2×2读出电路结构的结构示意图，图3为本实施例提供的第一感测放大电路和第三感测放大电路的电路结构示意图，图4为本实施例提供的第二感测放大电路和第四感测放大电路的电路结构示意图，图5为本实施例提供的第一 感测放大电路、第二感测放大电路、第三感测放大电路和第四感测放大电路的版图，以下结合附图对本实施例提供的读出电路结构进一步详细说明：
参考图1，读出电路结构，设置在存储阵列101的间隙中，包括：
存储阵列101中具有n行m列存储单元，每一存储单元都用于存储1bit(比特)数据，即一存储阵列101可以存储n×m bit数据，在数据读出过程中，通过选通具体存储单元，从而读出存储单元中存储的数据，或将存储单元中写入数据。
第一感测放大电路113和第二感测放大电路123，沿位线延伸方向相邻设置，用于感测存储单元的电压并输出对应于电压的逻辑1或0；其中，第一感测放大电路113通过第一位线BL1耦合相邻存储阵列101中的一存储阵列101，通过第一互补位线BLB1耦合相邻存储阵列101中的另一存储阵列101；第二感测放大电路123通过第二位线BL2耦合相邻存储阵列101中的一存储阵列101，通过第二互补位线BLB2耦合相邻存储阵列101中的另一存储阵列101。
在本实施例中，为了清楚分辨上述一存储阵列101和另一存储阵列101，在后续的描述中，将第一感测放大电路113通过第一位线BL1连接的存储阵列101称为“第一存储阵列”；将第二感测放大电路123通过第二互补位线BLB2连接的存储阵列101称为“第二存储阵列”。
在本实施例中，读出电路结构还包括：读写转换电路102，用于将外部数据写入存储阵列101的存储单元中，或将存储单元中的数据读出。
在本实施例中，读写转换电路102设置在第一感测放大电路113和第二感测放大电路123之间；在其他实施例中，读写转换电路也可以设置在第一感测放大电路与存储阵列之间或第二感测放大电路与存储阵列之间。
第一均衡管<N1>，源极或漏极的其中一者连接第一位线BL1，用于根据均衡信号，预充第一位线BL1的电压至预设电压；第二均衡管<N2>，源极或漏极的其中一者连接第一互补位线BLB1，用于根据均衡信号，预充第一互补位线BL1的电压至预设电压；第三均衡管<N3>，源极或漏极的其中一者连接第二位线BL2，用于根据均衡信号，预充第二位线BL2的电压至预设电压；第四 均衡管<N4>，源极或漏极的其中一者连接第二互补位线BLB2，用于根据均衡信号，预充第二互补位线BLB2的电压至预设电压。
通过第一均衡管<N1>源极或漏极的一端直接连接第一位线BL1，用于为第一位线BL1直接预充电，第二均衡管<N2>源极或漏极的一端直接连接第一互补位线BLB1，用于为第一互补位线BLB1直接预充电，第三均衡管<N3>源极或漏极的一端直接连接第二位线BL2，用于为第二位线BL2直接预充电，第四均衡管<N4>源极或漏极的一端直接连接第二互补位线BLB2，用于为第二互补位线BLB2直接预充电，即通过均衡管直接连接位线/互补位线，直接为位线和互补位线充电，避免了预充电过程需要开关晶体管的导通才能为位线/互补位线预充电，从而加快了对位线和互补位线的充电速度。
需要说明的是，上文提及的“预设电压”即存储器预充电阶段中的预充电所需电压，具体电压大小根据存储器正常工作所需的预充电电压进行设定，本实施例并不构成对“预设电压”数值的限定。
另外，第一均衡管<N1>和第三均衡管<N3>设置在第一感测放大电路113远离第二感测放大电路123的一侧，即第一均衡管<N1>和第三均衡管<N3>设置在第一感测放大电路113和“第一存储阵列”之间；第二均衡管<N2>和第四均衡管<N4>设置在第二感测放大电路123远离第一感测放大电路113的一侧，即第二均衡管<N2>和第四均衡管<N4>设置在第二感测放大电路123和“第二存储阵列”之间。
在相关技术的示例中，为第一感测放大电路113预充电的第一均衡管<N1>和第三均衡管<N3>分别设置在第一感测放大电路113的两侧；为第二感测放大电路123预充电的第二均衡管<N2>和第四均衡管<N4>分别设置在第二感测放大电路123的两侧。
在本实施例中，为连接第二感测放大电路123的第二位线BL2预充电的第三均衡管<N3>设置在第一感测放大电路113远离第二感测放大电路123的一侧，且第一均衡管<N1>原先设置在第一感测放大电路113远离第二感测放大电路123的一侧，即第三均衡管<N3>设置在第一均衡管<N1>所在区域的间隙中， 减小了原第三均衡管<N3>布局所需的版图区域；为连接第一感测放大电路113的第一互补位线BLB1预充电的第二均衡管<N2>设置在第二感测放大电路123远离第一感测放大电路113的一侧，且第四均衡管<N4>原先设置在第二感测放大电路123远离第一感测放大电路113的一侧，即第二均衡管<N2>设置在第四均衡管<N4>所在区域的间隙中，减少了原第二均衡管<N2>布局所需的版图区域，从而缩小读出电路结构的版图面积。
具体地，第一互补位线BLB1穿过第二感测放大电路123所在区域与第一感测放大电路113耦合，且不与第二感测放大电路123电连接；第二位线BL2穿过第一感测放大电路113所在区域与第二感测放大电路123耦合，且不与第一感测放大电路113电连接。第一互补位线BLB1从第二感测放大电路123所在区域穿过与第一感测放大电路113耦合，即第一互补位线BLB1无需额外占用布局面积完成布线，从而进一步缩小读出电路结构的版图面积，第二位线BL2从第一感测放大电路113所在区域穿过与第二感测放大电路123耦合，即第二位线BL2无需额外占用布局面积完成布线，从而进一步缩小读出电路结构的版图面积。
进一步地，在本实施例中，第一均衡管<N1>和第二均衡管<N2>基于读写转换电路102对称设置，第三均衡管<N3>和第四均衡管<N4>基于读写转换电路102对称设置。
对于第一均衡管<N1>、第二均衡管<N2>、第三均衡管<N3>和第四均衡管<N4>：
在一个例子中，均衡信号包括第一均衡信号和第二均衡信号，第一均衡管<N1>和第三均衡管<N3>共用同一栅极，用于接收第一均衡信号；第二均衡管<N2>和第四均衡管<N4>共用同一栅极，用于接收第二均衡信号。即第一均衡信号用于为连接第一感测放大电路113的第一位线BL1和连接第二感测放大电路123的第二位线BL2预充电，第二均衡信号用于为连接第一感测放大电路113和第一互补位线BLB1和连接第二感测放大电路123的第二互补位线BLB2预充电，通过设置在同一区域的第一均衡管<N1>和第三均衡管<N3>共用栅极， 通过第一均衡管<N1>和第三均衡管<N3>共用同一栅极，从而进一步缩小第一均衡管<N1>的有源区和第三均衡管<N3>的有源区之间的间距，从而缩小第一均衡管<N1>和第三均衡管<N3>所占面积；设置在同一区域的第二均衡管<N2>和第四均衡管<N4>共用栅极，通过第二均衡管<N2>和第四均衡管<N4>共用同一栅极，从而进一步缩小第二均衡管<N2>的有源区和第四均衡管<N4>的有源区之间的间距，从而缩小第二均衡管<N2>和第四均衡管<N4>所占面积。
在另一例子中，第一均衡信号和第二均衡信号为同一均衡信号。即用于为第一感测放大电路113和第二感测放大电路123预充电的均衡管采用同一信号控制。
本领域技术人员可知，对于相邻存储阵列101之间，具有多个感测放大电路。具体地，多个感测放大电路在字线延伸方向(其中，字线延伸方向与位线延伸方向相垂直)排列，参考图2，本实施例以2×2的感测放大电路布局进一步描述本实施例提供的感测放大电路以及均衡管的布局，在字线延伸方向上，其他感测放大电路结构与图示2×2的感测放大电路布局一致。
类似于第一感测放大电路113的连接结构，第三感测放大电路133通过第三位线BL3耦合“第一存储阵列”，通过第三互补位线BLB3耦合“第二存储阵列”，其中，第五均衡管<N5>用于为第三位线BL3预充电，第六均衡管<N6>用于为第三互补位线BLB3预充电。
类似于第二感测放大电路123的连接结构，第四感测放大电路143通过第四位线BL4耦合“第一存储阵列”，通过第四互补位线BLB4耦合“第二存储阵列”，其中，第七均衡管<N7>用于为第四位线BL4预充电，第八均衡管<N8>用于为第四互补位线BLB4预充电。
其中，第五均衡管<N5>和第七均衡管<N7>设置在第三感测放大电路133远离第四感测放大电路143的一侧，第六均衡管<N6>和第八均衡管<N8>设置在第四感测放大电路143远离第三感测放大电路133的一侧。
在预充电过程中，对于第一均衡管<N1>、第二均衡管<N2>、第三均衡管<N3>和第四均衡管<N4>：
在一个例子中，预设电压包括第一预充电电压、第二预充电电压、第三预充电电压和第四预充电电压。其中，第一均衡管<N1>栅极用于接收第一均衡信号EQ1，源极或漏极的一者用于接收第一预充电电压，另一者连接第一位线BL1；第二均衡管<N2>栅极用于接收第二均衡信号EQ2，源极或漏极的一者用于接收第二预充电电压，另一者连接第一互补位线BLB1；第三均衡管<N3>栅极用于接收第一均衡信号EQ1，源极或漏极的一者用于接收第三预充电电压，另一者连接第二位线BL2；第四均衡管<N4>栅极用于接收第二均衡信号EQ2，源极或漏极的一者用于接收第四预充电电压，另一者连接第二互补位线BLB2。
在另一个例子中，第一预充电电压和第三预充电电压为同一预充电电压，第二预充电电压和第四预充电电压为同一预充电电压，即用于为位线预充电的电压为同一预充电电压，用于为互补位线预充电的电压为同一预充电电压。进一步地，参考图3和图4，第一预充电电压、第二预充电电压、第三预充电电压和第四预充电电压为同一预充电电压，即用于为感测放大电路预充电的预充电电压为同一预充电电压VBLP；在本实施例中，预充电电压VBLP＝1/2VDD，其中，VDD为芯片内部电源电压；在其他实施例中，预充电电压VBLP可以根据具体应用场景进行设置。
参考图3和图4，对于第一感测放大电路113和第三感测放大电路133，下面以第一感测放大电路113为例进行详细说明，第一感测放大电路113(参考图2)，包括：
感测放大模块，通过读出位线SABL连接第一位线BL1，通过互补读出位线SABLB连接第一互补位线BLB1，用于感测存储单元的电压并输出对应于电压的逻辑1或0。
具体地，感测放大模块，包括：第一感测放大N管<N1400>，栅极连接第一位线BL1，漏极连接互补读出位线SABLB，源极连接第二信号端NCS，当感测放大模块处于放大阶段，第二信号端NCS电连接逻辑0所对应的电压；第二感测放大N管<N1405>，栅极连接第一互补位线BLB1，漏极连接读出位线SABL，源极连接第二信号端NCS；第一感测放大P管<P1401>，栅极连接读出 位线SABL，漏极连接互补读出位线SABLB，源极连接第一信号端PCS，当感测放大模块处于放大阶段，第一信号端PCS电连接逻辑1所对应的电压；第二感测放大P管<P1400>，栅极连接互补读出位线SABLB，漏极连接读出位线SABL，源极连接第一信号端PCS。
隔离模块，连接在互补读出位线SABLB和第一互补位线BLB1之间，且连接在读出位线SABL与第一位线BL1之间，用于根据隔离信号ISO隔离第一位线BL1、第一互补位线BLB1与读出位线SABL和互补读出位线SABLB之间的信号交互。
具体地，隔离模块，包括：第一隔离管<N1402>，栅极用于接收隔离信号ISO，源极连接第一位线BL1，漏极连接读出位线SABL，第二隔离管<N1403>，栅极用于接收隔离信号ISO，源极连接第一互补位线BLB1，漏极连接互补读出位线SABLB。
偏移消除模块，连接在读出位线SABL与第一互补位线BLB1之间，且连接在互补读出位线SABLB与第一位线BL1之间，用于根据偏移消除信号OC调节感测放大模块中NMOS之间或PMOS管之间的源漏导通差异。
需要说明的是，上文提到的“源漏导通差异”指：由于制造工艺、温度等的变化，第一感测放大N管<N1400>和第二感测放大N管<N1405>以及第一感测放大P管<P1401>和第二感测放大P管<P1400>彼此可以具有不同的阈值电压。在这种情况下，感测放大模块可能由于第一感测放大P管<P1401>和第二感测放大P管<P1400>以及第一感测放大N管<N1400>和第二感测放大N管<N1405>的阈值电压之间的差异而导致偏移噪声。
具体地，偏移消除模块，包括：第一偏移消除管<N1401>，栅极用于接收偏移消除信号OC，源极连接第一位线BL1，漏极连接互补读出位线SABLB；第二偏移消除管<N1404>，栅极用于接收偏移消除信号OC，源极连接第一互补位线BLB1，漏极连接读出位线SABL。
本领域技术人员可知，第三感测放大电路133的结构与第一感测放大电路113的结构相同，进行相应结构的特征替换后同样适用于上文说明。具体地， 对应结构包括：第一位线BL1对应于BL3、第一互补位线BLB1对应于BLB3、第一均衡管<N1>对应于<N5>、第三均衡管<N3>对应于<N7>、第一感测放大N管<N1400>对应于<N1410>、第二感测放大N管<N1405>对应于<N1415>、第一感测放大P管<P1401>对应于<P1411>、第二感测放大P管<P1400>对应于<P1410>、第一隔离管<N1402>对应于<N1412>、第二隔离管<N1403>对应于<N1413>、第一偏移消除管<N1401>对应于<N1411>、第二偏移消除管<N1404>对应于<N1414>。
参考图3和图4，对于第二感测放大电路123和第四感测放大电路143，下面以第二感测放大电路123为例进行详细说明，第二感测放大电路123(参考图2)，包括：
感测放大模块，通过读出位线SABL连接第二位线BL2，通过互补读出位线SABLB连接第二互补位线BLB2，用于感测存储单元的电压并输出对应于电压的逻辑1或0。
具体地，感测放大模块，包括：第三感测放大N管<N1425>，栅极连接第二位线BL2，漏极连接互补读出位线SABLB，源极连接第二信号端NCS，当感测放大模块处于放大阶段，第二信号端NCS电连接逻辑0所对应的电压；第四感测放大N管<N1420>，栅极连接第二互补位线BLB2，漏极连接读出位线SABL，源极连接第二信号端NCS；第三感测放大P管<P1421>，栅极连接读出位线SABL，漏极连接互补读出位线SABLB，源极连接第一信号端PCS，当感测放大模块处于放大阶段，第一信号端PCS电连接逻辑1所对应的电压；第四感测放大P管<P1420>，栅极连接互补读出位线SABLB，漏极连接读出位线SABL，源极连接第一信号端PCS。
隔离模块，连接在互补读出位线SABLB和第二互补位线BLB2之间，且连接在读出位线SABL与第二位线BL2之间，用于根据隔离信号ISO隔离第二位线BL2、第二互补位线BLB2与读出位线SABL和互补读出位线SABLB之间的信号交互。
具体地，隔离模块，包括：第一隔离管<N1423>，栅极用于接收隔离信号 ISO，源极连接第二位线BL2，漏极连接读出位线SABL，第二隔离管<N1422>，栅极用于接收隔离信号ISO，源极连接第二互补位线BLB2，漏极连接互补读出位线SABLB。
偏移消除模块，连接在读出位线SABL与第二互补位线BLB2之间，且连接在互补读出位线SABLB与第二位线BL2之间，用于根据偏移消除信号OC调节感测放大模块中NMOS之间或PMOS管之间的源漏导通差异。
需要说明的是，上文提到的“源漏导通差异”指：由于制造工艺、温度等的变化，第三感测放大N管<N1425>和第四感测放大N管<N1420>以及第三感测放大P管<P1421>和第四感测放大P管<P1420>彼此可以具有不同的阈值电压。在这种情况下，感测放大模块可能由于第三感测放大P管<P1421>和第四感测放大P管<P1420>以及第三感测放大N管<N1445>和第四感测放大N管<N1420>的阈值电压之间的差异而导致偏移噪声。
具体地，偏移消除模块，包括：第三偏移消除管<N1424>，栅极用于接收偏移消除信号OC，源极连接第二位线BL2，漏极连接互补读出位线SABLB；第四偏移消除管<N1421>，栅极用于接收偏移消除信号OC，源极连接第二互补位线BLB2，漏极连接读出位线SABL。
本领域技术人员可知，第四感测放大电路143的结构与第二感测放大电路123的结构相同，进行相应结构的特征替换后同样适用于上文说明。具体地，对应结构包括：第二位线BL2对应于BL4、第二互补位线BLB2对应于BLB4、第二均衡管<N2>对应于<N6>、第四均衡管<N4>对应于<N8>、第三感测放大N管<N1425>对应于<N1435>、第四感测放大N管<N1420>对应于<N1430>、第三感测放大P管<P1421>对应于<P1431>、第四感测放大P管<P1420>对应于<P1430>、第三隔离管<N1423>对应于<N1433>、第四隔离管<N1422>对应于<N1432>、第三偏移消除管<N1424>对应于<N1434>、第四偏移消除管<N1421>对应于<N1431>。
参考图5，左侧为第一感测放大电路113(参考图2)和第三感测放大电路133(参考图2)的版图，右侧为第二感测放大电路123(参考图2)和第四感 测放大电路143(参考图2)的版图。
对于图5，斜框区域为有源层的版图布局，白框区域为栅极层的版图布局，阴影区域为接触层的版图布局。在该图中，实线箭头经过接触层的版图布局，说明实线箭头所表征的结构与接触层相互接触；虚线箭头所经过的任何区域都不相互接触。
对于左侧版图，从上到下依次为：均衡结构版图、第一感测放大N管版图、第一偏移隔离版图、第一感测放大P管版图、第二感测放大P管版图、第二偏移隔离版图和第二感测放大N管版图。
由图可知，在本实施例中，第一感测放大N管<N1400>的栅极结构、第二感测放大N管<N1405>的栅极结构、第一感测放大P管<P1401>的栅极结构和第二感测放大P管<P1400>的栅极结构延伸方向相同，隔离模块中MOS管的栅极结构和偏移消除模块中MOS管的栅极结构延伸方向相同，且第一感测放大N管<N1400>的栅极结构和隔离模块中MOS管的栅极结构延伸方向相互垂直。
由图可知，在本实施例中，第一感测放大P管<P1401>、第二感测放大P管<P1400>、隔离模块和偏移消除模块设置在第一感测放大N管<N1400>和第二感测放大N管<N1405>之间。
其中，均衡结构版图包括第一均衡管<N1>、第三均衡管<N3>、第五均衡管<N5>和第七均衡管<N7>，在本实施例中，第一均衡管<N1>、第三均衡管<N3>、第五均衡管<N5>和第七均衡管<N7>用于接收同一预充电电压VBLP，即第一均衡管连接第一预充电电压的部分有源区、第二均衡管连接第二预充电电压的部分有源区、第三均衡管连接第三预充电电压的部分有源区和第四均衡管连接第四预充电电压的部分有源区相连通。
在其他实施例中，若第一预充电电压和第三预充电电压为同一预充电电压，第二预充电电压和第四预充电电压为同一预充电电压；此时，第一均衡管连接第一预充电电压的部分有源区和第三均衡管连接第三预充电电压的部分有源区相连通；第二均衡管连接第二预充电电压的部分有源区和第四均衡管连接第四预充电电压的部分有源区相连通。
对于第一偏移隔离版图和第二偏移隔离版图，第一隔离管<N1402>的源极和第一偏移消除管<N1401>的源极连通，并连接第一位线BL1；第二隔离管<N1403>的源极和第二偏移消除管<N1404>的源极连接，并连接第一互补位线BLB1。
对于右侧版图，从上到下依次为：均衡结构版图、第三感测放大N管版图、第三偏移隔离版图、第四感测放大P管版图、第四感测放大P管版图、第三偏移隔离版图和第三感测放大N管版图。
由图可知，在本实施例中，第三感测放大N管<N1425>的栅极结构、第四感测放大N管<N1420>的栅极结构、第三感测放大P管<P1421>的栅极结构和第四感测放大P管<P1420>的栅极结构延伸方向相同，隔离模块中MOS管的栅极结构和偏移消除模块中MOS管的栅极结构延伸方向相同，且第三感测放大N管<N1425>的栅极结构和隔离模块中MOS管的栅极结构延伸方向相互垂直。
由图可知，在本实施例中，第三感测放大P管<P1421>、第四感测放大P管<P1420>、隔离模块和偏移消除模块设置在第三感测放大N管<N1425>和第四感测放大N管<N1420>之间。
其中，均衡结构版图包括第二均衡管<N2>、第四均衡管<N4>、第六均衡管<N6>和第八均衡管<N8>，在本实施例中，第二均衡管<N2>、第四均衡管<N4>、第六均衡管<N6>和第八均衡管<N8>用于接收同一预充电电压VBLP，即第二均衡管<N2>连接第一预充电电压的部分有源区、第四均衡管<N4>连接第二预充电电压的部分有源区、第六均衡管<N6>连接第三预充电电压的部分有源区和第八均衡管<N8>连接第四预充电电压的部分有源区相连通。
在其他实施例中，若第一预充电电压和第三预充电电压为同一预充电电压，第二预充电电压和第四预充电电压为同一预充电电压；此时，第一均衡管连接第一预充电电压的部分有源区和第三均衡管连接第三预充电电压的部分有源区相连通；第二均衡管连接第二预充电电压的部分有源区和第四均衡管连接第四预充电电压的部分有源区相连通。
对于第三偏移隔离版图和第四偏移隔离版图，第三隔离管<N1423>的源极 和第三偏移消除管<N1424>的源极连通，并连接第二位线BL2；第四隔离管<N1422>的源极和第四偏移消除管<N1421>的源极连接，并连接第二互补位线BLB2。
与相关技术相比，第一均衡管源极或漏极的一端直接连接第一位线，用于为第一位线直接预充电，第二均衡管源极或漏极的一端直接连接第一互补位线，用于为第一互补位线直接预充电，第三均衡管源极或漏极的一端直接连接第二位线，用于为第二位线直接预充电，第四均衡管源极或漏极的一端直接连接第二互补位线，用于为第二互补位线直接预充电，即通过均衡管直接连接位线/互补位线，直接为位线和互补位线充电，避免了预充电过程需要开关晶体管的导通才能为位线/互补位线预充电，从而加快了对位线和互补位线的充电速度；另外，为连接第二感测放大电路的第二位线预充电的第三均衡管设置在第一感测放大电路远离第二感测放大电路的一侧，且第一均衡管原先设置在第一感测放大电路远离第二感测放大电路的一侧，即第三均衡管设置在第一均衡管所在区域的间隙中，减小了原第三均衡管布局所需的版图区域，为连接第一感测放大电路的第一互补位线预充电的第二均衡管设置在第二感测放大电路远离第一感测放大电路的一侧，且第四均衡管原先设置在第二感测放大电路远离第一感测放大电路的一侧，即第二均衡管设置在第四均衡管所在区域的间隙中，减少了原第二均衡管布局所需的版图区域，从而缩小读出电路结构的版图面积。
本领域的普通技术人员可以理解，上述各实施例是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开的精神和范围。
工业实用性
本公开实施例中，第一均衡管源极或漏极的一端直接连接第一位线，用于为第一位线直接预充电，第二均衡管源极或漏极的一端直接连接第一互补位线，用于为第一互补位线直接预充电，第三均衡管源极或漏极的一端直接连接第二位线，用于为第二位线直接预充电，第四均衡管源极或漏极的一端直接连接第 二互补位线，用于为第二互补位线直接预充电，即通过均衡管直接连接位线/互补位线，直接为位线和互补位线充电，避免了预充电过程需要开关晶体管的导通才能为位线/互补位线预充电，从而加快了对位线和互补位线的充电速度；另外，为连接第二感测放大电路的第二位线预充电的第三均衡管设置在第一感测放大电路远离第二感测放大电路的一侧，且第一均衡管原先设置在第一感测放大电路远离第二感测放大电路的一侧，即第三均衡管设置在第一均衡管所在区域的间隙中，减小了原第三均衡管布局所需的版图区域，为连接第一感测放大电路的第一互补位线预充电的第二均衡管设置在第二感测放大电路远离第一感测放大电路的一侧，且第四均衡管原先设置在第二感测放大电路远离第一感测放大电路的一侧，即第二均衡管设置在第四均衡管所在区域的间隙中，减少了原第二均衡管布局许所需的版图区域，从而缩小读出电路结构的版图面积。

Claims (16)

  1. 一种读出电路结构，设置在相邻存储阵列的间隙中，包括：
    第一感测放大电路和第二感测放大电路，沿位线延伸方向相邻设置，用于感测所述存储单元的电压并输出对应于所述电压的逻辑1或0，其中，所述第一感测放大电路通过第一位线耦合相邻存储阵列中的一存储阵列，通过第一互补位线耦合相邻存储阵列中的另一存储阵列，所述第二感测放大电路通过第二位线耦合相邻存储阵列中的一存储阵列，通过第二互补位线耦合相邻存储阵列中的另一存储阵列；
    第一均衡管，源极或漏极的其中一者连接所述第一位线；
    第二均衡管，源极或漏极的其中一者连接所述第一互补位线；
    所述第一均衡管和所述第二均衡管用于根据均衡信号，预充所述第一位线的电压和所述第一互补位线的电压至预设电压；
    第三均衡管，源极或漏极的其中一者连接所述第二位线；
    第四均衡管，源极或漏极的其中一者连接所述第二互补位线；
    所述第三均衡管和所述第四均衡管用于根据所述均衡信号，预充所述第二位线的电压和所述第二互补位线的电压至预设电压；
    其中，所述第一均衡管和所述第三均衡管设置在所述第一感测放大电路远离所述第二感测放大电路的一侧，所述第二均衡管和所述第四均衡管设置在所述第二感测放大电路远离所述第一感测放大电路的一侧。
  2. 根据权利要求1所述的读出电路结构，其中，所述第一互补位线穿过所述第二感测放大电路所在区域与所述第一感测放大电路耦合，且不与所述第二感测放大电路电连接；所述第二位线穿过所述第一感测放大电路所在区域与所述第二感测放大电路耦合，且不与所述第一感测放大电路电连接。
  3. 根据权利要求1所述的读出电路结构，其中，所述均衡信号包括第一均衡信号和第二均衡信号；所述第一均衡管和所述第三均衡管共用同一栅极，用于接收所述第一均衡信号；所述第二均衡管和所述第四均衡管共用同一栅极， 用于接收所述第二均衡信号。
  4. 根据权利要求3所述的读出电路结构，其中，所述第一均衡信号和所述第二均衡信号为同一均衡信号。
  5. 根据权利要求3所述的读出电路结构，其中，所述预设电压包括第一预充电电压、第二预充电压、第三预充电电压和第四预充电电压，包括：
    所述第一均衡管，栅极用于接收所述第一均衡信号，源极或漏极的其中一者用于接收第一预充电电压，另一者连接所述第一位线；
    所述第二均衡管，栅极用于接收所述第二均衡信号，源极或漏极的其中一者用于接收第二预充电电压，另一者连接所述第一互补位线；
    所述第三均衡管，栅极用于接收所述第一均衡信号，源极或漏极的其中一者用于接收第三预充电电压，另一者连接所述第二位线；
    所述第四均衡管，栅极用于接收所述第二均衡信号，源极或漏极的其中一者用于接收第四预充电电压，另一者连接所述第二互补位线。
  6. 根据权利要求5所述的读出电路结构，其中，所述第一预充电电压、所述第二预充电电压、所述第三预充电电压和所述第四预充电电压为同一预充电电压。
  7. 根据权利要求5所述的读出电路结构，其中，所述第一预充电电压和所述第三预充电电压为同一预充电电压，所述第二预充电电压和所述第四预充电电压为同一预充电电压。
  8. 根据权利要求7所述的读出电路结构，其中，所述第一均衡管连接所述第一预充电电压的部分有源区和所述第三均衡管连接所述第三预充电电压的部分有源区相连通；所述第二均衡管连接所述第二预充电电压的部分有源区和所述第四均衡管连接所述第四预充电电压的部分有源区相连通。
  9. 根据权利要求1所述的读出电路结构，其中，所述读出电路结构还包括：
    读写转换电路，设置在所述第一感测放大电路和所述第二感测放大电路之间，用于将外部数据写入所述存储阵列的存储单元中，或将所述存储单元中的数据读出；
    所述第一均衡管和所述第三均衡管基于所述读写转换电路对称设置；
    所述第二均衡管和所述第四均衡管基于所述读写转换电路对称设置。
  10. 根据权利要求1所述的读出电路结构，其中，所述第一感测放大电路包括：
    感测放大模块，通过读出位线连接所述第一位线，通过互补读出位线连接所述第一互补位线，用于感测所述存储单元的电压并输出对应于所述电压的逻辑1或0；
    隔离模块，连接在所述互补读出位线与所述第一互补位线之间，且连接在所述读出位线与所述第一位线之间，用于根据隔离信号隔离所述第一位线、第一互补位线与所述读出位线、互补读出位线之间的信号交互；
    偏移消除模块，连接在所述读出位线与所述第一互补位线之间，且连接在所述互补读出位线与所述第一位线之间，用于根据偏移消除信号调节所述感测放大模块中NMOS管之间或PMOS管之间的源漏导通差异。
  11. 根据权利要求10所述的读出电路结构，其中，所述感测放大模块包括：
    第一感测放大N管，栅极连接所述第一位线，漏极连接所述互补读出位线，源极连接第二信号端，当所述感测放大模块处于放大阶段，所述第二信号端电连接逻辑0所对应的电压；
    第二感测放大N管，栅极连接所述第一互补位线，漏极连接所述读出位线，源极连接所述第二信号端；
    第一感测放大P管，栅极连接所述读出位线，漏极连接所述互补读出位线，源极连接第一信号端，当所述感测放大模块处于放大阶段，所述第一信号端电连接逻辑1所对应的电压；
    第二感测放大P管，栅极连接所述互补读出位线，漏极连接所述读出位线，源极连接所述第一信号端。
  12. 根据权利要求11所述的读出电路结构，其中，所述第一感测放大N管的栅极结构、所述第二感测放大N管的栅极结构、所述第一感测放大P管的 栅极结构和所述第二感测放大P管的栅极结构延伸方向相同，所述隔离模块中MOS管的栅极结构和所述偏移消除模块中MOS管的栅极结构延伸方向相同，且所述第一感测放大N管的栅极结构和所述隔离模块中MOS管的栅极结构延伸方向相互垂直。
  13. 根据权利要求11所述的读出电路结构，其中，所述第一感测放大P管、所述第二感测放大P管、所述隔离模块和所述偏移消除模块设置在所述第一感测放大N管和所述第二感测放大N管之间。
  14. 根据权利要求10所述的读出电路结构，其中，所述隔离模块包括：
    第一隔离管，栅极用于接收所述隔离信号，源极连接所述第一位线，漏极连接所述读出位线；
    第二隔离管，栅极用于接收所述隔离信号，源极连接所述第一互补位线，漏极连接所述互补读出位线。
  15. 根据权利要求14所述的读出电路结构，其中，所述偏移消除模块包括：
    第一偏移消除管，栅极用于接收所述偏移消除信号，源极连接所述第一位线，漏极连接所述互补读出位线；
    第二偏移消除管，栅极用于接收所述偏移消除信号，源极连接所述第一互补位线，漏极连接所述读出位线。
  16. 根据权利要求15所述的读出电路结构，其中，所述第一隔离管的源极和所述第一偏移消除管的源极连通，并连接所述第一位线；所述第二隔离管的源极和所述第二偏移消除管的源极连接，并连接所述第一互补位线。
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