WO2023000490A1 - 感测放大电路和数据读出方法 - Google Patents

感测放大电路和数据读出方法 Download PDF

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Publication number
WO2023000490A1
WO2023000490A1 PCT/CN2021/120374 CN2021120374W WO2023000490A1 WO 2023000490 A1 WO2023000490 A1 WO 2023000490A1 CN 2021120374 W CN2021120374 W CN 2021120374W WO 2023000490 A1 WO2023000490 A1 WO 2023000490A1
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Prior art keywords
bit line
signal
complementary
readout
mos transistor
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PCT/CN2021/120374
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English (en)
French (fr)
Inventor
池性洙
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长鑫存储技术有限公司
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Priority to US17/773,255 priority Critical patent/US20230071414A1/en
Priority to EP21950728.2A priority patent/EP4246520A1/en
Publication of WO2023000490A1 publication Critical patent/WO2023000490A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Definitions

  • the present application relates to but is not limited to a sense amplifier circuit and a data readout method.
  • DRAM Dynamic Random Access Memory
  • CL CAS latency
  • tRCD row address to column address delay
  • tRP row precharge time
  • tRAS row activity time
  • the row address to column address delay tRCD refers to the minimum number of clock cycles required to open a row of memory and access its columns. In the design process of DRAM, the time interval t from row opening to column opening needs to be greater than tRCD, so as to ensure that The data in the memory cell is correctly read.
  • the time between the row opening and the column opening is the charge sharing stage of the sense amplifier.
  • the delay of tRCD is ensured by the time of the charge sharing stage, which makes the readout process time of the sense amplifier longer. Long, resulting in a longer data readout time of the DRAM.
  • An embodiment of the present application provides a sense amplifier circuit, which is arranged between adjacent memory arrays, and includes: a first PMOS transistor, the source of which is connected to a first signal terminal, and the first signal terminal is used to receive a first level signal ;
  • the source of the first NMOS transistor is connected to the second signal terminal, and the second signal terminal is used to receive the second level signal, and the first level signal is greater than the second level signal;
  • the drain of the NMOS transistor is connected to the first read bit line, the gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to the second read bit line;
  • the source of the second PMOS transistor is connected to the first signal terminal;
  • the second NMOS transistor the source of which is connected to the second signal terminal;
  • the drain of the second PMOS transistor and the drain of the second NMOS transistor are connected to the first complementary readout bit line, and the gate of the second PMOS transistor is connected to the second NMOS transistor
  • the second conduction unit one end of which is connected to the first complementary readout bit line, and the other end is connected to the initial complementary bit line, and the initial complementary bit line is connected to the memory unit of another memory array in the adjacent memory array;
  • the first drive unit one end of which is connected to the first readout bit line, and the other end is connected to the second complementary readout bit line for turning on the first PMOS transistor or the first NMOS transistor;
  • the second drive unit is connected to the first complementary readout bit line at one end The bit line, the other end of which is connected to the second read bit line, is used to turn on the second PMOS transistor or the second NMOS transistor.
  • the embodiment of the present application also provides a data readout method, based on the above-mentioned sense amplifier circuit, including: providing a row selection signal and a column selection signal to turn on the selected memory cell; providing a logic "1" to the first signal terminal corresponding electrical signal, and provide the electrical signal corresponding to logic "0" to the second signal terminal.
  • 1 to 3 are schematic circuit structure diagrams of a sense amplifier circuit provided by an embodiment of the present application.
  • FIG. 4 is a schematic timing diagram of various control signals for the sense amplifier circuit in the data readout method provided by another embodiment of the present application.
  • 5 to 9 are schematic diagrams of the circuit state of the sense amplifier circuit corresponding to each stage in the data readout method provided by another embodiment of the present application.
  • the row address to column address delay tRCD refers to the minimum number of clock cycles required to open a row of memory and access its columns. In the design process of DRAM, the time interval t from row opening to column opening needs to be greater than tRCD, so as to ensure that The data in the memory cell is correctly read.
  • the time between row opening and column opening is the charge sharing stage of the sense amplifier.
  • the delay of tRCD is ensured through the time of the charge sharing stage, resulting in a longer readout process of the sense amplifier. As a result, the data readout time of the DRAM is longer.
  • the delay of tRCD is ensured through different readout phases of the sense amplifier, so as to shorten the readout process time of the sense amplifier, thereby shortening the data readout time of the DRAM.
  • an embodiment of the present application provides a sense amplifier circuit, which is arranged between adjacent memory arrays, and includes: a first PMOS transistor, the source of which is connected to a first signal terminal, and the first signal terminal is used to receive the first signal terminal.
  • a level signal the source of the first NMOS transistor is connected to the second signal terminal, and the second signal terminal is used to receive the second level signal, and the first level signal is greater than the second level signal;
  • the drain of the first PMOS transistor Pole and the drain of the first NMOS transistor are connected to the first readout bit line, the gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to the second readout bit line;
  • the source of the second PMOS transistor is connected to the first A signal terminal;
  • the second NMOS transistor the source of which is connected to the second signal terminal;
  • the drain of the second PMOS transistor and the drain of the second NMOS transistor are connected to the first complementary read bit line, and the gate of the second PMOS transistor and The gate of the second NM
  • FIGS. 1 to 3 are schematic diagrams of the circuit structure of the sense amplifier circuit provided by this embodiment.
  • the sense amplifier circuit provided by this embodiment will be further described in detail below in conjunction with the accompanying drawings, specifically as follows:
  • the sense amplifier circuit includes:
  • the source of the first PMOS transistor ⁇ P1> is connected to the first signal terminal, and the first signal terminal is used to receive a first level signal (Positive Cell Storing Signal, PCS).
  • PCS Personal Cell Storing Signal
  • the source of the first NMOS transistor ⁇ N1> is connected to the second signal terminal, and the second signal terminal is used to receive the second level signal (Negative Cell Storing Signal, NCS).
  • NCS Native Cell Storing Signal
  • the drain of the first PMOS transistor ⁇ P1> and the drain of the first NMOS transistor ⁇ N1> are connected to the first read bit line SABL, the gate of the first PMOS transistor ⁇ P1> and the gate of the first NMOS transistor ⁇ N1>
  • the pole is connected to the second sense bit line ISABL.
  • the connection relationship between the gate of the first PMOS transistor ⁇ P1> and the gate of the first NMOS transistor ⁇ N1> is the same, that is, based on the second read bit line With different levels of ISABL, when the first PMOS transistor ⁇ P1> or the first NMOS transistor ⁇ N1> is turned on, there is only one turned-on MOS transistor among the first PMOS transistor ⁇ P1> and the first NMOS transistor ⁇ N1>.
  • the first level signal PCS is greater than the second level signal NCS.
  • the first level signal PCS is a high level corresponding to logic "1”
  • the second level signal NCS is a high level corresponding to logic "0”. " low level.
  • the first signal terminal is connected to the first read bit line SABL, thereby pulling the first read bit line SABL up to the first level signal PCS, and further The initial bit line BL is pulled up to the first level signal PCS, so that the data read by the memory through the initial bit line BL is the high level of the logic "1" corresponding to the first level signal PCS;
  • the first NMOS transistor ⁇ N1 > After being turned on, the second signal terminal is connected to the first read bit line SABL, thereby pulling the first read bit line SABL down to the second level signal NCS, and then pulling the initial bit line BL down to the second level signal Level signal NCS, so that the data read from the memory through the initial bit line BL is the low level of the second level signal NCS corresponding to logic "0".
  • the source of the second PMOS transistor ⁇ P2> is connected to the first signal terminal.
  • the source of the second NMOS transistor ⁇ N2> is connected to the second signal terminal.
  • the drain of the second PMOS transistor ⁇ P2> and the drain of the second NMOS transistor ⁇ N2> are connected to the first complementary read bit line SABLB, the gate of the second PMOS transistor ⁇ P2> and the gate of the second NMOS transistor ⁇ N2> The gate is connected to the second complementary read bit line ISABLB.
  • the first signal terminal is connected to the first complementary read bit line SABLB, thereby pulling the first complementary read bit line SABLB to the first level signal PCS, Then the initial complementary bit line BLB is pulled up to the first level signal PCS, so that the data read by the memory through the initial complementary bit line BLB is the high level of the logic "1" corresponding to the first level signal PCS;
  • the second signal terminal is connected to the first complementary read bit line SABLB, thereby pulling the first complementary read bit line SABLB down to the second level signal NCS, and then the initial complementary bit line BLB is pulled low to the second level signal NCS, so that the data read from the memory through the initial complementary bit line BLB is the low level of the second level signal NCS corresponding to logic "0".
  • the connection of the specific "source” and “drain” The method does not constitute a limitation to this embodiment. In other embodiments, a connection manner in which "drain” replaces “source” and “source” replaces “drain” may be used.
  • One end of the first conduction unit 201 is connected to the first readout bit line SABL, and the other end is connected to the initial bit line BL, and the initial bit line BL is connected to the memory cells of a memory array 101 in the adjacent memory array 101 .
  • One end of the second conduction unit 202 is connected to the first complementary readout bit line SABLB, and the other end is connected to the initial complementary bit line BLB, which is connected to the memory cells of another memory array 101 in the adjacent memory array 101 .
  • the initial bit line BL is connected to the first read bit line SABL, that is, the levels of the initial bit line BL and the first read bit line SABL are the same;
  • the second conduction unit 202 When turned on, the initial complementary bit line BLB is connected to the first complementary read bit line SABLB, that is, the levels of the initial complementary bit line BLB and the first complementary bit line SABLB are the same.
  • the first conduction unit 201 includes a first isolation MOS transistor ⁇ 11>, the source of the first isolation MOS transistor ⁇ 11> is connected to the first read bit line SABL, and the drain is connected to the initial bit line BL;
  • the second conduction unit 202 includes a second isolation MOS transistor ⁇ 12>, the source of the second isolation MOS transistor ⁇ 12> is connected to the first complementary readout bit line SABLB, and the drain is connected to the initial complementary bit line BLB;
  • the first isolation The gate of the MOS transistor ⁇ 11> and the gate of the second isolation MOS transistor ⁇ 12> are used to receive the isolation signal (Bit Line and SABL Isolation Signal, ISO), and based on the isolation signal ISO, the initial bit line BL and the first The sense bit line SABL is electrically connected, and the initial complementary sense bit line BLB is electrically connected to the first complementary sense bit line SABLB.
  • the specific connection mode of "source” and “drain” does not constitute a limitation to this embodiment, and in other implementations
  • the connection method of "drain” replacing “source” and “source” replacing “drain” can be used; in addition, this embodiment does not apply to the first isolation MOS transistor ⁇ 11> and the second isolation MOS transistor
  • the type of 12> is limited.
  • the first isolation MOS transistor ⁇ 11> and the second isolation MOS transistor ⁇ 12> can be NMOS transistors or PMOS transistors.
  • the initial bit line BL is connected to the first storage unit through the first switch ⁇ 01>
  • the complementary initial bit line BLB is connected to the second storage unit through the second switch ⁇ 02>.
  • the first storage unit and the second storage unit are used to store opposite data, that is, when the first storage unit stores a high level corresponding to logic “1”, the second storage unit stores a low level corresponding to logic “0”; When the first storage unit stores a low level corresponding to logic “0”, the second storage unit stores a high level corresponding to logic “1”.
  • the gate of the first switch tube ⁇ 01> is connected to the word line WL
  • the source is connected to the initial bit line BL
  • the drain is connected to the first memory cell
  • the second switch The gate of the transistor ⁇ 02> is connected to the word line WL
  • the source is connected to the initial complementary BLB
  • the drain is connected to the second storage unit.
  • the word line WL is used for turning on based on the row selection signal, when the word line WL is turned on, the switch connected to the word line WL is turned on, and the charge of the memory cells is shared to the initial bit line BL or the initial complementary bit line BLB , the initial bit line BL or the initial complementary bit line BLB is turned on based on the column selection signal, and when the initial bit line BL or the initial complementary bit line BLB is turned on, the memory reads out data.
  • the specific connection mode of "source” and “drain” does not constitute a limitation to this embodiment.
  • this embodiment does not apply to the type of the first switching tube ⁇ 01> and the second switching tube ⁇ 02>
  • the first switching transistor ⁇ 01> and the second switching transistor ⁇ 02> may be NMOS transistors or PMOS transistors.
  • the first drive unit 101 one end of which is connected to the first readout bit line SABL, and the other end is connected to the second complementary readout bitline ISABLB, is used to turn on the first PMOS transistor ⁇ P1> or the first NMOS transistor ⁇ N1>.
  • the second drive unit 102 one end of which is connected to the first complementary read bit line SABLB, and the other end connected to the second read bit line ISABL, is used to turn on the second PMOS transistor ⁇ P2> or the second NMOS transistor ⁇ N2>.
  • the first storage unit and the second storage unit are used to store opposite data.
  • the initial bit line BL and the initial complementary bit line The level on BLB is opposite.
  • the first isolation MOS transistor ⁇ 11> and the second isolation MOS transistor ⁇ 12> are turned on, the levels of the initial bit line BL and the first read bit line SABL are the same, and the initial complementary bit line BLB It is the same as the level of the first complementary sense bit line SABLB, that is, the levels of the first sense bit line SABL and the first complementary sense bit line SABLB are different.
  • the levels of the first sense bit line SABL, the first complementary sense bit line SABLB, the second sense bit line ISABL, and the second complementary sense bit line ISABLB are the same, and During the pre-charging process, the first drive unit 101 and the second drive unit 102 are charged; when the first isolation MOS transistor ⁇ 11> and the second isolation MOS transistor ⁇ 12> are turned on, the first read bit The levels of the line SABL and the first complementary read bit line SABLB change, and the direction of change is opposite. At this time, in order to delay the level change of the first read bit line SABL and the first complementary read bit line SABLB, the first The driving unit 101 and the second driving unit 102 will discharge.
  • the discharge directions of the first drive unit 101 and the second drive unit 102 are opposite, resulting in the second read bit line ISABL and the second
  • the changing direction of the complementary readout bit line ISABLB is different, so that when the first PMOS transistor is turned on, the second NMOS transistor is also turned on, and when the second PMOS transistor is turned on, the first NMOS transistor is also turned on.
  • the first readout The bit line SABL and the first complementary read bit line SABLB are respectively pulled high or low under the action of the first level signal PCS and the second level signal NCS, and are synchronized to the initial bit line BL and the complementary initial bit line BLB, Thus, the data reading of the memory is completed.
  • the first driving unit 101 includes a first driving MOS transistor, the source and drain of the first driving MOS transistor are connected to the first read bit line SABL, and the gate is connected to the second complementary read bit line.
  • the second driving unit 102 includes a second driving MOS transistor, the source and drain of the second driving MOS transistor are connected to the first complementary read bit line SABLB, and the gate is connected to the second read bit line ISABL.
  • the first driving unit 101 includes a first driving MOS transistor, the source and drain of the first driving MOS transistor are connected to the second complementary readout bit line ISABLB, and the gate is connected to the first readout bit line ISABLB.
  • the first drive unit 101 includes a first drive capacitor, one end of the first drive capacitor is connected to the first read bit line SABL, and the other end is connected to the second complementary read bit line ISABLB;
  • the driving unit 102 includes a second driving capacitor, one end of the second driving capacitor is connected to the first complementary sense bit line SABLB, and the other end is connected to the second sense bit line ISABL.
  • MOS transistors as equivalent capacitors can complete corresponding functions with a smaller device size. Therefore, using MOS transistors as equivalent capacitors for driving can save the layout area of the sense amplifier circuit, thereby reducing memory The layout area is beneficial to increase the integration degree of the memory.
  • the sense amplifier circuit further includes: a precharge unit 300 for, according to the precharge signal, initial bit line BL, first read bit line SABL, second read bit line ISABL, The initial complementary bit line BLB, the first complementary sensing bit line SABLB, and the second complementary sensing bit line ISABLB are precharged to a preset voltage.
  • the precharge signal includes a first precharge signal EQ1 and a second precharge signal EQ2
  • the preset voltage includes a first preset voltage V1 and a second preset voltage V2
  • the precharge unit 300 includes: a first precharge MOS Tube ⁇ 31>, used to precharge the voltage of the initial bit line BL, the voltage of the first sense bit line SABL and the voltage of the second sense bit line ISABL to the first preset voltage V1 according to the first precharge signal EQ1 ;
  • the second precharge MOS transistor ⁇ 32> is used to precharge the voltage of the initial complementary bit line BLB, the voltage of the first complementary read bit line SABLB and the voltage of the second complementary read bit line ISABLB according to the second precharge signal EQ2 voltage to the second preset voltage V2.
  • the gate of the first precharge MOS transistor ⁇ 31> is used to receive the first precharge signal EQ1, the source is used to receive the first preset voltage V1, and the drain is connected to the initial bit line BL; the second precharge MOS transistor ⁇ 32> The gate is used to receive the second precharge signal EQ2, the source is used to receive the second preset voltage V2, and the drain is connected to the initial complementary bit line BLB.
  • the first precharge signal EQ1 and the second precharge signal EQ2 are the same, that is, the first precharge MOS transistor ⁇ 31> and the second precharge MOS transistor ⁇ 32> are based on the same precharge signal (Bit Line Equalizing Signal , EQ) conduction.
  • the specific connection mode of "source” and “drain” does not constitute a limitation to this embodiment.
  • the connection method of "drain” replacing “source” and “source” replacing “drain” can be adopted; in addition, this embodiment does not make any adjustments to the first pre-charging MOS transistor ⁇ 31> and the second pre-charging MOS transistor ⁇ 31>.
  • the type of charging MOS transistor ⁇ 32> is limited.
  • the first precharging MOS transistor ⁇ 31> and the second precharging MOS transistor ⁇ 32> can be NMOS transistors or PMOS transistors.
  • the sense amplifier circuit further includes: a first offset elimination unit 301 and a second offset elimination unit 302 , the first readout bit line SABL is connected to the second offset elimination unit 301
  • the sense bit line ISABL, the first complementary sense bit line SABLB is connected to the second complementary sense bit line ISABLB through the second offset canceling unit 302 .
  • the first offset canceling unit 301 includes a first offset canceling MOS transistor ⁇ 21>, the source of the first offset canceling MOS transistor ⁇ 21> is connected to the first readout bit line SABL, and the drain is connected to the second readout bit line SABL.
  • the bit line ISABL; the second offset elimination unit 302 includes a second offset elimination MOS transistor ⁇ 22>, the source of the second offset elimination MOS transistor ⁇ 22> is connected to the first complementary read bit line SABLB, and the drain is connected to The second complementary read bit line ISABLB; the gate of the first offset canceling MOS transistor ⁇ 21> and the gate of the second offset canceling MOS transistor ⁇ 22> are used to receive the offset canceling signal (Offset Canceling Signal, OC) , and based on the offset cancellation signal OC, eliminate the device difference between the first PMOS transistor ⁇ P1> and the second PMOS transistor ⁇ P2>, and eliminate the difference between the first NMOS transistor ⁇ N1> and the second NMOS transistor ⁇ N2> device differences.
  • the offset canceling signal Offset Canceling Signal, OC
  • the specific connection mode of "source” and “drain” does not constitute a limitation to this embodiment , in other embodiments, the connection method of "drain” replacing “source” and “source” replacing “drain” can be used; in addition, this embodiment does not eliminate the first offset of MOS transistor ⁇ 21> and The type of the second offset elimination MOS transistor ⁇ 22> is limited.
  • the first offset elimination MOS transistor ⁇ 21> and the second offset elimination MOS transistor ⁇ 22> can be NMOS transistors or PMOS tube.
  • the memory cells connected to the initial bit line and the memory cells connected to the complementary initial bit line respectively store a level greater than the preset voltage and a level lower than the preset voltage, that is, when the above two memory cells are respectively connected to the initial bit line and the initial complementary bit line
  • the first conduction unit and the second conduction unit are turned on, the initial bit line is electrically connected to the first readout bit line, and the initial complementary bit line and the second
  • a complementary read-out bit line is electrically connected so that the levels of the first read-out bit line and the first complementary read-out bit line are different;
  • the levels of the complementary read bit line, the second read bit line, and the second complementary read bit line are the same, and during the precharging process, the first drive unit and the second drive unit will be charged, when the first The turn-on unit and the second turn-on unit are turned on, the levels of the first read bit line and the first complementary read bit line change, and the direction of change is opposite.
  • the first drive unit and the second drive unit will discharge; since the direction of the level change of the first read bit line and the first complementary read bit line is opposite, the first drive unit and the first drive unit The discharge direction of the second drive unit is opposite, causing the second read bit line and the second complementary read bit line to change in different directions, so that when the first PMOS transistor is turned on, the second NMOS transistor is also turned on, and the second PMOS transistor is turned on. When it is turned on, the first NMOS transistor is also turned on.
  • the first readout bit line and the first complementary readout bit line are respectively pulled up to logic "1" under the action of the first level signal and the second level signal. High level or low level pulled to logic "0”, and synchronized to the initial bit line and the complementary initial bit line, thus completing the data readout of the memory.
  • Another embodiment of the present application provides a data readout method, based on the sense amplifier circuit provided by the above embodiment, including: providing a row selection signal and a column selection signal to turn on the selected memory cell; An electrical signal corresponding to logic "1” is provided, and an electrical signal corresponding to logic "0" is provided to the second signal terminal.
  • FIG. 4 is a schematic timing diagram of each control signal for the sense amplifier circuit in the data readout method provided by this embodiment
  • FIGS. 5 to 9 are the sense amplifier circuits corresponding to each stage in the data readout method provided by this embodiment.
  • the schematic diagram of the circuit state, the data readout method provided by this embodiment will be further described in detail below in conjunction with the accompanying drawings, specifically as follows:
  • the sense amplifier's read phase includes: a first sense phase S1 during the time period t0 to t1, a second sense phase S2 during the time period t1 to t4, and a third sense phase during the time period t4 to t5.
  • the second readout phase includes: the first processing sub-phase in the time period from t1 to t2, the second processing sub-phase in the time period from t2 to t3
  • the processing sub-phase is the third processing sub-phase in the time period from t3 to t4.
  • the precharge signal EQ is provided to turn on the precharged cells for the initial bit line BL, the first read bit line SABL, the second The sense bit line ISABL, the complementary bit line BLB, the first complementary sense bit line SABLB, and the second complementary sense bit line ISABLB are precharged.
  • the precharge signal EQ includes a first precharge signal EQ1 and a second precharge signal EQ2, wherein the first precharge MOS transistor ⁇ 31> is used to receive the first precharge signal EQ1, and the second precharge MOS transistor ⁇ 32> for receiving the second pre-charging signal EQ2.
  • the isolation signal ISO of the offset cancellation signal OC is simultaneously provided.
  • the first isolation MOS transistor ⁇ 11> and the second isolation MOS transistor ⁇ 12> are used to receive the isolation signal ISO, and the first offset elimination MOS transistor ⁇ 21> and the second offset elimination MOS transistor ⁇ 22> are used for An offset cancellation signal OC is received.
  • the first isolation MOS transistor ⁇ 11> and the second isolation MOS transistor ⁇ 12> are turned on based on the isolation signal ISO, and the first offset elimination MOS transistor ⁇ 21> and the second offset elimination MOS
  • the tube ⁇ 22> is turned on based on the offset cancel signal OC, so that the initial bit line BL, the first read bit line SABL and the second read bit line ISABL are connected, and the initial complementary bit line BLB, the first complementary read The bit line SABLB is connected to the second complementary sense bit line ISABLB.
  • the first precharge MOS transistor ⁇ 31> is turned on based on the first precharge signal EQ1 for precharging the initial bit line BL, the first read bit line SABL and the second read bit line ISABL;
  • the second precharge MOS The tube ⁇ 32> is turned on based on the second precharge signal EQ2, which is used to precharge the initial complementary bit line BLB, the first complementary read bit line SABLB and the second complementary read bit line ISABLB, that is, the first read phase S1
  • the purpose of is to precharge the sense amplifier circuit; in addition, in the precharge phase, the precharge voltage will charge the first driving unit 101 and the second driving unit 102 .
  • a row selection signal is provided to turn on the selected memory cells, so that the charges stored in the memory cells are shared to the initial bit line BL Or the initial complementary bit line BLB.
  • the precharge signal EQ is turned off
  • the isolation signal ISO is turned off, that is, the first isolation unit, the second isolation unit, and the precharge unit are turned off
  • a first level signal PCS is provided to the first signal terminal, that is, an electrical signal corresponding to a logic “1”
  • a second level signal NCS is provided to the second signal terminal, that is, an electrical signal corresponding to a logic “0”.
  • the voltages received by the gates of the first PMOS transistor ⁇ P1> and the second PMOS transistor ⁇ P2> belonging to the same PMOS are the same as the pre-charged voltage, but because the first PMOS transistor ⁇ P1> and the second PMOS transistor ⁇ P1>
  • the threshold voltage of the PMOS transistor ⁇ P2> is different, so that the opening degree of the source and drain channels of the first PMOS transistor ⁇ P1> and the second PMOS transistor ⁇ P2> is different, resulting in the first PMOS transistor ⁇ P1> and the second PMOS transistor ⁇ P2>
  • the equivalent resistance of the NMOS is different, and the voltage received by the gates of the first NMOS transistor ⁇ N1> and the second NMOS transistor ⁇ N2> belonging to the NMOS is the same as the pre-charged voltage, but because the first NMOS transistor ⁇ N1>
  • the threshold voltage of the second NMOS transistor ⁇ N2> is different, so that the opening degree of the source and drain channels of the
  • a row selection signal that is, a word line signal
  • the data stored in the memory cell is read out to the initial bit line BL or the initial complementary On the bit line BLB; during the process of providing the row selection signal, continue to provide the offset elimination signal OC; since the isolation signal ISO is turned off during the first processing sub-stage, the initial bit line BL and the first readout
  • the bit line SABL is not connected, and the initial mutual bit line BLB and the first complementary read bit line SABLB are complementary connected, that is, the level change of the initial bit line BL and the initial complementary bit line BLB does not affect the sense amplifier offset cancellation implement.
  • the period A (time period from t1 to t3) is used to eliminate the offset of the sense amplifier, so as to eliminate the difference between the first PMOS transistor ⁇ P1> and the second PMOS transistor ⁇ P2>. device differences between them, and eliminate device differences between the first NMOS transistor ⁇ N1> and the second NMOS transistor ⁇ N2>.
  • the offset cancellation signal OC is turned off, and the supply of the first level signal PCS and the second level signal NCS is stopped, that is, the sense amplifier is stopped. Offset removal operation.
  • the isolation signal ISO is provided to electrically connect the initial bit line BL to the first read bit line SABL, and the initial complementary bit line BLB to the first complementary read bit line SABLB.
  • the bit line BL performs charge sharing with the first sense bit line SABL
  • the initial complementary bit line BLB performs charge sharing with the first complementary sense bit line SABLB.
  • the third readout phase S3 refer to the time period from t4 to t5 in FIG. 4 and FIG. 7, that is, the data readout phase of the sense amplifier.
  • the first signal terminal is provided with the first level signal PCS, That is, the electrical signal corresponding to logic "1” is provided to the first signal terminal, and the second level signal NCS is provided to the second signal terminal, that is, the electrical signal corresponding to logic "0” is provided to the second signal terminal, so that The sense amplifier circuit outputs the logic "1” or the logic "0" corresponding to the data stored in the storage unit.
  • the offset elimination signal OC is turned off, and the isolation signal ISO is provided, that is, the first offset elimination MOS transistor ⁇ 21> and the second offset elimination MOS transistor ⁇ 22> are turned off, and the first isolation MOS transistor ⁇ 22> is turned on.
  • the first isolation MOS transistor ⁇ 11> and the second isolation MOS transistor ⁇ 12> are turned on, the levels of the first read bit line SABL and the first complementary read bit line SABLB change, and the direction of change is opposite, at this time , in order to delay the level change of the first read bit line SABL and the first complementary read bit line SABLB, the first drive unit 101 and the second drive unit 102 will discharge; since the first read bit line SABL and the first complementary read bit line The change direction of the level of the read bit line SABLB is opposite, and the discharge directions of the first drive unit 101 and the second drive unit 102 are opposite, so that the change directions of the second read bit line ISABL and the second complementary read bit line ISABLB are different, so that When the first PMOS transistor ⁇ P1> is turned on, the second NMOS transistor ⁇ N2> is also turned on.
  • the first NMOS transistor ⁇ N1> is also turned on.
  • the first readout The bit line SABL and the first complementary read bit line SABLB are respectively pulled up to the high level of logic “1” or pulled down to the low level of logic “0” under the action of the first level signal PCS and the second level signal NCS Level, and synchronized to the initial bit line BL and the complementary initial bit line BLB, thereby completing the data readout of the memory.
  • the fourth readout stage S4 namely, the recovery stage of the sense amplifier circuit, it is also used for precharging for the next data readout, and its specific details are the same as those of the first readout stage S1 , which will not be repeated here.

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Abstract

本申请实施例提供一种感测放大电路和数据读出方法，感测放大电路包括：第一PMOS管源极连接第一信号端，第一NMOS管源极连接第二信号端；第一PMOS管漏极和第一NMOS管漏极连接第一读出位线，栅极连接第二读出位线；第二PMOS管源极连接第一信号端，第二NMOS管源极连接第二信号端；第二PMOS管漏极和第二NMOS管漏极连接第一互补读出位线，栅极连接第二互补读出位线；第一导通单元一端连接连接第一读出位线，另一端连接初始位线；第二导通单元连一端接第一互补读出位线，另一端连接初始互补位线；第一驱动单元用于导通第一PMOS管或第一NMOS管；第二驱动单元用于导通第二PMOS管或第二NMOS管。

Description

感测放大电路和数据读出方法
相关申请的交叉引用
本公开基于申请号为202110821488.4、申请日为2021年07月20日、申请名称为“感测放大电路和数据读出方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此以全文引入的方式引入本公开。
技术领域
本申请涉及但不限于一种感测放大电路和数据读出方法。
背景技术
内存时序(Memory timings)是描述动态随机存取存储器(Dynamic Random Access Memory，DRAM)性能的四个参数，包括：CAS潜伏时间(CL)、行地址到列地址延迟(tRCD)、行预充电时间(tRP)和行活动时间(tRAS)。
行地址到列地址延迟tRCD，指打开一行内存并访问其中的列所需的最小时钟周期数，在DRAM的设计过程中，需使行打开到列打开的时间间隔t需大于tRCD，从而保证将存储单元中的数据正确读出。
然而，目前DRAM的数据读出过程中，行打开到列打开之间的时间即感测放大器的电荷分享阶段，通过电荷分享阶段的时间确保tRCD的延迟，造成感测放大器的读出流程时间较长，导致DRAM的数据读出时间较长。
发明内容
本申请实施例提供了一种感测放大电路，设置在相邻存储阵列之间，包括：第一PMOS管，其源极连接第一信号端，第一信号端用于接收第一电平信号；第一NMOS管，其源极连接第二信号端，第二信号端用于接收第二电平信号，第一电平信号大于第二电平信号；第一PMOS管的漏极和第一NMOS管的漏极连接第一读出位线，第一PMOS管的栅极和第一NMOS管的栅极连接第二读出位线；第二PMOS管，其源极连接第一信号端；第二NMOS管，其源极连接第二信号端；第二PMOS管的漏极和第二NMOS管的漏极连接第一互补读出位线，第二PMOS管的栅极和第二NMOS管的栅极连接第二互补读出位线；第一导通单元，其一端连接第一读出位线，其另一端连接初始位线，初始位线连接相邻存储阵列中一存储阵列的存储单元；第二导通单元，其一端连接第一互补读出位线，其另一端连接初始互补位线，初始互补位线连接相邻存储阵列中另一存储阵列的存储单元；第一驱动单元，其一端连接第一读出位线，其另一端连接第二互补读出位线，用于导通第一PMOS管或第一NMOS管；第 二驱动单元，其一端连接第一互补读出位线，其另一端连接第二读出位线，用于导通第二PMOS管或第二NMOS管。
本申请实施例还提供了一种数据读出方法，基于上述感测放大电路，包括：提供行选择信号、列选择信号以导通被选中的存储单元；向第一信号端提供逻辑“1”对应的电信号，并向第二信号端提供逻辑“0”对应的电信号。
附图说明
图1至图3为本申请一实施例提供的感测放大电路的电路结构示意图；
图4为本申请另一实施例提供的数据读出方法中对于感测放大电路的各个控制信号的时序示意图；
图5至图9为本申请另一实施例提供的数据读出方法中各阶段对应的感测放大电路的电路状态示意图。
具体实施方式
行地址到列地址延迟tRCD，指打开一行内存并访问其中的列所需的最小时钟周期数，在DRAM的设计过程中，需使行打开到列打开的时间间隔t需大于tRCD，从而保证将存储单元中的数据正确读出。
目前DRAM的数据读出过程中，行打开到列打开之间的时间即感测放大器的电荷分享阶段，通过电荷分享阶段的时间确保tRCD的延迟，造成感测放大器的读出流程时间较长，导致DRAM的数据读出时间较长。
本申请实施例以通过感测放大器不同的读出阶段来确保tRCD的延迟，以缩短感测放大器的读出流程时间，从而缩短DRAM的数据读出时间。
具体地，本申请一实施例提供了一种感测放大电路，设置在相邻存储阵列之间，包括：第一PMOS管，其源极连接第一信号端，第一信号端用于接收第一电平信号；第一NMOS管，其源极连接第二信号端，第二信号端用于接收第二电平信号，第一电平信号大于第二电平信号；第一PMOS管的漏极和第一NMOS管的漏极连接第一读出位线，第一PMOS管的栅极和第一NMOS管的栅极连接第二读出位线；第二PMOS管，其源极连接第一信号端；第二NMOS管，其源极连接第二信号端；第二PMOS管的漏极和第二NMOS管的漏极连接第一互补读出位线，第二PMOS管的栅极和第二NMOS管的栅极连接第二互补读出位线；第一导通单元，其一端连接第一读出位线，其另一端连接初始位线，初始位线连接相邻存储阵列中一存储阵列的存储单元；第二导通单元，其一端连接第一互补读出位线，其另一端连接初 始互补位线，初始互补位线连接相邻存储阵列中另一存储阵列的存储单元；第一驱动单元，其一端连接第一读出位线，其另一端连接第二互补读出位线，用于导通第一PMOS管或第一NMOS管；第二驱动单元，其一端连接第一互补读出位线，其另一端连接第二读出位线，用于导通第二PMOS管或第二NMOS管。
本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
图1至图3为本实施例提供的感测放大电路的电路结构示意图，以下结合附图对本实施例提供的感测放大电路作进一步详细说明，具体如下：
参考图1至图3，感测放大电路，包括：
第一PMOS管<P1>，其源极连接第一信号端，第一信号端用于接收第一电平信号(Positive Cell Storing Signal，PCS)。
第一NMOS管<N1>，其源极连接第二信号端，第二信号端用于接收第二电平信号Negative Cell Storing Signal，NCS)。
第一PMOS管<P1>的漏极和第一NMOS管<N1>和漏极连接第一读出位线SABL，第一PMOS管<P1>的栅极和第一NMOS管<N1>的栅极连接第二读出位线ISABL。
对于第一PMOS管<P1>和第一NMOS管<N1>，由于第一PMOS管<P1>栅极和第一NMOS管<N1>栅极的连接关系相同，即基于第二读出位线ISABL的不同电平，第一PMOS管<P1>或第一NMOS管<N1>导通时，第一PMOS管<P1>和第一NMOS管<N1>中仅存在一个导通的MOS管。
其中，第一电平信号PCS大于第二电平信号NCS，在一些实施例中，第一电平信号PCS为对应逻辑“1”的高电平，第二电平信号NCS为对应逻辑“0”的低电平。
具体地，当第一PMOS管<P1>导通后，第一信号端与第一读出位线SABL连通，从而将第一读出位线SABL拉高至第一电平信号PCS，进而将初始位线BL拉高至第一电平信号PCS，从而使存储器通过初始位线BL读出的数据为第一电平信号PCS对应逻辑“1”的高电平；当第一NMOS管<N1>导通后，第二信号端与第一读出位线SABL连通，从而将第一读出位线SABL拉低至第二电平信号NCS，进而将初始位线BL拉低至第二电平信号NCS，从而使存储器通过初始位线BL读出的数据为第二电平信号NCS对应逻辑“0”的低电平。
第二PMOS管<P2>，其源极连接第一信号端。
第二NMOS管<N2>，其源极连接第二信号端。
第二PMOS管<P2>的漏极和第二NMOS管<N2>的漏极连接第一互补读出位线SABLB，第二PMOS管<P2>的栅极和第二NMOS管<N2>的栅极连接第二互补读出位线ISABLB。
对于第二PMOS管<P2>和第二NMOS管<N2>，由于第二PMOS管<P2>栅极和第二NMOS管<N2>栅极的连接关系相同，即基于第二互补位线ISABLB的不同电平，第二PMOS管<P2>或第二NMOS管<N2>导通时，第二PMOS管<P2>和第二NMOS管<N2>中仅存在一个导通的MOS管。
具体地，当第二PMOS管<P2>导通后，第一信号端与第一互补读出位线SABLB连通，从而将第一互补读出位线SABLB拉高至第一电平信号PCS，进而将初始互补位线BLB拉高至第一电平信号PCS，从而使存储器通过初始互补位线BLB读出的数据为第一电平信号PCS对应逻辑“1”的高电平；当第二NMOS管<N2>导通后，第二信号端与第一互补读出位线SABLB连通，从而将第一互补读出位线SABLB拉低至第二电平信号NCS，进而将初始互补位线BLB拉低至第二电平信号NCS，从而使存储器通过初始互补位线BLB读出的数据为第二电平信号NCS对应逻辑“0”的低电平。
需要说明的是，对于第一PMOS管<P1>、第一NMOS管<N1>、第二PMOS管<P2>和第二NMOS管<N2>，具体“源极”和“漏极”的连接方式，并不构成对本实施例的限定，在其他实施例中，可以采用“漏极”替换“源极”，“源极”替换“漏极”的连接方式。
第一导通单元201，其一端连接第一读出位线SABL，其另一端连接初始位线BL，初始位线BL连接相邻存储阵列101中一存储阵列101的存储单元。
第二导通单元202，其一端连接第一互补读出位线SABLB，其另一端连接初始互补位线BLB，初始互补位线BLB连接相邻存储阵列101中另一存储阵列101的存储单元。
当第一导通单元201导通时，初始位线BL与第一读出位线SABL相连通，即初始位线BL和第一读出位线SABL的电平相同；第二导通单元202导通时，初始互补位线BLB与第一互补读出位线SABLB相连通，即初始互补位线BLB和第一互补位线SABLB的电平相同。
具体地，在一些实施例中，第一导通单元201包括第一隔离MOS管<11>，第一隔离MOS管<11>源极连接第一读出位线SABL，漏极连接初始位线BL；第二导通单元202包括第二隔离MOS管<12>，第二隔离MOS管<12>源极连接第一互补读出位线SABLB，漏极连接初始互补位线BLB；第一隔离MOS管<11>的栅极和第二隔离MOS管<12>的栅极用于接收隔离信号(Bit Line and SABL Isolation Signal，ISO)，并基于隔离信号ISO，使初始位线BL与第 一读出位线SABL电连接，并使初始互补位线BLB与第一互补读出位线SABLB电连接。
需要说明的是，对于第一隔离MOS管<11>和第二隔离MOS管<12>，具体“源极”和“漏极”的连接方式，并不构成对本实施例的限定，在其他实施例中，可以采用“漏极”替换“源极”，“源极”替换“漏极”的连接方式；另外，本实施例并不对第一隔离MOS管<11>和第二隔离MOS管<12>的类型进行限定，在具体的应用中，第一隔离MOS管<11>和第二隔离MOS管<12>可以为NMOS管，也可以为PMOS管。
在本实施例中，初始位线BL通过第一开关管<01>连接第一存储单元，互补初始位线BLB通过第二开关管<02>连接第二存储单元，
其中，第一存储单元和第二存储单元用于存储相反数据，即当第一存储单元存储对应逻辑“1”的高电平时，第二存储单元存储对应逻辑“0”的低电平；当第一存储单元存储对应逻辑“0”的低电平时，第二存储单元存储对应逻辑“1”的高电平时。
对于第一开关管<01>和第二开关管<02>，第一开关管<01>栅极连接字线WL，源极连接初始位线BL，漏极连接第一存储单元，第二开关管<02>栅极连接字线WL，源极连接初始互补BLB，漏极连接第二存储单元。
其中，字线WL用于基于行选择信号导通，字线WL导通时，字线WL所连接的开关管导通，将存储单元的电荷共享至初始位线BL或初始互补位线BLB上，初始位线BL或初始互补位线BLB基于列选择信号导通，初始位线BL或初始互补位线BLB导通时，存储器将数据读出。
需要说明的是，对于第一开关管<01>和第二开关管<02>，具体“源极”和“漏极”的连接方式，并不构成对本实施例的限定，在其他实施例中，可以采用“漏极”替换“源极”，“源极”替换“漏极”的连接方式；另外，本实施例并不对第一开关管<01>和第二开关管<02>的类型进行限定，在具体的应用中，第一开关管<01>和第二开关管<02>可以为NMOS管，也可以为PMOS管。
第一驱动单元101，其一端连接第一读出位线SABL，另一端连接第二互补读出位线ISABLB，用于导通第一PMOS管<P1>或第一NMOS管<N1>。
第二驱动单元102，其一端连接第一互补读出位线SABLB，另一端连接第二读出位线ISABL，用于导通第二PMOS管<P2>或第二NMOS管<N2>。
具体地，由上述内容可知第一存储单元和第二存储单元用于存储相反数据，当第一开关管<01>和第二开关管<02>打开后，初始位线BL和初始互补位线BLB上的电平相反，当第一 隔离MOS管<11>和第二隔离MOS管<12>打开后，初始位线BL和第一读出位线SABL的电平相同，初始互补位线BLB和第一互补读出位线SABLB的电平相同，即第一读出位线SABL和第一互补读出位线SABLB的电平不相同。在对感测放大电路进行预充电后，第一读出位线SABL、第一互补读出位线SABLB、第二读出位线ISABL、第二互补读出位线ISABLB的电平相同，且在预充电的过程中，会对第一驱动单元101和第二驱动单元102进行充电；当第一隔离MOS管<11>和第二隔离MOS管<12>导通后，第一读出位线SABL和第一互补读出位线SABLB的电平发生变化，且变化的方向相反，此时，为了延缓第一读出位线SABL和第一互补读出位线SABLB电平变化，第一驱动单元101和第二驱动单元102会进行放电。由于第一读出位线SABL和第一互补读出位线SABLB的电平变化方向相反，第一驱动单元101和第二驱动单元102放电方向相反，导致第二读出位线ISABL和第二互补读出位线ISABLB变化的方向不同，使第一PMOS管导通时，第二NMOS管也导通，第二PMOS管导通时，第一NMOS管也导通，此时第一读出位线SABL和第一互补读出位线SABLB分别在第一电平信号PCS和第二电平信号NCS的作用下拉高或拉低，并同步到初始位线BL和互补初始位线BLB上，从而完成存储器的数据读出。
在一个例子中，参考图1，第一驱动单元101包括第一驱动MOS管，第一驱动MOS管的源极和漏极连接第一读出位线SABL，栅极连接第二互补读出位线ISABLB；第二驱动单元102包括第二驱动MOS管，第二驱动MOS管的源极和漏极连接第一互补读出位线SABLB，栅极连接第二读出位线ISABL。
在另一例子中，参考图2，第一驱动单元101包括第一驱动MOS管，第一驱动MOS管的源极和漏极连接第二互补读出位线ISABLB，栅极连接第一读出位线SABL；第二驱动单元102包括第二驱动MOS管，第二驱动MOS管的源极和漏极连接第二读出位线ISABL，栅极连接第一互补读出位线SABLB。
在又一个例子中，参考图3，第一驱动单元101包括第一驱动电容，第一驱动电容的一端连接第一读出位线SABL，另一端连接第二互补读出位线ISABLB；第二驱动单元102包括第二驱动电容，第二驱动电容的一端连接第一互补读出位线SABLB，另一端连接第二读出位线ISABL。
MOS管作为等效电容相比于电容而言，可以以更小的器件尺寸完成相应功能，因此，采用MOS管作为等效电容进行驱动，可以节省感测放大电路的版图面积，从而减小存储器的版图面积，有利于增加存储器的集成度。
继续参考图1至图3，感测放大电路，还包括：预充电单元300，用于根据预充电信号， 对初始位线BL、第一读出位线SABL、第二读出位线ISABL、初始互补位线BLB、第一互补读出位线SABLB和第二互补读出位线ISABLB预充电至预设电压。
具体地，预充电信号包括第一预充电信号EQ1和第二预充电信号EQ2，预设电压包括第一预设电压V1和第二预设电压V2，预充电单元300包括：第一预充电MOS管<31>，用于根据第一预充电信号EQ1，预充电初始位线BL的电压、第一读出位线SABL的电压和第二读出位线ISABL的电压至第一预设电压V1；第二预充电MOS管<32>，用于根据第二预充电信号EQ2，预充电初始互补位线BLB的电压、第一互补读出位线SABLB和电压和第二互补读出位线ISABLB的电压至第二预设电压V2。
具体地，第一预充电MOS管<31>栅极用于接收第一预充电信号EQ1，源极用于接收第一预设电压V1，漏极连接初始位线BL；第二预充电MOS管<32>栅极用于接收第二预充电信号EQ2，源极用于接收第二预设电压V2，漏极连接初始互补位线BLB。
在一个例子中，第一预充电信号EQ1和第二预充电信号EQ2相同，即第一预充电MOS管<31>和第二预充电MOS管<32>基于同一预充电信号(Bit Line Equalizing Signal，EQ)导通。
在另一例子中，第一预设电压V1和第二预设电压V2相同，用于接收同一预设电压V BLP；在本实施例中，预设电压V BLP＝1/2V DD，其中，V DD为芯片内部电源电压；在一些实施例中，预充电电压V BLP可以根据具体应用场景进行设置。
需要说明的是，对于第一预充电MOS管<31>和第二预充电MOS管<32>，具体“源极”和“漏极”的连接方式，并不构成对本实施例的限定，在其他实施例中，可以采用“漏极”替换“源极”，“源极”替换“漏极”的连接方式；另外，本实施例并不对第一预充电MOS管<31>和第二预充电MOS管<32>的类型进行限定，在具体的应用中，第一预充电MOS管<31>和第二预充电MOS管<32>可以为NMOS管，也可以为PMOS管。
继续参考图1至图3，感测放大电路，还包括：第一偏移消除单元301和第二偏移消除单元302，第一读出位线SABL通过第一偏移消除单元301连接第二读出位线ISABL，第一互补读出位线SABLB通过第二偏移消除单元302连接第二互补读出位线ISABLB。
具体地，第一偏移消除单元301包括第一偏移消除MOS管<21>，第一偏移消除MOS管<21>的源极连接第一读出位线SABL，漏极连接第二读出位线ISABL；第二偏移消除单元302包括第二偏移消除MOS管<22>，第二偏移消除MOS管<22>的源极连接第一互补读出位线SABLB，漏极连接第二互补读出位线ISABLB；第一偏移消除MOS管<21>的栅极和第二偏 移消除MOS管<22>的栅极用于接收偏移消除信号(Offset Cancelling Signal，OC)，并基于偏移消除信号OC，消除第一PMOS管<P1>和第二PMOS管<P2>之间的器件差异，以及消除第一NMOS管<N1>和第二NMOS管<N2>之间的器件差异。
需要说明的是，对于第一偏移消除MOS管<21>和第二偏移消除MOS管<22>，具体“源极”和“漏极”的连接方式，并不构成对本实施例的限定，在其他实施例中，可以采用“漏极”替换“源极”，“源极”替换“漏极”的连接方式；另外，本实施例并不对第一偏移消除MOS管<21>和第二偏移消除MOS管<22>的类型进行限定，在具体的应用中，第一偏移消除MOS管<21>和第二偏移消除MOS管<22>可以为NMOS管，也可以为PMOS管。
初始位线连接的存储单元和互补初始位线连接的存储单元分别存储大于预设电压的电平和小于预设电压的电平，即当上述两个存储单元分别于初始位线和初始互补位线进行数据分享后初始位线和初始互补位线上的电平相反；第一导通单元和第二导通单元打开，初始位线和第一读出位线电连接，初始互补位线和第一互补读出位线电连接，使第一读出位线和第一互补读出位线的电平不相同；而对感测放大电路进行预充电后，第一读出位线、第一互补读出位线、第二读出位线、第二互补读出位线的电平相同，且在预充电的过程中，会对第一驱动单元和第二驱动单元进行充电，当第一导通单元和第二导通单元打开，第一读出位线和第一互补读出位线的电平发生变化，且变化的方向相反，此时，为了延缓第一读出位线和第一互补读出位线电平变化，第一驱动单元和第二驱动单元会进行放电；由于第一读出位线和第一互补读出位线的电平变化方向相反，第一驱动单元和第二驱动单元放电方向相反，导致第二读出位线和第二互补读出位线变化的方向不同，使第一PMOS管导通时，第二NMOS管也导通，第二PMOS管导通时，第一NMOS管也导通，此时第一读出位线和第一互补读出位线分别在第一电平信号和第二电平信号的作用下拉高至逻辑“1”的高电平或拉低至逻辑“0”的低电平，并同步到初始位线和互补初始位线上，从而完成存储器的数据读出。
需要说明的是，为了突出本申请的创新部分，本实施例中并没有将与解决本申请所提出的技术问题关系不太密切的单元引入，但这并不表明本实施例中不存在其它的单元；本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。
本申请另一实施例提供了一种数据读出方法，基于上述实施例提供的感测放大电路，包括：提供行选择信号、列选择信号以导通被选中的存储单元；向第一信号端提供逻辑“1”对应的电信号，并向第二信号端提供逻辑“0”对应的电信号。
图4为本实施例提供的数据读出方法中对于感测放大电路的各个控制信号的时序示意 图，图5至图9为本实施例提供的数据读出方法中各阶段对应的感测放大电路的电路状态示意图，以下结合附图对本实施例提供的数据读出方法作进一步详细说明，具体如下：
参考图4，感测放大器的读出阶段包括：在t0至t1时间段的第一读出阶段S1，在t1至t4时间段的第二读出阶段S2，在t4至t5时间段的第三读出阶段S3，在t5至t6时间段的第四读出阶段S4；其中，第二读出阶段包括：在t1至t2时间段的第一处理子阶段，在t2至t3时间段的第二处理子阶段，在t3至t4时间段的第三处理子阶段。
对于第一读出阶段S1，参考图4中t0至t1时间段以及图5，提供预充电信号EQ，以导通预充电单元，对初始位线BL、第一读出位线SABL、第二读出位线ISABL、互补位线BLB、第一互补读出位线SABLB和第二互补读出位线ISABLB预充电。
具体地，预充电信号EQ包括第一预充电信号EQ1和第二预充电信号EQ2，其中，第一预充电MOS管<31>用于接收第一预充电信号EQ1，第二预充电MOS管<32>用于接收第二预充电信号EQ2。
在提供预充电信号EQ的过程中，同时提供偏移消除信号OC的隔离信号ISO。
具体地，第一隔离MOS管<11>和第二隔离MOS管<12>用于接收隔离信号ISO，第一偏移消除MOS管<21>和第二偏移消除MOS管<22>用于接收偏移消除信号OC。
在第一读出阶段S1中，第一隔离MOS管<11>和第二隔离MOS管<12>基于隔离信号ISO导通，第一偏移消除MOS管<21>和第二偏移消除MOS管<22>基于偏移消除信号OC导通，使初始位线BL、第一读出位线SABL和第二读出位线ISABL之间相连通，初始互补位线BLB、第一互补读出位线SABLB和第二互补读出位线ISABLB之间相连通。
第一预充电MOS管<31>基于第一预充电信号EQ1导通，用于对初始位线BL、第一读出位线SABL和第二读出位线ISABL预充电；第二预充电MOS管<32>基于第二预充电信号EQ2导通，用于对初始互补位线BLB、第一互补读出位线SABLB和第二互补读出位线ISABLB预充电，即第一读出阶段S1的目的在于：对感测放大电路进行预充电；另外，在预充电阶段中，预充电电压会对第一驱动单元101和第二驱动单元102进行充电。
对于第二读出阶段S2，参考图4中t1至t4时间段以及图6和图7，提供行选择信号以导通被选中的存储单元，使存储单元中存储的电荷共享至初始位线BL或初始互补位线BLB。
具体地，对于第一处理子阶段，参考图4中t1至t2时间段以及图6，关闭预充电信号EQ，隔离信号ISO，即关闭第一隔离单元、第二隔离单元、预充电单元，并同时向第一信号端提供第一电平信号PCS，即提供逻辑“1”对应的电信号，向第二信号端提供第二电平信号 NCS，即提供逻辑“0”对应的电信号。
此时，同属于PMOS的第一PMOS管<P1>和第二PMOS管<P2>的栅极接收到的电压相同，与预充电后的电压，但由于第一PMOS管<P1>和第二PMOS管<P2>的阈值电压不同，使第一PMOS管<P1>和第二PMOS管<P2>源漏沟道开启程度不同，导致第一PMOS管<P1>和第二PMOS管<P2>的等效电阻不同，同属于NMOS的第一NMOS管<N1>和第二NMOS管<N2>的栅极接收到的电压相同，与预充电后的电压，但由于第一NMOS管<N1>和第二NMOS管<N2>的阈值电压不同，使第一NMOS管<N1>和第二NMOS管<N2>源漏沟道开启程度不同，导致第一NMOS管<N1>和第二NMOS管<N2>的等效电阻不同，从而微调第一读出位线SABL的电平和第一互补读出位线SABLB的电平。
对于第二处理子阶段，参考图4中t2至t3时间段，提供行选择信号，即字线信号，以选中存储单元，并将该存储单元存储的数据读出到初始位线BL或初始互补位线BLB上；在提供行选择信号的过程中，继续提供偏移消除信号OC；由于在第一处理子阶段的过程中，关闭了隔离信号ISO，此时初始位线BL和第一读出位线SABL并不连通，初始互不位线BLB和第一互补读出位线SABLB互补连通，即初始位线BL和初始互补位线BLB的电平变化并不影响感测放大器偏移消除的执行。
由此可知，在第二读出阶段S2的A段(t1至t3时间段)用于对感测放大器进行偏移消除，以消除第一PMOS管<P1>和第二PMOS管<P2>之间的器件差异，以及消除第一NMOS管<N1>和第二NMOS管<N2>之间的器件差异。
对于第三处理子阶段，参考图4中t3至t4时间段以及图7，关闭偏移消除信号OC，并停止提供第一电平信号PCS和第二电平信号NCS，即停止感测放大器的偏移消除操作。
在这一阶段的过程中，提供隔离信号ISO，以使初始位线BL和第一读出位线SABL电连接，初始互补位线BLB和第一互补读出位线SABLB电连接，此时初始位线BL和第一读出位线SABL进行电荷共享，初始互补位线BLB和第一互补读出位线SABLB进行电荷共享。
由此可知，在读出阶段S2的B段(t2至t4时间段)用于将初始位线BL连接的存储单元的电荷共享至第一读出位线SABL上，将初始互补位线BLB连接的存储单元的电荷共享至第一互补读出位线SABLB上。
对于第三读出阶段S3，参考图4中t4至t5时间段以及图7，即感测放大器的数据读出阶段，在这一阶段中，向第一信号端提供第一电平信号PCS，即向第一信号端提供逻辑“1”对应的电信号，并向所述第二信号端提供第二电平信号NCS，即向第二信号端提供逻辑“0” 对应的电信号，以使感测放大电路输出存储单元存储数据对应的逻辑“1”或所述逻辑“0”。在这一过程中，关闭偏移消除信号OC，并提供隔离信号ISO，即关断第一偏移消除MOS管<21>和第二偏移消除MOS管<22>，导通第一隔离MOS管<11>和第二隔离MOS管<12>。
当第一隔离MOS管<11>和第二隔离MOS管<12>打开，第一读出位线SABL和第一互补读出位线SABLB的电平发生变化，且变化的方向相反，此时，为了延缓第一读出位线SABL和第一互补读出位线SABLB电平变化，第一驱动单元101和第二驱动单元102会进行放电；由于第一读出位线SABL和第一互补读出位线SABLB的电平变化方向相反，第一驱动单元101和第二驱动单元102放电方向相反，导致第二读出位线ISABL和第二互补读出位线ISABLB变化的方向不同，使第一PMOS管<P1>导通时，第二NMOS管<N2>也导通，第二PMOS管<P2>导通时，第一NMOS管<N1>也导通，此时第一读出位线SABL和第一互补读出位线SABLB分别在第一电平信号PCS和第二电平信号NCS的作用下拉高至逻辑“1”的高电平或拉低至逻辑“0”的低电平，并同步到初始位线BL和互补初始位线BLB上，从而完成存储器的数据读出。
对于第四读出阶段S4，即感测放大电路的回复阶段，同时用于为下一次的数据读出进行预充电，其具体细节同第一读出阶段S1，在此不过多赘述。
由于上述实施例与本实施例相互对应，因此本实施例可与上述实施例互相配合实施。上述实施例中提到的相关技术细节在本实施例中依然有效，在上述实施例中所能达到的技术效果在本实施例中也同样可以实现，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在上述实施例中。
上面各读出阶段划分，只是为了描述清楚，实现时可以合并为一个读出阶段或者对某些读出阶段进行拆分，分解为多个读出阶段，只要控制信号的时序变化时刻相同，都在本专利的保护范围内；对读出阶段中添加无关紧要的修改或者引入无关紧要的设计，但不改变读出阶段的核心设计都在该专利的保护范围内；本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。

Claims (15)

  1. 一种感测放大电路，设置在相邻存储阵列之间，包括：
    第一PMOS管，其源极连接第一信号端，所述第一信号端用于接收第一电平信号；
    第一NMOS管，其源极连接第二信号端，所述第二信号端用于接收第二电平信号，所述第一电平信号大于所述第二电平信号；
    所述第一PMOS管的漏极和所述第一NMOS管的漏极连接第一读出位线，所述第一PMOS管的栅极和所述第一NMOS管的栅极连接第二读出位线；
    第二PMOS管，其源极连接所述第一信号端；
    第二NMOS管，其源极连接所述第二信号端；
    所述第二PMOS管的漏极和所述第二NMOS管的漏极连接第一互补读出位线，所述第二PMOS管的栅极和所述第二NMOS管的栅极连接第二互补读出位线；
    第一导通单元，其一端连接所述第一读出位线，其另一端连接初始位线，所述初始位线连接相邻所述存储阵列中一所述存储阵列的存储单元；
    第二导通单元，其一端连接所述第一互补读出位线，其另一端连接初始互补位线，所述初始互补位线连接相邻所述存储阵列中另一所述存储阵列的存储单元；
    第一驱动单元，其一端连接所述第一读出位线，其另一端连接所述第二互补读出位线，用于导通所述第一PMOS管或所述第一NMOS管；
    第二驱动单元，其一端连接所述第一互补读出位线，其另一端连接所述第二读出位线，用于导通所述第二PMOS管或所述第二NMOS管。
  2. 根据权利要求1所述的感测放大电路，其中，所述第一驱动单元包括：第一驱动MOS管；
    所述第一驱动MOS管的源极和漏极连接所述第一读出位线，栅极连接所述第二互补读出位线；
    或，所述第一驱动MOS管的源极和漏极连接所述第二互补读出位线，栅极连接所述第一读出位线。
  3. 根据权利要求1所述的感测放大电路，其中，所述第二驱动单元包括：第二驱动MOS管；
    所述第二驱动MOS管的源极和漏极连接所述第一互补读出位线，栅极连接所述第二读出位线；
    或，所述第二驱动MOS管的源极和漏极连接所述第二读出位线，栅极连接所述第一互补读出位线。
  4. 根据权利要求1所述的感测放大电路，包括：
    所述第一驱动单元包括第一驱动电容，所述第一驱动电容的一端连接所述第一读出位线，另一端连接所述第二互补读出位线；
    所述第二驱动单元包括第二驱动电容，所述第二驱动电容的一端连接所述第一互补读出位线，另一端连接所述第二读出位线。
  5. 根据权利要求1所述的感测放大电路，其中，所述第一导通单元包括第一隔离MOS管，所述第二导通单元包括第二隔离MOS管；
    所述第一隔离MOS管的源极连接所述第一读出位线，漏极连接所述初始位线；
    所述第二隔离MOS管的源极连接所述第一互补读出位线，漏极连接所述初始互补位线；
    所述第一隔离MOS管的栅极和所述第二隔离MOS管的栅极用于接收隔离信号，并基于所述隔离信号，使所述初始位线与所述第一读出位线电连接，并使所述初始互补位线与所述第一互补读出位线电连接。
  6. 根据权利要求1所述的感测放大电路，还包括：第一偏移消除单元和第二偏移消除单元，所述第一读出位线通过所述第一偏移消除单元连接所述第二读出位线，所述第一互补读出位线通过所述第二偏移消除单元连接所述第二互补读出位线。
  7. 根据权利要求6所述的感测放大电路，其中，所述第一偏移消除单元包括第一偏移消除MOS管，所述第二偏移消除单元包括第二偏移消除MOS管；
    所述第一偏移消除MOS管的源极连接所述第一读出位线，漏极连接所述第二读出位线；
    所述第二偏移消除MOS管的源极连接所述第一互补读出位线，漏极连接所述第二互补读出位线；
    所述第一偏移消除MOS管的栅极和所述第二偏移消除MOS管的栅极用于接收偏移消除信号，并基于所述偏移消除信号，消除所述第一PMOS管和所述第二PMOS管之间的器件差异，以及消除所述第一NMOS管和所述第二NMOS管之间的器件差异。
  8. 根据权利要求1所述的感测放大电路，还包括：预充电单元，用于根据预充电信号，对所述初始位线、所述第一读出位线、所述第二读出位线、所述初始互补位线、所述第一互补读出位线和所述第二互补读出位线预充电至预设电压。
  9. 根据权利要求8所述的感测放大电路，其中，所述预充电信号包括第一预充电信号和第二预充电信号，所述预设电压包括第一预设电压和第二预设电压，所述预充电单元包括：
    第一预充电MOS管，用于根据所述第一预充电信号，预充所述初始位线的电压、所述第一读出位线的电压和所述第二读出位线的电压至所述第一预设电压；
    第二预充电MOS管，用于根据所述第二预充电信号，预充所述初始互补位线的电压、 所述第一互补读出位线的电压和所述第二互补读出位线的电压至所述第二预设电压。
  10. 根据权利要求9所述的感测放大电路，，所述第一预充电MOS管的栅极用于接收所述第一预充电信号，源极用于接收所述第一预设电压，漏极连接所述初始位线；所述第二预充电MOS管的栅极用于接收所述第二预充电信号，源极用于接收所述第二预设电压，漏极连接所述初始互补位线。
  11. 根据权利要求9所述的感测放大电路，所述第一预充电信号和所述第二预充电信号相同。
  12. 根据权利要求9或11所述的感测放大电路，所述第一预设电压和所述第二预设电压相同。
  13. 一种数据读出方法，基于权利要求1至至12任一项所述的感测放大电路，包括：
    提供行选择信号以导通被选中的存储单元；
    向所述第一信号端提供逻辑“1”对应的电信号，并向所述第二信号端提供逻辑“0”对应的电信号。
  14. 根据权利要求13所述的数据读出方法，所述感测放大电路还包括预充电单元，在提供所述行选择信号和所述列选择信号之前，还包括：
    提供预充电信号，以导通所述预充电单元。
  15. 根据权利要求14所述的数据读出方法，所述感测放大电路还包括第一隔离单元、第二隔离单元、第一偏移消除单元和第二偏移消除单元；
    在提供预充电信号的过程中，同时提供偏移消除信号和隔离信号；
    在提供所述行选择信号之前，且在提供预充电信号之后，还包括：
    关闭所述第一隔离单元、所述第二隔离单元和所述预充电单元，并同时向所述第一信号端提供逻辑“1”对应的电信号，并向所述第二信号端提供逻辑“0”对应的电信号；
    在提供所述行选择信号的过程中，提供所述偏移消除信号；
    在向所述第一信号端提供逻辑“1”对应的电信号，并向所述第二信号端提供逻辑“0”对应的电信号的过程中，关闭所述偏移消除信号，并提供所述隔离信号。
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