WO2023133975A1 - 读出电路版图 - Google Patents
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- WO2023133975A1 WO2023133975A1 PCT/CN2022/078107 CN2022078107W WO2023133975A1 WO 2023133975 A1 WO2023133975 A1 WO 2023133975A1 CN 2022078107 W CN2022078107 W CN 2022078107W WO 2023133975 A1 WO2023133975 A1 WO 2023133975A1
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- 230000000295 complement effect Effects 0.000 claims abstract description 79
- 238000003379 elimination reaction Methods 0.000 claims description 45
- 230000008030 elimination Effects 0.000 claims description 42
- 238000002955 isolation Methods 0.000 claims description 36
- 238000010586 diagram Methods 0.000 description 35
- 230000003321 amplification Effects 0.000 description 9
- 238000003199 nucleic acid amplification method Methods 0.000 description 9
- 230000001360 synchronised effect Effects 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 230000009466 transformation Effects 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000000844 transformation Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
- G06F30/3947—Routing global
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/12—Printed circuit boards [PCB] or multi-chip modules [MCM]
Definitions
- the present disclosure relates to the field of semiconductor circuit design, in particular to a readout circuit layout.
- Dynamic Random Access Memory writes data through the charge in the cell capacitor; the cell capacitor is connected to the bit line and the complementary bit line.
- DRAM Dynamic Random Access Memory
- the sense amplifier senses and amplifies the voltage difference between the bit line and the complementary bit line.
- the inventors have found that the PMOS gate of the current sense amplifier is controlled by the sense bit line/complementary sense bit line, and there is a terminal connected to the sense bit line/complementary sense bit line, that is, after the PMOS is turned on, it may be affected
- the potential of the read bit line/complementary read bit line changes due to its own influence, thereby affecting the accuracy of data read out of the memory.
- An embodiment of the present disclosure provides a readout circuit layout, including: a first PMOS layout for forming a first PMOS transistor, the source of the first PMOS transistor is connected to the first signal terminal, and the first signal terminal is used to receive the first level signal; the first NMOS layout is used to form the first NMOS transistor, the source of the first NMOS transistor is connected to the second signal terminal, and the second signal terminal is used to receive the second level signal; the first level signal and the second signal terminal One of the two-level signals is a high-level signal, and the other is a low-level signal; the gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to the bit line, and the drain of the first PMOS transistor is connected to the first NMOS transistor.
- the drain of the NMOS transistor is connected to the complementary readout bit line;
- the second PMOS layout is used to form the second PMOS transistor, and the source of the second PMOS transistor is connected to the first signal terminal;
- the second NMOS layout is used to form the second NMOS transistor , the source of the second NMOS transistor is connected to the second signal terminal;
- the gate of the second PMOS transistor and the gate of the second NMOS transistor are connected to the complementary bit line, and the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor Read out the bit line; in the direction perpendicular to the extension of the bit line, the first PMOS layout and the second PMOS layout are symmetrically arranged, and the first NMOS layout and the second NMOS layout are symmetrically arranged.
- the readout circuit layout also includes: an offset elimination layout, used to form a first offset elimination MOS transistor and a second offset elimination MOS transistor; an isolation layout, used to form a first isolation MOS transistor and a second isolation MOS transistor ;
- the first offset elimination MOS transistor and the first isolation MOS transistor are arranged in the first region, and the first offset elimination MOS transistor and the first isolation MOS transistor share an active area;
- the second offset elimination MOS transistor and the second The isolation MOS transistor is arranged in the second region, and the second offset elimination MOS transistor and the second isolation MOS transistor share an active region; in a direction perpendicular to the extending direction of the bit line, the first region and the second region are arranged symmetrically.
- the source of the first offset elimination MOS transistor is connected to the bit line, the drain is connected to the complementary readout bit line, and the gate is used to receive the offset elimination signal;
- the source of the second offset elimination MOS transistor is connected to the complementary bit line, The drain is connected to the read bit line, and the gate is used to receive the offset canceling signal.
- the source of the first isolated MOS transistor is connected to the bit line, the drain is connected to the read bit line, and the gate is used to receive the isolation signal;
- the source of the second isolated MOS transistor is connected to the complementary bit line, and the drain is connected to the complementary read bit line, the gate is used to receive the isolated signal.
- the readout circuit layout also includes: a balanced charging layout, used to form a balanced charging module, wherein, the balanced charging layout is partially set in the first area and partially set in the second area; or, the first PMOS layout and the second PMOS layout
- the PMOS layout is symmetrically set based on the balanced charging layout
- the first NMOS layout and the second NMOS layout are symmetrically set based on the balanced charging layout
- the first area and the second area are symmetrically set based on the balanced charging layout.
- one end of the equalization charging module is connected to the readout bit line, and the other end is connected to the complementary readout bit line, for equalizing the readout bit line and the complementary readout bit line to a preset voltage.
- the balanced charging module includes: the first precharge MOS transistor, the source of which is connected to the complementary readout bit line; the second precharge MOS transistor, the source of which is connected to the readout bit line; the drain of the first precharge MOS transistor and the second The drains of the two pre-charged MOS tubes are used to receive the preset voltage, the gates of the first pre-charged MOS tube and the gates of the second pre-charged MOS tube are used to receive the pre-charged signal; the balanced MOS tubes, the source is connected to the complementary reading A bit line is output, the drain is connected to the read bit line, and the gate is used to receive the balanced signal.
- the balanced charging module includes: the first precharge MOS transistor, the source of which is connected to the complementary readout bit line; the second precharge MOS transistor, the source of which is connected to the readout bit line; the drain of the first precharge MOS transistor and the second The drain of the two pre-charged MOS tubes is used to receive the preset voltage; the equalized MOS tube, the source is connected to the complementary readout bit line, and the drain is connected to the readout bit line; the gate of the first pre-charged MOS tube, the second pre-charged MOS tube The gate of the MOS transistor and the gate of the balanced MOS transistor are used to receive the balanced signal.
- the balanced charging layout is used to form the first pre-charged MOS tube, the second pre-charged MOS tube and the balanced MOS tube, wherein the gate of the first pre-charged MOS tube, the gate of the second pre-charged MOS tube and the balanced MOS tube
- the gates of the tubes extend in the same direction; the first pre-charge MOS tube, the second pre-charge MOS tube and the balance MOS tube share an active area.
- the balanced charging module includes: a pre-charged MOS tube, the source is connected to the complementary readout bit line or connected to the readout bit line, the drain is used to receive the preset voltage, and the gate is used to receive the pre-charge signal; the balanced MOS tube, The source is connected to the complementary readout bit line, the drain is connected to the readout bit line, and the gate is used to receive the balanced signal.
- the balanced charging module includes: a pre-charged MOS tube, the source is connected to the complementary readout bit line or connected to the readout bit line, and the drain is used to receive the preset voltage; the balanced MOS tube, the source is connected to the complementary readout bit line, The drain is connected to the readout bit line; the gate of the precharge MOS transistor and the gate of the balance MOS transistor are used to receive the balance signal.
- the balanced charging layout is used to form the pre-charged MOS tube and the balanced MOS tube, wherein the gate of the pre-charged MOS tube and the grid of the balanced MOS tube extend in the same direction; the pre-charged MOS tube and the balanced MOS tube share an active area.
- the gate of the first PMOS layout, the gate of the second PMOS layout, the gate of the first NMOS layout, and the gate of the second NMOS layout extend in the same direction, and the extension direction of the gate of the first PMOS layout is equal to The gate extension directions of the MOS layout intersect.
- the gate of the first NMOS layout and the gate of the second NMOS layout extend in the same direction
- the gate of the first PMOS layout, the gate of the second PMOS layout and the grid in the balanced charging layout extend in the same direction
- the first The extending direction of the gate in the NMOS layout intersects with the extending direction of the gate in the balanced MOS charging layout.
- the active areas for receiving the pre-charging signal are connected to each other.
- FIG. 1 is a schematic circuit structure diagram of a sense amplifier circuit provided by an embodiment of the present disclosure
- FIG. 2 is a schematic diagram of the circuit structure of the first balanced charging module provided by an embodiment of the present disclosure
- FIG. 3 is a schematic diagram of a circuit structure of a second balanced charging module provided by an embodiment of the present disclosure
- FIG. 4 is a schematic diagram of a circuit structure of a third balanced charging module provided by an embodiment of the present disclosure
- FIG. 5 is a schematic diagram of a circuit structure of a fourth balanced charging module provided by an embodiment of the present disclosure
- FIG. 6 is a schematic diagram of a working sequence of a sense amplifier circuit provided by an embodiment of the present disclosure.
- FIG. 7 is a schematic diagram of the layout of the first circuit corresponding to the equalizing charging module shown in FIG. 2 or FIG. 3 provided by the embodiment of the present disclosure
- FIG. 8 is a schematic diagram of the layout of the second type of circuit corresponding to the equalizing charging module shown in FIG. 2 or FIG. 3 provided by an embodiment of the present disclosure
- FIG. 9 is a schematic diagram of a third type of circuit provided by an embodiment of the present disclosure corresponding to a circuit with the equalization charging module shown in FIG. 2 or FIG. 3 ;
- FIG. 10 is a schematic diagram of a fourth type of circuit provided by an embodiment of the present disclosure corresponding to a circuit with the equalization charging module shown in FIG. 2 or FIG. 3 ;
- FIG. 11 is a schematic diagram of the layout of the fifth circuit corresponding to the equalizing charging module shown in FIG. 2 or FIG. 3 provided by an embodiment of the present disclosure
- FIG. 12 is a schematic diagram of the layout of the active areas of the balanced charging module used to receive the pre-charging signal in FIGS. 7 to 11 provided by an embodiment of the present disclosure
- FIG. 13 is a schematic diagram of the layout of the first circuit corresponding to the equalizing charging module shown in FIG. 4 or FIG. 5 provided by an embodiment of the present disclosure
- Fig. 14 is a schematic diagram of the layout of the first circuit corresponding to the equalizing charging module shown in Fig. 4 or Fig. 5 provided by the embodiment of the present disclosure;
- FIG. 15 is a schematic diagram of the layout of the first circuit corresponding to the equalizing charging module shown in FIG. 4 or FIG. 5 provided by the embodiment of the present disclosure;
- FIG. 16 is a schematic structural diagram of another PMOS layout provided by an embodiment of the present disclosure.
- the PMOS gate of the sense amplifier is controlled by the sense bit line/complementary sense bit line, and there is a terminal connected to the sense bit line/complementary sense bit line, that is, after the PMOS in the sense amplifier is turned on, it may be Affected by itself, the potential of the read bit line/complementary read bit line changes, thereby affecting the accuracy of data read out of the memory.
- An embodiment of the present disclosure provides a readout circuit layout to improve the readout accuracy of a sense amplifier.
- Figure 1 is a schematic diagram of the circuit structure of the sense amplifier circuit provided in this embodiment
- Figure 2 is a schematic diagram of the circuit structure of the first balanced charging module provided in this embodiment
- Figure 3 is a schematic diagram of the second balanced charging module provided in this embodiment
- Figure 4 is a schematic diagram of the circuit structure of the third balanced charging module provided in this embodiment
- Figure 5 is a schematic diagram of the circuit structure of the fourth balanced charging module provided in this embodiment
- Figure 6 is a schematic diagram of the circuit structure provided in this embodiment
- Figure 7 is a schematic diagram of the layout of the first circuit provided by this embodiment corresponding to the circuit with the equalization charging module shown in Figure 2 or Figure 3
- Figure 8 is a schematic diagram of the second circuit provided by this embodiment
- the first type corresponds to a schematic layout diagram of a circuit having a balanced charging module shown in FIG.
- FIG. 9 is a schematic layout diagram corresponding to a circuit having a balanced charging module shown in FIG. 2 or FIG. 3 provided by this embodiment.
- Figure 10 is a schematic diagram of the layout of the fourth type provided by this embodiment corresponding to the circuit with the equalization charging module shown in Figure 2 or Figure 3
- Figure 11 is the fifth type provided by this embodiment corresponding to the circuit with the equalization charging module shown in Figure 2 or Figure 3
- Figure 12 is a schematic diagram of the layout of the circuit of the balanced charging module.
- Figure 12 is a schematic diagram of the layout of the active areas of the balanced charging module in Figures 7 to 11 for receiving pre-charging signals provided by this embodiment.
- Figure 13 is a schematic diagram of the layout provided by this embodiment.
- the first type corresponds to a schematic diagram of the layout of a circuit with a balanced charging module shown in Figure 4 or Figure 5
- Figure 14 is the first type provided in this embodiment corresponding to the layout of a circuit with a balanced charging module shown in Figure 4 or Figure 5
- Schematic diagram Fig. 15 is a schematic diagram of the layout of the first circuit corresponding to the balanced charging module shown in Fig. 4 or Fig. 5 provided by this embodiment
- Fig. 16 is a schematic diagram of the structure of another PMOS layout provided by this embodiment, as follows
- the readout circuit layout provided by this embodiment is further described in detail in conjunction with the accompanying drawings, as follows:
- circuit layout including:
- the first PMOS layout is used to form the first PMOS transistor ⁇ P1>, the source of the first PMOS transistor ⁇ P1> is connected to the first signal terminal (Positive Cell Storing Signal, PCS), specifically, the first signal terminal PCS is used for Receive a first level signal.
- PCS Positive Cell Storing Signal
- the first NMOS layout is used to form the first NMOS transistor ⁇ N1>, the source of the first NMOS transistor ⁇ N1> is connected to the second signal terminal (Negative Cell Storing Signal, NCS), specifically, the second signal terminal NCS is used for Receive the second level signal.
- NCS Native Cell Storing Signal
- One of the first level signal and the second level signal is a high level signal, and the other is a low level signal.
- the gate of the first PMOS transistor ⁇ P1> and the gate of the first NMOS transistor ⁇ N1> are connected to the bit line BL, and the drain of the first PMOS transistor ⁇ P1> is connected to the drain of the first NMOS transistor ⁇ N1> Complementary sense bit line SABLB.
- the second PMOS layout is used to form the second PMOS transistor ⁇ P2>, and the source of the second PMOS transistor ⁇ P2> is connected to the first signal terminal PCS.
- the second NMOS layout is used to form the second NMOS transistor ⁇ N2>, and the source of the second NMOS transistor ⁇ N2> is connected to the second signal terminal NCS.
- the gate of the second PMOS transistor ⁇ P2> and the gate of the second NMOS transistor ⁇ N2> are connected to the complementary bit line BLB, and the drain of the second PMOS transistor ⁇ P2> is connected to the drain of the second NMOS transistor ⁇ N2> to read bit line SABL.
- the first PMOS layout and the second PMOS layout are arranged symmetrically, and the first NMOS layout and the second NMOS layout are arranged symmetrically.
- the gates of the first PMOS transistor and the first NMOS transistor are directly connected to the bit line, the gates of the second PMOS transistor and the second NMOS transistor are directly connected to the complementary bit line, and the first PMOS transistor and the first NMOS transistor are connected through the same gate relationship, so as to accurately realize the amplification of the potential of the bit line, and the second PMOS transistor and the second NMOS transistor have the same gate connection relationship, so as to accurately realize the amplification of the potential of the complementary bit line, thereby improving the readout accuracy of the sense amplifier.
- the first level signal takes the first level signal as a high level corresponding to logic "1” and the second level signal as a low level corresponding to logic “0” as an example to describe the sense amplifier circuit provided by the present disclosure. Specifically, this does not constitute a limitation to this embodiment.
- the first level signal may be a low level corresponding to logic "0”
- the second level signal may be a high level corresponding to logic "1”.
- the role of the sense amplifier is to invert and amplify the bit line data, and then invert the data during the output process to output the original data.
- the read circuit layout further includes: an offset elimination layout and an isolation layout, wherein the offset elimination layout is used to form the first offset elimination MOS transistor ⁇ 21> and the second offset elimination MOS transistor ⁇ 22>, the isolation layout is used to form the first isolation MOS transistor ⁇ 11> and the second isolation MOS transistor ⁇ 12>; the first offset elimination MOS transistor ⁇ 21> and the first isolation MOS transistor ⁇ 11> are arranged in the first area , and the first offset elimination MOS transistor ⁇ 21> and the first isolation MOS transistor ⁇ 11> share the active area, and the second offset elimination MOS transistor ⁇ 22> and the second isolation MOS transistor ⁇ 12> are arranged in the second In the region, the second offset elimination MOS transistor ⁇ 22> and the second isolation MOS transistor ⁇ 12> share the active region, and the first region and the second region are arranged symmetrically in the direction perpendicular to the extending direction of the bit line.
- the offset elimination layout is used to form the first offset elimination MOS transistor ⁇ 21> and the second offset
- the offset elimination module 201 includes a first offset elimination MOS transistor ⁇ 21> and a second offset elimination MOS transistor ⁇ 22>, wherein the source of the first offset elimination MOS transistor ⁇ 21> Connect to the bit line BL, connect the drain to the complementary read bit line SABLB, and the gate to receive the offset cancellation signal OC, connect the source of the second offset cancellation MOS transistor ⁇ 22> to the complementary bit line BLB, and connect the drain to the read bit Line SABL, the gate is used to receive the offset cancellation signal OC.
- the isolation module 301 includes a first isolation MOS transistor ⁇ 11> and a second isolation MOS transistor ⁇ 12>, wherein the source of the first isolation MOS transistor ⁇ 11> is connected to the bit line BL, and the drain is connected to the read The output bit line SABL, the gate is used to receive the isolation signal ISO, the source of the second isolation MOS transistor ⁇ 12> is connected to the complementary bit line BLB, the drain is connected to the complementary read bit line SABLB, and the gate is used to receive the isolation signal ISO.
- the gates of the first PMOS transistor ⁇ P1> and the first NMOS transistor ⁇ N1> are directly connected to the bit line BL, and the bias voltage after offset elimination will first appear in the complementary readout On the bit line SABLB, that is, the bias voltage will not affect the stability of the offset elimination of the first PMOS transistor ⁇ P1> and the first NMOS transistor ⁇ N1>.
- the bias voltage When the bias voltage is synchronized to the bit line BL, it is already Completing the offset elimination process, that is, by directly controlling the gates of the first PMOS transistor ⁇ P1> and the first NMOS transistor ⁇ N1> through the bit line BL, it is also used to improve the stability of the sense amplifier circuit for offset elimination; Similarly, the gates of the second PMOS transistor ⁇ P2> and the second NMOS transistor ⁇ N2> are directly connected to the complementary bit line BLB, and the bias voltage after offset elimination will first appear on the read bit line SABL, that is, the bias voltage The set voltage will not affect the stability of the offset elimination of the second PMOS transistor ⁇ P2> and the second NMOS transistor ⁇ N2>.
- the offset elimination process has been completed at this time. That is, by directly controlling the gates of the second PMOS transistor ⁇ P2> and the second NMOS transistor ⁇ N2> through the complementary bit line BLB, it is also used to improve the stability of the sense amplifier circuit for offset elimination.
- the read circuit layout further includes: an equalized charge layout, wherein the equalized charge layout is used to form an equalized charge module, and the equalized charge layout is partially arranged in the first area and partially arranged in the second area, or
- the first PMOS layout and the second PMOS layout are set symmetrically based on the balanced charging layout
- the first NMOS layout and the second NMOS layout are symmetrically set based on the balanced charging layout
- the first area and the second area are symmetrically set based on the balanced charging layout.
- the balanced charging module 101 is connected to the read bit line SABL at one end, and connected to the complementary read bit line SABLB at the other end, for equalizing the read bit line SABL and the complementary read bit line SABLB to a preset voltage VBLP.
- the balanced charging module 101 includes a first pre-charged MOS transistor, a second pre-charged MOS transistor and a balanced MOS transistor, wherein the source of the first pre-charged MOS transistor is connected to the complementary readout bit line SABLB , the source of the second pre-charge MOS tube is connected to the read bit line SABL, the drain of the first pre-charge MOS tube and the drain of the second pre-charge MOS tube are used to receive the preset voltage VBLP, the first pre-charge MOS tube The gate of the gate and the gate of the second pre-charge MOS transistor are used to receive the pre-charge signal (Pre-charge Signal, PRE), the source of the balanced MOS transistor is connected to the complementary read bit line SABLB, and the drain is connected to the read bit line SABL , the gate is used to receive the equalizing signal (Equalizing Signal, EQ).
- PRE pre-charge Signal
- PRE pre-charge Signal
- the source of the balanced MOS transistor is connected to the complementary read bit line SABLB
- the drain is
- the balanced charging module 101 includes a first precharged MOS transistor, a second precharged MOS transistor, and a balanced MOS transistor, wherein the source of the first precharged MOS transistor is connected to the complementary readout bit line SABLB , the source of the second precharge MOS transistor is connected to the read bit line SABL, the drain of the first precharge MOS transistor and the drain of the second precharge MOS transistor are used to receive the preset voltage VBLP, and the source of the balanced MOS transistor Connected to the complementary readout bit line SABLB, the drain is connected to the readout bitline SABL, the gate of the first precharge MOS transistor, the gate of the second precharge MOS transistor and the gate of the equalization MOS transistor are used to receive the equalization signal EQ.
- the equalization charging layout is used to form the first pre-charging MOS transistor.
- the second pre-charging MOS tube and the balancing MOS tube wherein the gate of the first pre-charging MOS tube, the grid of the second pre-charging MOS tube and the grid of the balancing MOS tube extend in the same direction, the first pre-charging MOS tube, the second pre-charging MOS tube
- the two pre-charging MOS tubes and the equalizing MOS tubes share an active area.
- the balanced charging layout is set in the middle position
- the first PMOS layout and the second PMOS layout are symmetrically set based on the balanced charging layout
- the first NMOS layout and the second NMOS layout are symmetrically set based on the balanced charging layout.
- the first area and the second area are set symmetrically based on the balanced charging layout, and the first area is set on the side of the first PMOS layout and the first NMOS layout away from the balanced charging layout, and the second area is set on the second PMOS layout and the second NMOS layout.
- the layout is far away from the side of the balanced charging layout; it should be noted that in this example, the positions of the first PMOS layout and the first NMOS layout can be interchanged, and correspondingly, the positions of the second PMOS layout and the second NMOS layout can be interchanged. Change.
- the balanced charging layout is set in the middle position
- the first PMOS layout and the second PMOS layout are symmetrically set based on the balanced charging layout
- the first NMOS layout and the second NMOS layout are symmetrically set based on the balanced charging layout.
- the first area and the second area are arranged symmetrically based on the balanced charging layout, and the first area is set between the first PMOS layout and the first NMOS layout, and the second area is set between the second PMOS layout and the second NMOS layout; it is required It should be noted that, in this example, the positions of the first PMOS layout and the first NMOS layout can be interchanged, and correspondingly, the positions of the second PMOS layout and the second NMOS layout can be interchanged.
- the balanced charging layout is set in the middle position
- the first PMOS layout and the second PMOS layout are symmetrically set based on the balanced charging layout
- the first NMOS layout and the second NMOS layout are symmetrically set based on the balanced charging layout.
- the first area and the second area are set symmetrically based on the balanced charging layout, and the first area is set on the side of the first PMOS layout and the first NMOS layout close to the balanced charging layout, and the second area is set on the second PMOS layout and the second NMOS layout.
- the layout is close to the side of the balanced charging layout; it should be noted that, in this example, the positions of the first PMOS layout and the first NMOS layout can be interchanged, and correspondingly, the positions of the second PMOS layout and the second NMOS layout can be interchanged. Change.
- the first PMOS layout and the second PMOS layout are arranged symmetrically, the first NMOS layout and the second NMOS layout are symmetrically arranged, the first region and the second region are symmetrically arranged, and the balanced charging layout is arranged in the first area; it should be noted that in this example, the positions of the first PMOS layout and the first NMOS layout can be interchanged, and the balanced charging layout can also be set in the second area; in addition, the structure shown in Figure 10 is also applicable to Similar to the transformation of Fig. 7 ⁇ Fig. 8 and Fig. 7 ⁇ Fig. 9 .
- the first pre-charge MOS transistor is set in the first area
- the second pre-charge MOS tube is set in the second area
- the balanced MOS tube is set in the middle position
- the layout and the second PMOS layout are symmetrically set based on the balanced MOS transistors
- the first NMOS layout and the second NMOS layout are symmetrically set based on the balanced MOS transistors
- the first area and the second area are symmetrically set based on the balanced MOS transistors
- the first area is set at the One PMOS layout and the first NMOS layout are close to the side of the balanced charging layout
- the second area is set on the side of the second PMOS layout and the second NMOS layout close to the balanced charging layout
- the first The positions of the PMOS layout and the first NMOS layout can be interchanged, and correspondingly, the positions of the second PMOS layout and the second NMOS layout can be interchanged; in addition,
- the active regions for receiving the precharge signal are connected to each other, so as to simplify the layout wiring when the precharge signal is subsequently connected, and increase the driving capability of the active region for receiving the precharge signal .
- the balanced charging module 101 includes a pre-charged MOS transistor and a balanced MOS transistor, wherein the source of the pre-charged MOS transistor is connected to the complementary read bit line SABLB or connected to the read bit line SABL, and the drain is used for For receiving the preset voltage, the gate is used to receive the precharge signal PRE, the source of the equalization MOS transistor is connected to the complementary readout bit line SABLB, the drain is connected to the readout bitline SABL, and the gate is used to receive the equalization signal EQ.
- the balance charging module 101 includes a precharge MOS transistor and a balance MOS transistor.
- the source of the precharge MOS transistor is connected to the complementary read bit line SABLB or connected to the read bit line SABL, and the drain is used to receive The voltage is preset, the source of the balanced MOS transistor is connected to the complementary read bit line SABLB, the drain is connected to the read bit line SABL, the gate of the precharge MOS transistor and the gate of the balanced MOS transistor are used to receive the balanced signal EQ.
- the balanced charging layout is used to form a pre-charged MOS transistor and a balanced MOS transistor, wherein the gate of the pre-charged MOS transistor and the gate of the balanced MOS transistor extend in the same direction, and the pre-charged MOS transistor extends in the same direction.
- the MOS transistor and the balanced MOS transistor share an active area.
- the balanced charging layout is set in the middle position
- the first PMOS layout and the second PMOS layout are symmetrically set based on the balanced charging layout
- the first NMOS layout and the second NMOS layout are symmetrically set based on the balanced charging layout.
- the first area and the second area are set symmetrically based on the balanced charging layout, and the first area is set on the side of the first PMOS layout and the first NMOS layout away from the balanced charging layout, and the second area is set on the second PMOS layout and the second NMOS layout.
- the layout is far away from the side of the balanced charging layout; it should be noted that in this example, the positions of the first PMOS layout and the first NMOS layout can be interchanged, and correspondingly, the positions of the second PMOS layout and the second NMOS layout can be interchanged.
- the structure shown in Figure 13 is also applicable to transformations similar to Figure 7 ⁇ Figure 8 and Figure 7 ⁇ Figure 9.
- the first PMOS layout and the second PMOS layout are symmetrically arranged, the first NMOS layout and the second NMOS layout are symmetrically arranged, the first region and the second region are symmetrically arranged, and the balanced charging layout is arranged at the
- the positions of the first PMOS layout and the first NMOS layout can be interchanged, and the balanced charging layout can also be set in the second area; in addition, the structure shown in Figure 10 is also applicable In the transformation similar to Fig. 7 ⁇ Fig. 8 and Fig. 7 ⁇ Fig. 9 .
- the precharge MOS transistor is arranged in the first region
- the balanced MOS transistor is arranged in the second region
- the first PMOS layout and the second PMOS layout are symmetrically arranged
- the layout and the second NMOS layout are set symmetrically, and the first area and the second area are set symmetrically.
- the positions of the first PMOS layout and the first NMOS layout can be interchanged, and the balanced charging layout can also be set In the second area;
- the structure shown in FIG. 10 is also applicable to transformations similar to those shown in FIG. 7 ⁇ FIG. 8 and FIG. 7 ⁇ FIG. 9 .
- the active areas for receiving the pre-charge signal are connected to each other, so as to simplify the layout connection when the pre-charge signal is subsequently connected, and to increase the area used for receiving the pre-charge signal.
- the drive capability of the active area of the signal is not limited to
- the gates of the first PMOS layout, the gates of the second PMOS layout, the gates of the first NMOS layout and the gates of the second NMOS layout extend in the same direction, and the first PMOS
- the extending direction of the gate of the layout intersects the extending direction of the gate of the balanced MOS layout.
- the gate of the first NMOS layout and the gate of the second NMOS layout extend in the same direction, and the gate of the first PMOS layout transistor and the gate of the second PMOS layout
- the extending direction of the gate is the same as that in the balanced charging layout, and the extending direction of the transistor gate in the first NMOS layout intersects with the extending direction of the gate in the balanced MOS charging layout.
- the preset voltage VBLP 1/2VDD, where VDD is the internal power supply voltage of the chip; in other embodiments, the preset voltage VBLP can be set according to specific application scenarios.
- the semiconductor devices constituting the sense amplifier may have different device characteristics (eg, threshold voltage) due to process variation, temperature and other factors. Different device characteristics lead to offset noise in the sense amplifier, which reduces the effective read margin of the sense amplifier and degrades the performance of the DRAM.
- the sense amplifier circuit For the sense amplifier circuit provided in the present disclosure, its amplification process includes four stages. Referring to FIG. 6, in the first stage S1 (t0 ⁇ t1), an equalization signal EQ, a precharge signal PRE, an isolation signal ISO, and an offset Eliminate the signal OC to correlate all lines in the sense amplifier circuit and precharge all lines to a preset voltage; in the second stage S2 (t1 ⁇ t2), continue to provide the offset elimination signal OC, and supply the first
- the signal terminal PCS provides the first voltage, and supplies the second voltage to the second signal terminal NCS, and the amplification difference between the first NMOS transistor ⁇ N1> and the second NMOS transistor ⁇ N2>, and the first PMOS transistor ⁇ P1> and the second
- the offset voltage difference formed by the amplification difference of the PMOS transistor ⁇ P2> is transferred to the read bit line SABL and the complementary read bit line SABLB, and the potentials of the read bit line SABL and the complementary read bit line SABLB are set
- an equalization signal EQ is also provided to Equalize the potentials of the read bit line SABL and the complementary read bit line SABLB to a preset voltage, so as to reduce the error of subsequent signal amplification; in the second stage S2 (t3 ⁇ t4), provide the isolation signal ISO, the bit line BL and the read bit line SABL perform charge sharing, or the complementary bit line BLB and the complementary read bit line SABLB are electrically connected for charge sharing, so that the potential of the memory cell turned on by the word line WL is synchronized to the read bit line SABL or the complementary read bit line
- the bit line SABLB is output,
- the gates of the first PMOS transistor ⁇ P1> and the first NMOS transistor ⁇ N1> are directly connected to the bit line BL, and the gates of the second PMOS transistor ⁇ P2> and the second NMOS transistor ⁇ N2> are directly connected to the complementary bit line BLB.
- a PMOS transistor ⁇ P1> and the first NMOS transistor ⁇ N1> use the same gate connection to accurately amplify the potential of the bit line BL, and the second PMOS transistor ⁇ P2> and the second NMOS transistor ⁇ N2> pass the same gate connection relationship.
- the gate connection relationship is used to accurately realize the amplification of the potential BLB of the complementary bit line, thereby improving the readout accuracy of the sense amplifier.
- this embodiment does not introduce units that are not closely related to solving the technical problems raised by the present disclosure, but this does not mean that there are no other units in this embodiment unit.
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Abstract
一种读出电路版图,包括:第一PMOS版图,用于形成第一PMOS管<P1>,第一PMOS管的源极连接第一信号端,第一信号端用于接收第一电平信号;第一NMOS版图,用于形成第一NMOS管<N1>,第一NMOS管的源极连接第二信号端,第二信号端用于接收第二电平信号;第一PMOS管<P1>的栅极和第一NMOS管<N1>的栅极连接位线,第一PMOS管<P1>的漏极和第一NMOS管<N1>的漏极连接互补读出位线;第二PMOS版图,用于形成第二PMOS管<P2>,第二PMOS管<P2>的源极连接第一信号端;第二NMOS版图,用于形成第二NMOS管<N2>,第二NMOS管<N2>的源极连接第二信号端;第二PMOS管<P2>的栅极和第二NMOS管<N2>的栅极连接互补位线,第二PMOS管<P2>的漏极和第二NMOS管<N2>的漏极连接读出位线。
Description
交叉引用
本公开要求于2022年01月11日递交的名称为“读出电路版图”、申请号为202210028129.8的中国专利申请的优先权,其通过引用被全部并入本公开。
本公开涉及半导体电路设计领域,特别涉及一种读出电路版图。
动态随机存取存储存储器(Dynamic Random Access Memory,DRAM)通过单元电容中的电荷来写入数据;单元电容连接至位线和互补位线,在DRAM中,当执行读取操作或刷新操作时,读出放大器读出并放大位线和互补位线之间的电压差。
发明人发现,目前感测放大器的PMOS栅极由读出位线/互补读出位线控制,且存在一个端子连接读出位线/互补读出位线,即PMOS导通后,可能会受到自身影响而导致读出位线/互补读出位线的电位变化,从而影响存储器数据读出的准确性。
发明内容
本公开实施例提供了一种读出电路版图,包括:第一PMOS版图,用于形成第一PMOS管,第一PMOS管的源极连接第一信号端,第一信号端用于接收第一电平信号;第一NMOS版图,用于形成第一NMOS管,第一NMOS管的源极连接第二信号端,第二信号端用于接收第二电平信号;第一电平信号和第二电平信号中其中一个为高电平信号,另一个为低电平信号;第一PMOS管的栅极和第一NMOS管的栅极连接位线,第一PMOS管的漏极和第一NMOS管的漏极连接互补读出位线;第二PMOS版图,用于形成第二PMOS管,第二PMOS管的源极连接第一信号端;第二NMOS版图,用于形成第二NMOS管,第二NMOS管的源极连接第二信号端;第二PMOS管的栅极和第二NMOS管的栅极连接互补位线,第二PMOS管的漏极和第二NMOS管的漏极连接读出位线;在垂直于位线延伸方向上,第一PMOS版图和第二PMOS版图对称设置, 第一NMOS版图和第二NMOS版图对称设置。
另外,读出电路版图还包括:偏移消除版图,用于形成第一偏移消除MOS管和第二偏移消除MOS管;隔离版图,用于形成第一隔离MOS管和第二隔离MOS管;第一偏移消除MOS管和第一隔离MOS管设置在第一区域中,且第一偏移消除MOS管和第一隔离MOS管共用有源区;第二偏移消除MOS管和第二隔离MOS管设置在第二区域中,且第二偏移消除MOS管和第二隔离MOS管共用有源区;在垂直于位线延伸方向上,第一区域和第二区域对称设置。
另外,第一偏移消除MOS管的源极连接位线,漏极连接互补读出位线,栅极用于接收偏移消除信号;第二偏移消除MOS管的源极连接互补位线,漏极连接读出位线,栅极用于接收偏移消除信号。
另外,第一隔离MOS管的源极连接位线,漏极连接读出位线,栅极用于接收隔离信号;第二隔离MOS管的源极连接互补位线,漏极连接互补读出位线,栅极用于接收隔离信号。
另外,读出电路版图还包括:均衡充电版图,用于形成均衡充电模块,其中,均衡充电版图部分设置在第一区域中,部分设置在第二区域中;或,第一PMOS版图和第二PMOS版图基于均衡充电版图对称设置,第一NMOS版图和第二NMOS版图基于均衡充电版图对称设置,第一区域和第二区域基于均衡充电版图对称设置。
另外,均衡充电模块,一端连接读出位线,另一端连接互补读出位线,用于将读出位线和互补读出位线均衡至预设电压。
另外,均衡充电模块,包括:第一预充电MOS管,源极连接互补读出位线;第二预充电MOS管,源极连接读出位线;第一预充电MOS管的漏极和第二预充电MOS管的漏极用于接收预设电压,第一预充电MOS管的栅极和第二预充电MOS管的栅极用于接收预充电信号;均衡MOS管,源极连接互补读出位线,漏极连接读出位线,栅极用于接收均衡信号。
另外,均衡充电模块,包括:第一预充电MOS管,源极连接互补读出位线;第二预充电MOS管,源极连接读出位线;第一预充电MOS管的漏极和第二预充电MOS管的漏极用于接收预设电压;均衡MOS管,源极连接互补读出位线,漏极连接读出位线;第一预充电MOS管的栅极、第二预充电MOS管的 栅极和均衡MOS管的栅极用于接收均衡信号。
另外,均衡充电版图用于形成第一预充电MOS管、第二预充电MOS管和均衡MOS管,其中,第一预充电MOS管的栅极、第二预充电MOS管的栅极和均衡MOS管的栅极延伸方向相同;第一预充电MOS管、第二预充电MOS管和均衡MOS管共用有源区。
另外,均衡充电模块,包括:预充电MOS管,源极连接互补读出位线或连接读出位线,漏极用于接收预设电压,栅极用于接收预充电信号;均衡MOS管,源极连接互补读出位线,漏极连接读出位线,栅极用于接收均衡信号。
另外,均衡充电模块,包括:预充电MOS管,源极连接互补读出位线或连接读出位线,漏极用于接收预设电压;均衡MOS管,源极连接互补读出位线,漏极连接读出位线;预充电MOS管的栅极和均衡MOS管的栅极用于接收均衡信号。
另外,均衡充电版图用于形成预充电MOS和均衡MOS管,其中,预充电MOS管的栅极和均衡MOS管的栅极延伸方向相同;预充电MOS管和均衡MOS管共用有源区。
另外,第一PMOS版图的栅极、第二PMOS版图的栅极、第一NMOS版图的栅极和第二NMOS版图的栅极延伸方向相同,且第一PMOS版图的栅极的延伸方向与均衡MOS版图的栅极延伸方向相交。
另外,第一NMOS版图的栅极和第二NMOS版图的栅极延伸方向相同,第一PMOS版图的栅极、第二PMOS版图的栅极和均衡充电版图中栅极延伸方向相同,且第一NMOS版图的栅极的延伸方向与均衡MOS充电版图中栅极延伸方向相交。
另外,均衡充电版图中,用于接收预充电信号的有源区相互连通。
一个或多个实施例通过与之对应的附图中的图片进行示例性说明,这些示例性说明并不构成对实施例的限定,除非有特别申明,附图中的图不构成比例限制;为了更清楚地说明本公开实施例或传统技术中的技术方案,下面将对实施例中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅 仅是本公开的一些实施例,对于本领缺普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的感测放大电路的电路结构示意图;
图2为本公开实施例提供的第一种均衡充电模块的电路结构示意图;
图3为本公开实施例提供的第二种均衡充电模块的电路结构示意图;
图4为本公开实施例提供的第三种均衡充电模块的电路结构示意图;
图5为本公开实施例提供的第四种均衡充电模块的电路结构示意图;
图6为本公开实施例提供的感测放大电路的工作时序示意图;
图7为本公开实施例提供的第一种对应于具有图2或图3所示均衡充电模块的电路的版图示意图;
图8为本公开实施例提供的第二种对应于具有图2或图3所示均衡充电模块的电路的版图示意图;
图9为本公开实施例提供的第三种对应于具有图2或图3所示均衡充电模块的电路的版图示意图;
图10为本公开实施例提供的第四种对应于具有图2或图3所示均衡充电模块的电路的版图示意图;
图11为本公开实施例提供的第五种对应于具有图2或图3所示均衡充电模块的电路的版图示意图;
图12为本公开实施例提供的图7~图11中均衡充电模块用于接收预充电信号的有源区相连的版图示意图;
图13为本公开实施例提供的第一种对应于具有图4或图5所示均衡充电模块的电路的版图示意图;
图14为本公开实施例提供的第一种对应于具有图4或图5所示均衡充电模块的电路的版图示意图;
图15为本公开实施例提供的第一种对应于具有图4或图5所示均衡充电模块的电路的版图示意图;
图16为本公开实施例提供的另一种PMOS版图的结构示意图。
目前感测放大器的PMOS栅极由读出位线/互补读出位线控制,且存在一个端子连接读出位线/互补读出位线,即感测放大器中的PMOS导通后,可能会受到自身影响而导致读出位线/互补读出位线的电位变化,从而影响存储器数据读出的准确性。
本公开实施例提供了一种读出电路版图,以提高感测放大器的读出准确性。
本领域的普通技术人员可以理解,在本公开各实施例中,为了使读者更好地理解本公开而提出了许多技术细节。但是,即使没有这些技术细节和基于以下各实施例的种种变化和修改,也可以实现本公开所要求保护的技术方案。以下各个实施例的划分是为了描述方便,不应对本公开的具体实现方式构成任何限定,各个实施例在不矛盾的前提下可以相互结合,相互引用。
图1为本实施例提供的感测放大电路的电路结构示意图,图2为本实施例提供的第一种均衡充电模块的电路结构示意图,图3为本实施例提供的第二种均衡充电模块的电路结构示意图,图4为本实施例提供的第三种均衡充电模块的电路结构示意图,图5为本实施例提供的第四种均衡充电模块的电路结构示意图,图6为本实施例提供的感测放大电路的工作时序示意图,图7为本实施例提供的第一种对应于具有图2或图3所示均衡充电模块的电路的版图示意图,图8为本实施例提供的第二种对应于具有图2或图3所示均衡充电模块的电路的版图示意图,图9为本实施例提供的第三种对应于具有图2或图3所示均衡充电模块的电路的版图示意图,图10为本实施例提供的第四种对应于具有图2或图3所示均衡充电模块的电路的版图示意图,图11为本实施例提供的第五种对应于具有图2或图3所示均衡充电模块的电路的版图示意图,图12为本实施例提供的图7~图11中均衡充电模块用于接收预充电信号的有源区相连的版图示意图,图13为本实施例提供的第一种对应于具有图4或图5所示均衡充电模块的电路的版图示意图,图14为本实施例提供的第一种对应于具有图4或图5所示均衡充电模块的电路的版图示意图,图15为本实施例提供的第一种对应于具有图4或图5所示均衡充电模块的电路的版图示意图,图16为本实施例提 供的另一种PMOS版图的结构示意图,以下结合附图对本实施例提供的读出电路版图作进一步详细说明,具体如下:
参考图1,读出电路版图,包括:
第一PMOS版图,用于形成第一PMOS管<P1>,第一PMOS管<P1>的源极连接第一信号端(Positive Cell Storing Signal,PCS),具体地,第一信号端PCS用于接收第一电平信号。
第一NMOS版图,用于形成第一NMOS管<N1>,第一NMOS管<N1>的源极连接第二信号端(Negative Cell Storing Signal,NCS),具体地,第二信号端NCS用于接收第二电平信号。
第一电平信号和第二电平信号中其中一个为高电平信号,另一个为低电平信号。
其中,第一PMOS管<P1>的栅极和第一NMOS管<N1>的栅极连接位线BL,第一PMOS管<P1>的漏极和第一NMOS管<N1>的漏极连接互补读出位线SABLB。
第二PMOS版图,用于形成第二PMOS管<P2>,第二PMOS管<P2>的源极连接第一信号端PCS。
第二NMOS版图,用于形成第二NMOS管<N2>,第二NMOS管<N2>的源极连接第二信号端NCS。
第二PMOS管<P2>的栅极和第二NMOS管<N2>的栅极连接互补位线BLB,第二PMOS管<P2>的漏极和第二NMOS管<N2>的漏极连接读出位线SABL。
在垂直于位线延伸方向上,第一PMOS版图和第二PMOS版图对称设置,第一NMOS版图和第二NMOS版图对称设置。
第一PMOS管和第一NMOS管的栅极直接连接位线,第二PMOS管和第二NMOS管的栅极直接连接互补位线,第一PMOS管和第一NMOS管通过相同的栅极连接关系,以准确实现位线电位的放大,第二PMOS管和第二NMOS管通过相同的栅极连接关系,以准确实现互补位线电位的放大,从而提高感测放大器的读出准确性。
需要说明的是,下述以第一电平信号为对应逻辑“1”的高电平,第二电平信号为对应逻辑“0”的低电平为例对本公开提供的感测放大电路进行具体说明,并不构成对本实施例的限定,在一些实施例中,第一电平信号可以为对应逻辑“0”的低电平,第二电平信号可以为对应逻辑“1”的高电平,此时感测放大器的作用即对位线数据进行反相放大,后续在输出过程中对数据进行反相即可输出原始数据。
在一些实施例中,读出电路版图,还包括:偏移消除版图和隔离版图,其中,偏移消除版图用于形成第一偏移消除MOS管<21>和第二偏移消除MOS管<22>,隔离版图用于形成第一隔离MOS管<11>和第二隔离MOS管<12>;第一偏移消除MOS管<21>和第一隔离MOS管<11>设置在第一区域中,且第一偏移消除MOS管<21>和第一隔离MOS管<11>共用有源区,第二偏移消除MOS管<22>和第二隔离MOS管<12>设置在第二区域中,且第二偏移消除MOS管<22>和第二隔离MOS管<12>共用有源区,在垂直于位线延伸方向上,第一区域和第二区域对称设置。
具体地,参考图1,偏移消除模块201包括第一偏移消除MOS管<21>和第二偏移消除MOS管<22>,其中,第一偏移消除MOS管<21>的源极连接位线BL,漏极连接互补读出位线SABLB,栅极用于接收偏移消除信号OC,第二偏移消除MOS管<22>源极连接互补位线BLB,漏极连接读出位线SABL,栅极用于接收偏移消除信号OC。
具体地,参考图1,隔离模块301包括第一隔离MOS管<11>和第二隔离MOS管<12>,其中,第一隔离MOS管<11>源极连接位线BL,漏极连接读出位线SABL,栅极用于接收隔离信号ISO,第二隔离MOS管<12>源极连接互补位线BLB,漏极连接互补读出位线SABLB,栅极用于接收隔离信号ISO。
需要说明的是,上述各个晶体管定义的具体“源极”和“漏极”的连接方式,并不构成对本实施例的限定,在其他实施例中,可以采用“漏极”替换“源极”,“源极”替换“漏极”的连接方式。
本公开提供的读出电路版图中,第一PMOS管<P1>和第一NMOS管<N1>的栅极直接连接位线BL,经过偏移消除后的偏置电压首先会出现在互补读出位线SABLB上,即偏置电压并不会影响第一PMOS管<P1>和第一NMOS管<N1> 偏移消除的稳定性,当偏置电压被同步至位线BL时,此时已完成偏移消除过程,即通过将第一PMOS管<P1>和第一NMOS管<N1>的栅极直接通过位线BL控制,还用于提高感测放大电路进行偏移消除的稳定性;同理,第二PMOS管<P2>和第二NMOS管<N2>的栅极直接连接互补位线BLB,经过偏移消除后的偏置电压首先会出现在读出位线SABL上,即偏置电压并不会影响第二PMOS管<P2>和第二NMOS管<N2>偏移消除的稳定性,当偏置电压被同步至互补位线BLB时,此时已完成偏移消除过程,即通过将第二PMOS管<P2>和第二NMOS管<N2>的栅极直接通过互补位线BLB控制,还用于提高感测放大电路进行偏移消除的稳定性。
在一些实施例中,读出电路版图,还包括:均衡充电版图,其中,均衡充电版图用于形成均衡充电模块,均衡充电版图部分设置在第一区域中,部分设置在第二区域中,或第一PMOS版图和第二PMOS版图基于均衡充电版图对称设置,第一NMOS版图和第二NMOS版图基于均衡充电版图对称设置,第一区域和第二区域基于均衡充电版图对称设置。
具体地,参考图1,均衡充电模块101,一端连接读出位线SABL,另一端连接互补读出位线SABLB,用于将读出位线SABL和互补读出位线SABLB均衡至预设电压VBLP。
在一个例子中,参考图2,均衡充电模块101包括第一预充电MOS管、第二预充电MOS管和均衡MOS管,其中,第一预充电MOS管的源极连接互补读出位线SABLB,第二预充电MOS管的源极连接读出位线SABL,第一预充电MOS管的漏极和第二预充电MOS管的漏极用于接收预设电压VBLP,第一预充电MOS管的栅极和第二预充电MOS管的栅极用于接收预充电信号(Pre-charge Signal,PRE),均衡MOS管的源极连接互补读出位线SABLB,漏极连接读出位线SABL,栅极用于接收均衡信号(Equalizing Signal,EQ)。
在一个例子中,参考图3,均衡充电模块101包括第一预充电MOS管、第二预充电MOS管和均衡MOS管,其中,第一预充电MOS管的源极连接互补读出位线SABLB,第二预充电MOS管的源极连接读出位线SABL,第一预充电MOS管的漏极和第二预充电MOS管的漏极用于接收预设电压VBLP,均衡MOS管的源极连接互补读出位线SABLB,漏极连接读出位线SABL,第一预充电MOS管的栅极、第二预充电MOS管的栅极和均衡MOS管的栅极用于 接收均衡信号EQ。
参考图7~图11,在一些实施例中,均衡充电版图用于形成第一预充电MOS管。第二预充电MOS管和均衡MOS管,其中,第一预充电MOS管的栅极、第二预充电MOS的栅极和均衡MOS管的栅极延伸方向相同,第一预充电MOS管、第二预充电MOS管和均衡MOS管共用有源区。
对于具有图2和图3所示的均衡充电模块的感测放大电路,其版图如下:
在一个例子中,具体参考图7,均衡充电版图设置在中间位置,第一PMOS版图和第二PMOS版图基于均衡充电版图对称设置,第一NMOS版图和第二NMOS版图基于均衡充电版图对称设置,第一区域和第二区域基于均衡充电版图对称设置,且第一区域设置在第一PMOS版图和第一NMOS版图远离均衡充电版图的一侧,第二区域设置在第二PMOS版图和第二NMOS版图远离均衡充电版图的一侧;需要说明的是,在该示例中,第一PMOS版图和第一NMOS版图的位置可以互换,相应地,第二PMOS版图和第二NMOS版图的位置可以互换。
在一个例子中,具体参考图8,均衡充电版图设置在中间位置,第一PMOS版图和第二PMOS版图基于均衡充电版图对称设置,第一NMOS版图和第二NMOS版图基于均衡充电版图对称设置,第一区域和第二区域基于均衡充电版图对称设置,且第一区域设置在第一PMOS版图和第一NMOS版图之间,第二区域设置在第二PMOS版图和第二NMOS版图之间;需要说明的是,在该示例中,第一PMOS版图和第一NMOS版图的位置可以互换,相应地,第二PMOS版图和第二NMOS版图的位置可以互换。
在一个例子中,具体参考图9,均衡充电版图设置在中间位置,第一PMOS版图和第二PMOS版图基于均衡充电版图对称设置,第一NMOS版图和第二NMOS版图基于均衡充电版图对称设置,第一区域和第二区域基于均衡充电版图对称设置,且第一区域设置在第一PMOS版图和第一NMOS版图靠近均衡充电版图的一侧,第二区域设置在第二PMOS版图和第二NMOS版图靠近均衡充电版图的一侧;需要说明的是,在该示例中,第一PMOS版图和第一NMOS版图的位置可以互换,相应地,第二PMOS版图和第二NMOS版图的位置可以互换。
在一个例子中,参考图10,第一PMOS版图和第二PMOS版图对称设置,第一NMOS版图和第二NMOS版图对称设置,第一区域和第二区域对称设置,均衡充电版图设置在第一区域中;需要说明的是,在该示例中,第一PMOS版图和第一NMOS版图的位置可以互换,均衡充电版图也可以设置在第二区域中;另外,图10所示结构也适用于类似于图7→图8和图7→图9的变换。
在一个例子中,参考图11,均衡充电版图中第一预充电MOS管设置在第一区域中,第二预充电MOS管设置在第二区域中,均衡MOS管设置在中间位置,第一PMOS版图和第二PMOS版图基于均衡MOS管对称设置,第一NMOS版图和第二NMOS版图基于均衡MOS管对称设置,第一区域和第二区域基于均衡MOS管对称设置,且第一区域设置在第一PMOS版图和第一NMOS版图靠近均衡充电版图的一侧,第二区域设置在第二PMOS版图和第二NMOS版图靠近均衡充电版图的一侧;需要说明的是,在该示例中,第一PMOS版图和第一NMOS版图的位置可以互换,相应地,第二PMOS版图和第二NMOS版图的位置可以互换;另外,图11所示结构也适用于类似于图7→图8和图7→图9的变换。
参考图7~图11并结合图12(图12左上图对应于图7~图9所示版图,图12左下图对应于图10所示版图,图12右图对应于图11所示版图),在一些实施例中,用于接收预充电信号的有源区相互连通,以简化后续接入预充电信号时的版图连线,并增大用于接收预充电信号的有源区的驱动能力。
在一个例子中,参考图4,均衡充电模块101包括预充电MOS管和均衡MOS管,其中,预充电MOS管的源极连接互补读出位线SABLB或连接读出位线SABL,漏极用于接收预设电压,栅极用于接收预充电信号PRE,均衡MOS管的源极连接互补读出位线SABLB,漏极连接读出位线SABL,栅极用于接收均衡信号EQ。
在一个例子中,参考图5,均衡充电模块101包括预充电MOS管和均衡MOS管,预充电MOS管的源极连接互补读出位线SABLB或连接读出位线SABL,漏极用于接收预设电压,均衡MOS管的源极连接互补读出位线SABLB,漏极连接读出位线SABL,预充电MOS管的栅极和均衡MOS管的栅极用于接收均衡信号EQ。
参考图13~图15,在一些实施例中,均衡充电版图用于形成预充电MOS管和均衡MOS管,其中,预充电MOS管的栅极和均衡MOS管的栅极延伸方向相同,预充电MOS管和均衡MOS管共用有源区。
对于具有图4和图5所示的均衡充电模块的感测放大电路,其版图如下:
在一个例子中,具体参考图13,均衡充电版图设置在中间位置,第一PMOS版图和第二PMOS版图基于均衡充电版图对称设置,第一NMOS版图和第二NMOS版图基于均衡充电版图对称设置,第一区域和第二区域基于均衡充电版图对称设置,且第一区域设置在第一PMOS版图和第一NMOS版图远离均衡充电版图的一侧,第二区域设置在第二PMOS版图和第二NMOS版图远离均衡充电版图的一侧;需要说明的是,在该示例中,第一PMOS版图和第一NMOS版图的位置可以互换,相应地,第二PMOS版图和第二NMOS版图的位置可以互换;另外,图13所示结构也适用于类似于图7→图8和图7→图9的变换。
在一个例子中,具体参考图14,第一PMOS版图和第二PMOS版图对称设置,第一NMOS版图和第二NMOS版图对称设置,第一区域和第二区域对称设置,均衡充电版图设置在第一区域中;需要说明的是,在该示例中,第一PMOS版图和第一NMOS版图的位置可以互换,均衡充电版图也可以设置在第二区域中;另外,图10所示结构也适用于类似于图7→图8和图7→图9的变换。
在一个例子中,具体参考图15,均衡充电版图中预充电MOS管设置在第一区域中,均衡MOS管设置在第二区域中,第一PMOS版图和第二PMOS版图对称设置,第一NMOS版图和第二NMOS版图对称设置,第一区域和第二区域对称设置,需要说明的是,在该示例中,第一PMOS版图和第一NMOS版图的位置可以互换,均衡充电版图也可以设置在第二区域中;另外,图10所示结构也适用于类似于图7→图8和图7→图9的变换。
需要说明的是,在图13~图15的示意图中,用于接收预充电信号的有源区相互连通,以简化后续接入预充电信号时的版图连线,并增大用于接收预充电信号的有源区的驱动能力。
在图7~图15所示电路中,第一PMOS版图的栅极、第二PMOS版图的栅极、第一NMOS版图的栅极和第二NMOS版图的栅极延伸方向相同,且第一PMOS版图的栅极的延伸方向与均衡MOS版图的栅极延伸方向相交。
在一些实施例中,参考图16且结合图7~图15,第一NMOS版图的栅极和第二NMOS版图的栅极延伸方向相同,第一PMOS版图管的栅极、第二PMOS版图的栅极和均衡充电版图中栅极延伸方向相同,且第一NMOS版图的管栅极的延伸方向与均衡MOS充电版图中栅极延伸方向相交。
在本实施例中,预设电压VBLP=1/2VDD,其中,VDD为芯片内部电源电压;在其他实施例中,预设电压VBLP可以根据具体应用场景进行设置。
由于构成读出放大器的半导体器件可能由于工艺变化、温度等因素的影响从而具有不同的器件特性(例如,阈值电压)。不同的器件特性会导致读出放大器中的产生偏移噪声,而偏移噪声会降低读出放大器的有效读出裕度,并且会降低DRAM的性能。
对于本公开提供的感测放大电路,其放大过程包括4个阶段,参考图6,在第一阶段S1(t0~t1)中,提供均衡信号EQ、预充电信号PRE,隔离信号ISO,偏移消除信号OC,以关联感测放大电路中的所有线路,并将所有线路预充电至预设电压;在第二阶段S2(t1~t2)中,继续提供偏移消除信号OC,并向第一信号端PCS提供第一电压,向第二信号端NCS提供第二电压,将第一NMOS管<N1>和第二NMOS管<N2>的放大差异,以及第一PMOS管<P1>和第二PMOS管<P2>的放大差异形成的偏移电压差转移至读出位线SABL和互补读出位线SABLB上,读出位线SABL和互补读出位线SABLB的电位被设置为具有偏移电压的差,同时由于具有偏移消除信号OC,第一偏移消除MOS管<21>和第二偏移消除MOS管<22>导通,读出位线SABL与互补位线BLB连接,互补读出位线SABLB与位线BL连接,位线BL和互补位线BLB的电位同样被设置为具有偏移电压的差。因此,感测放大电路的偏移噪声被消除;在第二阶段S2(t2~t3)中,将第一信号端PCS和第二信号端NCS所接收的信号恢复至预设电压;需要说明的是,在一些实施例中,在第二阶段S2(t2~t3)中,将第一信号端PCS和第二信号端NCS所接收的信号恢复至预设电压后,还提供均衡信号EQ,以将读出位线SABL和互补读出位线SABLB的电位均衡至预设电压,以减小后续进行信号放大的误差;在第二阶段S2(t3~t4)中,提供隔离信号ISO,位线BL和读出位线SABL进行电荷分享,或互补位线BLB和互补读出位线SABLB电连接进行电荷分享,以通过字线WL打开的存储单元的电位同步至读出位线SABL或互补读出位线SABLB,且同步后的读出位线SABL或互补读出位线 SABLB的电位具有偏移电压的差将偏移电位交叉同步(偏移消除过程中,互补读出位线SABLB上的偏移电压同步至位线BL上,在这一阶段会同步至读出位线SABL)后,以补偿第一NMOS管<N1>和第二NMOS管<N2>的放大差异,并补偿第一PMOS管<P1>和第二PMOS管<P2>的放大差异;在S3阶段(t4~t5),即信号读出阶段,感测放大电路根据读出位线SABL和互补读出位线SABLB的电位感测放大后,读出存储数据,并对存储单元的电位进行数据恢复;在S4阶段(t5~t6),即信号复位阶段,通过预充电,将读出电路中各线路的电位预充至预设电压,准备下一次读出数据。
第一PMOS管<P1>和第一NMOS管<N1>的栅极直接连接位线BL,第二PMOS管<P2>和第二NMOS管<N2>的栅极直接连接互补位线BLB,第一PMOS管<P1>和第一NMOS管<N1>通过相同的栅极连接关系,以准确实现位线BL电位的放大,第二PMOS管<P2>和第二NMOS管<N2>通过相同的栅极连接关系,以准确实现互补位线电位BLB的放大,从而提高感测放大器的读出准确性。
需要说明的是,为了突出本公开的创新部分,本实施例中并没有将与解决本公开所提出的技术问题关系不太密切的单元引入,但这并不表明本实施例中不存在其它的单元。
本领域的普通技术人员可以理解,上述各实施例是实现本公开的具体实施例,而在实际应用中,可以在形式上和细节上对其作各种改变,而不偏离本公开的精神和范围。
Claims (15)
- 一种读出电路版图,包括:第一PMOS版图,用于形成第一PMOS管,所述第一PMOS管的源极连接第一信号端,所述第一信号端用于接收第一电平信号;第一NMOS版图,用于形成第一NMOS管,所述第一NMOS管的源极连接第二信号端,所述第二信号端用于接收第二电平信号;所述第一电平信号和所述第二电平信号中其中一个为高电平信号,另一个为低电平信号;所述第一PMOS管的栅极和所述第一NMOS管的栅极连接位线,所述第一PMOS管的漏极和所述第一NMOS管的漏极连接互补读出位线;第二PMOS版图,用于形成第二PMOS管,所述第二PMOS管的源极连接所述第一信号端;第二NMOS版图,用于形成第二NMOS管,所述第二NMOS管的源极连接所述第二信号端;所述第二PMOS管的栅极和所述第二NMOS管的栅极连接互补位线,所述第二PMOS管的漏极和所述第二NMOS管的漏极连接读出位线;在垂直于位线延伸方向上,所述第一PMOS版图和所述第二PMOS版图对称设置,所述第一NMOS版图和所述第二NMOS版图对称设置。
- 根据权利要求1所述的读出电路版图,其中,还包括:偏移消除版图,用于形成第一偏移消除MOS管和第二偏移消除MOS管;隔离版图,用于形成第一隔离MOS管和第二隔离MOS管;所述第一偏移消除MOS管和所述第一隔离MOS管设置在第一区域中,且所述第一偏移消除MOS管和所述第一隔离MOS管共用有源区;所述第二偏移消除MOS管和所述第二隔离MOS管设置在第二区域中,且所述第二偏移消除MOS管和所述第二隔离MOS管共用有源区;在垂直于位线延伸方向上,所述第一区域和所述第二区域对称设置。
- 根据权利要求2所述的读出电路版图,其中,所述第一偏移消除MOS管的源极连接所述位线,漏极连接所述互补读出位线,栅极用于接收所述偏移消除信号;所述第二偏移消除MOS管的源极连接所述互补位线,漏极连接所述读出位线,栅极用于接收所述偏移消除信号。
- 根据权利要求2所述的读出电路版图,其中,所述第一隔离MOS管的源极连接所述位线,漏极连接所述读出位线,栅极用于接收所述隔离信号;所述第二隔离MOS管的源极连接所述互补位线,漏极连接所述互补读出位线,栅极用于接收所述隔离信号。
- 根据权利要求1所述的读出电路版图,其中,还包括:均衡充电版图,用于形成均衡充电模块,其中,所述均衡充电版图部分设置在第一区域中,部分设置在第二区域中;或,所述第一PMOS版图和所述第二PMOS版图基于所述均衡充电版图对称设置,所述第一NMOS版图和所述第二NMOS版图基于所述均衡充电版图对称设置,所述第一区域和所述第二区域基于所述均衡充电版图对称设置。
- 根据权利要求5所述的读出电路版图,其中,所述均衡充电模块,一端连接所述读出位线,另一端连接所述互补读出位线,用于将所述读出位线和所述互补读出位线均衡至预设电压。
- 根据权利要求6所述的读出电路版图,其中,所述均衡充电模块,包括:第一预充电MOS管,源极连接所述互补读出位线;第二预充电MOS管,源极连接所述读出位线;所述第一预充电MOS管的漏极和所述第二预充电MOS管的漏极用于接收所述预设电压,所述第一预充电MOS管的栅极和所述第二预充电MOS管的栅极用于接收预充电信号;均衡MOS管,源极连接所述互补读出位线,漏极连接所述读出位线,栅极用于接收均衡信号。
- 根据权利要求6所述的读出电路版图,其中,所述均衡充电模块,包括:第一预充电MOS管,源极连接所述互补读出位线;第二预充电MOS管,源极连接所述读出位线;所述第一预充电MOS管的漏极和所述第二预充电MOS管的漏极用于接收所述预设电压;均衡MOS管,源极连接所述互补读出位线,漏极连接所述读出位线;所述第一预充电MOS管的栅极、所述第二预充电MOS管的栅极和所述均衡MOS管的栅极用于接收均衡信号。
- 根据权利要求7或8所述的读出电路版图,其中,所述均衡充电版图用于形成第一预充电MOS管、第二预充电MOS管和均衡MOS管,其中,所述第一预充电MOS管的栅极、所述第二预充电MOS管的栅极和所述均衡MOS管的栅极延伸方向相同;所述第一预充电MOS管、所述第二预充电MOS管和所述均衡MOS管共用有源区。
- 根据权利要求6所述的读出电路版图,其中,所述均衡充电模块,包括:预充电MOS管,源极连接所述互补读出位线或连接所述读出位线,漏极用于接收所述预设电压,栅极用于接收预充电信号;均衡MOS管,源极连接所述互补读出位线,漏极连接所述读出位线,栅极用于接收均衡信号。
- 根据权利要求6所述的读出电路版图,其中,所述均衡充电模块,包括:预充电MOS管,源极连接所述互补读出位线或连接所述读出位线,漏极用于接收所述预设电压;均衡MOS管,源极连接所述互补读出位线,漏极连接所述读出位线;所述预充电MOS管的栅极和所述均衡MOS管的栅极用于接收均衡信号。
- 根据权利要求10或11所述的读出电路版图,其中,所述均衡充电版图用于形成预充电MOS和均衡MOS管,其中,所述预充电MOS管的栅极和所述均衡MOS管的栅极延伸方向相同;所述预充电MOS管和所述均衡MOS管共用有源区。
- 根据权利要求7、8、10或11所述的读出电路版图,其中,所述第一PMOS版图的栅极、所述第二PMOS版图的栅极、所述第一NMOS版图的栅极和所述第二NMOS版图的栅极延伸方向相同,且第一PMOS版图的栅极的延伸方向与所述均衡MOS版图的栅极延伸方向相交。
- 根据权利要求7、8、10或11所述的读出电路版图,其中,所述第一NMOS版图的栅极和所述第二NMOS版图的栅极延伸方向相同,所述第一PMOS版图的栅极、所述第二PMOS版图的栅极和所述均衡充电版图中栅极延伸方向相同,且第一NMOS版图的栅极的延伸方向与所述均衡MOS充电版图中栅极延伸方向相交。
- 根据权利要求7、8、10或11所述的读出电路版图,其中,所述均衡充电版图中,用于接收预充电信号的有源区相互连通。
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CN113193870A (zh) * | 2021-04-21 | 2021-07-30 | 江苏信息职业技术学院 | 一种低功耗、低版图面积的sar adc |
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CN1825477A (zh) * | 2006-02-24 | 2006-08-30 | 北京芯技佳易微电子科技有限公司 | 互补动态存储器单元及其实现读、写、刷新操作的方法 |
US20080080282A1 (en) * | 2006-09-29 | 2008-04-03 | Samsung Electronics Co., Ltd. | Layout structures and methods of fabricating layout structures |
CN111081296A (zh) * | 2016-12-28 | 2020-04-28 | 三星电子株式会社 | 具有偏移消除的读出放大器和存储器装置 |
CN110620577A (zh) * | 2019-10-12 | 2019-12-27 | 上海华力微电子有限公司 | 基于fdsoi结构的电平转换单元电路及版图设计方法 |
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