WO2023040158A1 - 读出电路架构 - Google Patents

读出电路架构 Download PDF

Info

Publication number
WO2023040158A1
WO2023040158A1 PCT/CN2022/072740 CN2022072740W WO2023040158A1 WO 2023040158 A1 WO2023040158 A1 WO 2023040158A1 CN 2022072740 W CN2022072740 W CN 2022072740W WO 2023040158 A1 WO2023040158 A1 WO 2023040158A1
Authority
WO
WIPO (PCT)
Prior art keywords
layout
gate
active layer
bit line
nmos
Prior art date
Application number
PCT/CN2022/072740
Other languages
English (en)
French (fr)
Inventor
杨桂芬
池性洙
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US18/151,466 priority Critical patent/US20230162782A1/en
Publication of WO2023040158A1 publication Critical patent/WO2023040158A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Definitions

  • the present application relates to the field of semiconductor circuit layout, in particular to a readout circuit architecture.
  • Dynamic Random Access Memory writes data through the charge in the cell capacitor; the cell capacitor is connected to the bit line and the complementary bit line.
  • DRAM Dynamic Random Access Memory
  • the sense amplifier senses and amplifies the voltage difference between the bit line and the complementary bit line.
  • Semiconductor devices constituting a sense amplifier may have different device characteristics (eg, threshold voltage) due to process variations, temperature, and the like. Different device characteristics lead to offset noise in the sense amplifier, which reduces the effective read margin of the sense amplifier and degrades the performance of the DRAM.
  • device characteristics eg, threshold voltage
  • Different device characteristics lead to offset noise in the sense amplifier, which reduces the effective read margin of the sense amplifier and degrades the performance of the DRAM.
  • the embodiment of the present application provides a readout circuit architecture to eliminate the offset in the readout circuit without introducing more offset elimination metal oxide semiconductor field effect transistors (Metal Oxide Semiconductor Field Effect Transistor, MOSFET) Noise is conducive to the improvement of DRAM integration.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • An embodiment of the present application provides a readout circuit architecture, including: a first N-type metal-oxide-semiconductor (N-Metal-Oxide-Semiconductor, NMOS) layout, including first discretely arranged in a first direction The N-type active layer, and the first gate layer arranged discretely on the first N-type active layer; the second NMOS layout, including the second N-type active layer arranged discretely in the first direction, And the second gate layer arranged discretely on the second N-type active layer; the first P-type metal-oxide-semiconductor (P-Metal-Oxide-Semiconductor, PMOS) layout, including in the first direction a discretely arranged first P-type active layer, and a discretely arranged third gate layer disposed on the first P-type active layer; a second PMOS layout, including a discretely arranged second gate layer in the first direction The P-type active layer, and the fourth gate layer arranged discret
  • the gate of the first PMOS transistor is connected to the complementary readout bit line, and the drain is connected to the readout bit line.
  • the first signal terminal is electrically connected to the readout bit line, and One signal end is used to receive the high level corresponding to the logic "1", that is, the first signal end receives the internal power supply voltage of the chip; at this time, the first PMOS transistor that is turned on affects the read based on the level and threshold voltage of the complementary read bit line.
  • the level of the bit line; the gate of the second PMOS transistor is connected to the read bit line, and the drain is connected to the complementary read bit line.
  • the first signal terminal is electrically connected to the read bit line, and the second One signal terminal is used to receive the high level corresponding to logic "1", that is, the internal power supply voltage of the chip at the first signal terminal; at this time, the second PMOS transistor that is turned on affects the complementary readout based on the level and threshold voltage of the readout bit line
  • the level of the bit line, the threshold voltage difference between the first PMOS transistor and the second PMOS transistor will cause the level difference between the read bit line and the complementary read bit line, that is, through the voltage of the read bit line and the complementary read bit line Flat, reflecting the offset noise of the first PMOS transistor and the second PMOS transistor.
  • the gate of the first NMOS transistor is connected to the complementary read bit line, and the drain is connected to the bit line; the gate of the second NMOS transistor is connected to the read bit line, and the drain is complementary to the bit line; since the first isolated MOS transistor ⁇ 11>
  • the connection method with the second isolation MOS transistor ⁇ 12> when the offset elimination is in progress, the first isolation MOS transistor ⁇ 11> and the second isolation MOS transistor ⁇ 12> are not conducted, and the second signal terminal is also used to receive Corresponding to the high level of logic "1", that is, the first signal terminal receives the internal power supply voltage of the chip; so that the conduction difference between the first NMOS transistor and the second NMOS transistor does not affect the readout bit line and the complementary readout bit line, but It is to directly adjust the bit line voltage and the complementary bit line voltage.
  • the conduction degree of the first NMOS transistor is based on the voltage of the complementary read bit line and the threshold voltage of the first NMOS transistor are determined
  • the conduction degree of the second NMOS transistor is determined based on the level of the read bit line and the threshold voltage of the second NMOS transistor; at this time, the first NMOS transistor and the second NMOS transistor are respectively based on complementary
  • the adjusted bit line voltage and the complementary bit line reflect the offset noise of the first PMOS transistor and the second PMOS transistor, and simultaneously reflect the first NMOS transistor and the second PMOS transistor.
  • the layout of the readout circuit provided by the embodiment of the present application can avoid the layout shift and eliminate the MOS transistor, thereby reducing the layout area of the readout circuit.
  • FIG. 1 is a schematic diagram of a circuit structure of a readout circuit provided in an embodiment of the present application
  • 2 to 15 are schematic diagrams of the layout structure of the readout circuit provided by the embodiment of the present application.
  • Semiconductor devices constituting a sense amplifier may have different device characteristics (eg, threshold voltage) due to process variations, temperature, and the like. Different device characteristics lead to offset noise in the sense amplifier, which reduces the effective read margin of the sense amplifier and degrades the performance of the DRAM.
  • device characteristics eg, threshold voltage
  • Different device characteristics lead to offset noise in the sense amplifier, which reduces the effective read margin of the sense amplifier and degrades the performance of the DRAM.
  • An embodiment of the present application provides a readout circuit architecture, including: a first NMOS layout, including a first N-type active layer discretely arranged in a first direction, and a discrete array disposed on the first N-type active layer.
  • the first gate layer arranged;
  • the second NMOS layout including a second N-type active layer discretely arranged in the first direction, and a second gate discretely arranged on the second N-type active layer pole layer;
  • a first PMOS layout including a first P-type active layer discretely arranged in a first direction, and a third gate layer discretely arranged on the first P-type active layer;
  • a second PMOS The layout includes a second P-type active layer that is discretely arranged in the first direction, and a fourth gate layer that is discretely arranged on the second P-type active layer;
  • the first processing structure layout includes the second P-type active layer.
  • a first active layer discretely arranged in one direction and extending in a second direction, and a first isolation gate arranged on the first active layer and extending in a second direction;
  • a second processing structure layout It includes a second active layer arranged discretely in the first direction and extending in the second direction, and a second isolation gate arranged on the first active layer and extending in the second direction; the first direction intersects with the second direction.
  • Figure 1 is a schematic diagram of the circuit structure of the readout circuit provided by this embodiment
  • Figures 2 to 15 are schematic diagrams of the layout structure of the readout circuit provided by this embodiment.
  • the details are as follows:
  • the first direction is perpendicular to the second direction for illustration, the first direction is the horizontal direction (the extending direction of the storage array gap), and the second direction is the longitudinal direction (the width direction of the storage array gap). ); since perpendicularity is a special case of intersection, in other embodiments, those skilled in the art can set the intersection mode of the first direction and the second direction according to any angle, and this embodiment is still applicable.
  • the readout circuit architecture includes:
  • the first NMOS layout includes a first N-type active layer 101 that is discretely arranged in a first direction, and a first gate layer 102 that is discretely arranged on the first N-type active layer 101;
  • a gate layer 102 is electrically connected to the complementary readout bit line SABLB, and the first N-type active layer 101 located on both sides of the first gate layer 102 is electrically connected to the bit line BL and the second signal terminal respectively.
  • the first NMOS layout is used to form the first NMOS transistor ⁇ N1>, the first NMOS transistor ⁇ N1> is connected between the second signal terminal and the bit line BL, and has a control terminal connected to the complementary read bit line SABLB.
  • the source of the first NMOS transistor ⁇ N1> is connected to the second signal terminal, the drain is connected to the bit line BL, and the gate is connected to the complementary read bit line SABLB.
  • the second NMOS layout includes a second N-type active layer 103 arranged discretely in the first direction, and a second gate layer 104 arranged discretely on the second N-type active layer 103; wherein, the first The second gate layer 104 is electrically connected to the read bit line SABL, and the second N-type active layer 103 located on both sides of the second gate layer 104 is electrically connected to the complementary bit line BLB and the second signal terminal respectively.
  • the second NMOS layout is used to form the second NMOS transistor ⁇ N2>, and the second NMOS transistor ⁇ N2> is connected between the second signal terminal and the complementary bit line BLB, and has a control terminal connected to the sense bit line SABL.
  • the source of the second NMOS transistor ⁇ N2> is connected to the second signal terminal, the drain is connected to the complementary bit line BLB, and the gate is connected to the read bit line SABL.
  • the first PMOS layout includes a first P-type active layer 201 that is discretely arranged in a first direction, and a third gate layer 202 that is discretely arranged on the first P-type active layer 201;
  • the tri-gate layer 202 is electrically connected to the complementary read bit line SABLB, and the first P-type active layer 201 located on both sides of the third gate layer 202 is electrically connected to the read bit line SABL and the first signal terminal respectively.
  • the first PMOS layout is used to form the first PMOS transistor ⁇ P1>, the first PMOS transistor ⁇ P1> is connected between the first signal terminal and the read bit line SABL, and has a control terminal connected to the complementary read bit line SABLB .
  • the source of the first PMOS transistor ⁇ P1> is connected to the first signal terminal, the drain is connected to the sense bit line SABL, and the gate is connected to the complementary sense bit line SABLB.
  • the second PMOS layout includes a second P-type active layer 203 arranged discretely in the first direction, and a fourth gate layer 204 arranged discretely on the second P-type active layer 203; wherein, the first The four gate layers 204 are electrically connected to the read bit line SABL, and the second P-type active layer 203 located on both sides of the fourth gate layer 204 are electrically connected to the complementary read bit line SABLB and the first signal terminal respectively.
  • the second PMOS layout is used to form the second PMOS transistor ⁇ P2>, the second PMOS transistor ⁇ P2> is connected between the first signal terminal and the complementary read bit line SABLB, and has a control terminal connected to the read bit line SABL .
  • the source of the second PMOS transistor ⁇ P2> is connected to the first signal terminal, the drain is connected to the complementary read bit line SABLB, and the gate is connected to the read bit line SABL.
  • the first processing structure layout includes a first active layer 301 arranged discretely in the first direction and extending in the second direction, and a first active layer 301 arranged on the first active layer 301 and extending in the second direction An isolation gate 311; wherein, since the first isolation gate 311 receives an isolation signal (Isolation Signal, ISO), the first active layer 301 located on both sides of the first isolation gate 311 is respectively electrically connected to the bit line BL and the readout bit line SABL.
  • ISO isolation Signal
  • the first active layer 301 and the first isolation gate 311 are used to form the first isolation MOS transistor ⁇ 11>, the source of the first isolation MOS transistor ⁇ 11> is connected to the bit line BL, the drain is connected to the read bit line SABL, and the gate The pole is used for receiving the isolation signal ISO, and the first isolation MOS transistor ⁇ 11> is used for conducting according to the isolation signal, so as to electrically connect the bit line BL and the read bit line SABL.
  • the second processing structure layout includes a second active layer 302 arranged discretely in the first direction and extending in the second direction, and a first active layer 302 arranged on the second active layer 302 and extending in the second direction
  • Two isolation gates 312 wherein, the second isolation gate 312 is used to receive the isolation signal ISO, and the second active layer 302 located on both sides of the second isolation gate 312 is electrically connected to the complementary bit line BLB and the complementary readout bit line respectively SABLB.
  • the second active layer 302 and the second isolation gate 312 are used to form the second isolated MOS transistor ⁇ 12>, the source of the second isolated MOS transistor ⁇ 12> is connected to the complementary bit line BLB, and the drain is connected to the complementary read bit line SABLB , the gate is used to receive the isolation signal ISO, and the second isolation MOS transistor ⁇ 12> is used to conduct according to the isolation signal, so that the complementary bit line BLB is electrically connected to the complementary read bit line SABLB.
  • bit line BL is connected to the memory cell ⁇ 01> of one memory array 400 in the adjacent memory array 400
  • complementary bit line BLB is connected to the memory cell of another memory array 400 in the adjacent memory array 400 ⁇ 02>.
  • both the first signal terminal and the second signal terminal are used to receive the high level corresponding to logic "1"; in the process of data readout, the first signal terminal is used to receive the high level corresponding to logic "1". High level, the second signal terminal is used to receive low level corresponding to logic "0".
  • the voltage of the first level signal is greater than the voltage of the second level signal (Negative Cell Storing Signal, NCS), that is, the first level signal PCS is the corresponding logic "1 ", the second level signal NCS is a low level corresponding to logic "0"; in other embodiments, it can also be set that the voltage of the first level signal is less than the voltage of the second level signal, That is, the first level signal is a low level corresponding to logic "0", and the second level signal is a high level corresponding to logic "1".
  • the memory precharges the bit line BL, the complementary bit line BLB, the read bit line SABL and the complementary read bit line SABLB to a preset voltage.
  • a first level signal PCS is provided to the first signal terminal and the second signal terminal; the first PMOS transistor ⁇ P1 The gate of > is connected to the complementary read bit line SABLB, the drain is connected to the read bit line SABL, and the source is connected to the first signal terminal.
  • the first PMOS transistor ⁇ P1> is turned on based on the preset voltage of the complementary read bit line SABLB , the first signal terminal is electrically connected to the read bit line SABL, and the read bit line SABL is pulled high under the action of the first level signal PCS; the gate of the second PMOS transistor ⁇ P2> is connected to the read bit line SABL, The drain is connected to the complementary read bit line SABLB, the source is connected to the first signal terminal, and after the second PMOS transistor ⁇ P2> is turned on based on the preset voltage of the read bit line SABL, the first signal terminal is connected to the complementary read bit line SABLB electrically connected, the complementary readout bit line SABLB is pulled high under the action of the first level signal PCS.
  • the first PMOS transistor ⁇ P1> and the second PMOS transistor ⁇ P2> are turned off.
  • the semiconductor devices constituting the sense amplifier may have different device characteristics (for example, threshold voltage) due to process changes, temperature and other factors, that is, due to external factors or the influence of the formation process
  • the first PMOS transistor ⁇ P1> There is a difference in the threshold voltage of the second PMOS transistor ⁇ P2>, that is, the conduction capabilities of the first PMOS transistor ⁇ P1> and the second PMOS transistor ⁇ P2> are different based on the preset voltage, and the first PMOS transistor ⁇ P1>
  • the second PMOS transistor ⁇ P2> is turned on, there is a difference in the level of the read bit line SABL and the complementary read bit line SABLB, that is, the offset noise of the first PMOS transistor ⁇ P1> and the second PMOS transistor ⁇ P2> , due to the connection method of the first
  • the drain is connected to the bit line BL, and the source is connected to the second The second signal terminal, the first NMOS transistor ⁇ N1> is turned on based on the complementary readout bit line SABLB after being pulled high, the bit line BL is electrically connected to the second signal terminal after the first NMOS transistor ⁇ N1> is turned on, and the bit line BL is in It is pulled high under the action of the first level signal PCS; since the gate of the second NMOS transistor ⁇ N2> is connected to the read bit line SABL, the drain is connected to the complementary bit line BLB, and the source is connected to the second signal terminal, the second NMOS The transistor ⁇ N2> is turned on based on the sense bit line SABL after being pulled high, and the complementary bit line BLB is electrically connected to the second signal terminal after the second NMOS
  • the semiconductor device constituting the sense amplifier may have different device characteristics (for example, threshold voltage) due to process variation, temperature and other factors, that is, due to external factors or the influence of the formation process
  • the first NMOS transistor ⁇ N1> and The threshold voltage of the second NMOS transistor ⁇ N2> is different, that is, the conduction capabilities of the first NMOS transistor ⁇ N1> and the second NMOS transistor ⁇ N2> are different after being turned on based on the preset voltage, and the first NMOS transistor ⁇ N1> and the After the second NMOS transistor ⁇ N2> is turned on, there is a difference in the level of the bit line BL and the complementary bit line BLB, and the turn-on voltage of the first NMOS transistor ⁇ N1> and the second NMOS transistor ⁇ N2> includes the first PMOS
  • the threshold voltages of the second PMOS transistor ⁇ P2> and the second NMOS transistor ⁇ N2> are both lower than the threshold voltages of the first PMOS transistor ⁇ P1> and the first For the NMOS transistor ⁇ N1>, after the offset is eliminated, based on the above discussion, it can be seen that the voltage of the bit line BL is lower than the voltage of the complementary bit line BLB.
  • the voltage of the target memory cell is shared on the bit line BL, and the voltage of the target memory cell is shared on the complementary bit line BLB.
  • the actual voltage ratio of the bit line BL is The theoretical voltage is relatively small, so that in the second readout stage, that is, in the actual readout amplification stage, the first isolation MOS transistor ⁇ 11> and the second isolation MOS transistor ⁇ 12> are turned on, and the bit line BL and the readout bit line SABL is electrically connected, and the complementary bit line BLB is electrically connected to the complementary readout bit line SABLB, so that the gate voltage received by the second PMOS transistor ⁇ P2> and the second NMOS transistor ⁇ N2>, which originally have a smaller threshold voltage, is relatively small, thereby Offset cancellation of the readout circuit is realized.
  • the layout of the readout circuit provided by this embodiment can avoid the layout shift and eliminate the MOS transistor, thereby reducing the layout area of the readout circuit.
  • the readout circuit architecture further includes:
  • the first processing structure layout further includes: a first pre-charge gate 321 disposed on the first active layer 301 and extending in a first direction, and the first pre-charge gate 321 and the first isolation gate 311 The two directions are arranged sequentially; wherein, the first precharge gate 321 is used to receive a precharge signal (Precharge Signal, PRE), and the first gate located on both sides of the first precharge gate 321 and away from the first isolation gate 311
  • the active layer 301 is used to receive the preset voltage V BLP ; the first active layer 301 located on both sides of the first precharge gate 321 and shared with the first isolation gate 311 is connected to the bit line BL.
  • the first precharge gate 321 and the first active layer 301 are used to form the first precharge MOS transistor ⁇ 21>, one terminal of the first precharge MOS transistor ⁇ 21> is connected to the bit line BL, and the other terminal is used to receive The preset voltage V BLP , the control terminal is used to receive the pre-charge signal PRE, and the first pre-charge MOS transistor ⁇ 21> is configured to be turned on based on the pre-charge signal PRE.
  • the source of the first precharge MOS transistor ⁇ 21> is connected to the bit line BL, the drain is used to receive the preset voltage V BLP , and the gate is used to receive the precharge signal PRE.
  • the preset voltage V BLP 1/2V DD , where V DD is the internal power supply voltage of the chip; in other embodiments, the preset voltage V BLP can be set according to specific application scenarios.
  • the second processing structure layout further includes: a second pre-charge gate 322 and a third pre-charge gate 323, arranged on the second active layer 302 and extending in the first direction, and the second pre-charge gate 322,
  • the second isolation gate 312 and the third pre-charge gate 323 are arranged sequentially in the second direction; wherein, the second pre-charge gate 322 is used to receive the pre-charge signal; it is located on both sides of the second pre-charge gate 322 and The second active layer 302 away from the second isolation gate 312 is used to receive the preset voltage V BLP ; the second active layer 302 located on both sides of the second precharge gate 322 and shared with the second isolation gate 312 is connected Complementary bit line BLB; the third precharge gate 323 is used to receive a precharge signal; the second active layer 302 located on both sides of the third precharge gate 323 and away from the second isolation gate 312 is used to receive a preset voltage V BLP ; the second active layer 302 located on both sides of the third precharge
  • the second precharge gate 322 and the second active layer 302 are used to form the second precharge MOS transistor ⁇ 22>, one terminal of the second precharge MOS transistor ⁇ 22> is connected to the complementary bit line BLB, and the other terminal is used for Receiving the preset voltage V BLP , the control terminal is used to receive the pre-charging signal PRE, and the second pre-charging MOS transistor ⁇ 22> is configured to conduct based on the pre-charging signal PRE.
  • the source of the second precharge MOS transistor ⁇ 22> is connected to the complementary bit line BLB, the drain is used to receive the preset voltage V BLP , and the gate is used to receive the precharge signal PRE.
  • the terminal of the first pre-charge MOS transistor ⁇ 21> receiving the preset voltage V BLP is connected to the terminal of the second pre-charge MOS transistor ⁇ 22> receiving the preset voltage V BLP
  • the drain of the first pre-charging MOS transistor ⁇ 21> is connected to the drain of the second pre-charging MOS transistor ⁇ 22> for receiving a preset voltage V BLP .
  • control terminal of the first pre-charging MOS transistor ⁇ 21> is connected to the control terminal of the second pre-charging MOS transistor ⁇ 22>, that is, the gate of the first pre-charging MOS transistor ⁇ 21> and the second The gate of the pre-charging MOS transistor ⁇ 22> is connected to receive the pre-charging signal PRE.
  • the third precharge gate 323 and the second active layer 302 are used to form the third precharge MOS transistor ⁇ 23>, and one terminal of the third precharge MOS transistor ⁇ 23> is connected to the read bit line SABL or the complementary read bit
  • the other terminal of the line SABLB is used to receive the preset voltage V BLP
  • the control terminal is used to receive the pre-charge signal PRE
  • the third pre-charge MOS transistor ⁇ 23> is configured to be turned on based on the pre-charge signal PRE.
  • the source of the third precharge MOS transistor ⁇ 23> is connected to the read bit line SABL or the complementary read bit line SABLB
  • the drain is used to receive the preset voltage V BLP
  • the gate is used to receive the precharge Signal PRE.
  • the first processing structure layout further includes: an equalization gate 331, disposed on the first active layer 301, extending in the first direction, and the first pre-charge gate 321, the first isolation gate 311 and the equalization gate 331
  • the gates 331 are arranged sequentially in the second direction; wherein, the equalization gate 331 is used to receive an equalizing signal (Equalizing Signal, EQ);
  • the layer 301 is connected to the complementary read bit line SABLB; the first active layer 301 located on both sides of the balance gate 331 and shared with the first isolation gate 311 is connected to the SABL.
  • the balanced gate 331 and the first active layer 301 are used to form a balanced MOS transistor ⁇ 31>, and the balanced MOS transistor ⁇ 31> is connected between the read bit line SABL and the complementary read bit line SABLB, and has a receiving equalized signal EQ control terminals.
  • the source of the equalization MOS transistor ⁇ 31> is connected to the readout bit line SABL
  • the drain is connected to the complementary readout bitline SABLB
  • the gate is used to receive the equalization signal EQ.
  • the levels of the bit line BL and the read bit line BLB are only affected by the first NMOS transistor ⁇ N1> and the second NMOS transistor ⁇ N2>, that is, during the offset elimination process, it can also provide
  • the equalization signal EQ is used to turn on the equalization MOS transistor ⁇ 31>, so that the read bit line SABL is electrically connected to the complementary read bit line SABLB, so as to ignore the offset of the first PMOS transistor ⁇ P1> and the second PMOS transistor ⁇ P2> Therefore, the offset noise of the first NMOS transistor ⁇ N1> and the second NMOS transistor ⁇ N2> can be eliminated more accurately.
  • the readout circuit architecture further includes:
  • the first processing structure layout further includes: a first pre-charge gate 321 and a third pre-charge gate 323 disposed on the first active layer 301 and extending in a first direction, and the first pre-charge gate
  • the charging grid 321, the first isolation grid 311 and the third pre-charging grid 323 are sequentially arranged in the second direction; wherein, the first pre-charging grid 321 is used to receive the pre-charging signal PRE, and is located at the first pre-charging grid.
  • the first active layer 301 on both sides of the gate 321 and away from the first isolation gate 311 is used to receive the preset voltage V BLP ;
  • An active layer 301 is connected to the bit line BL;
  • the third isolation gate 323 is used to receive the precharge signal PRE, and the first active layer 301 located on both sides of the third precharge gate 323 and away from the first isolation gate 311 is used for When receiving the preset voltage V BLP ;
  • the first active layer 301 located on both sides of the third precharge gate 323 and shared with the first isolation gate 311 is connected to the sense bit line SABL or the complementary sense bit line SABLB.
  • the first pre-charge gate 321 and the first active layer 301 are used to form the first pre-charge MOS transistor ⁇ 21>, and the third pre-charge gate 323 and the first active layer 301 are used to form the third pre-charge MOS transistor ⁇ 23>.
  • the first processing structure layout further includes: an equalization gate 331, disposed on the first active layer 301, extending in the first direction, and the first pre-charge gate 321, the first isolation gate 311, the equalization gate 331
  • the gate 331 and the third pre-charge gate 323 are arranged in sequence in the second direction; wherein, the equalization gate 331 is used to receive the equalization signal EQ; it is located on both sides of the equalization gate 331 and shared with the third pre-charge gate 323
  • the first active layer 301 is connected to the read bit line SABL; the first active layer 301 located on both sides of the balance gate 331 and shared with the first isolation gate 311 is connected to the complementary read bit line SABLB.
  • the balanced gate 331 and the first active layer 301 are used to form a balanced MOS transistor ⁇ 31>.
  • the layout of the second processing structure further includes: a second pre-charge gate 322 disposed on the second active layer 302 and extending in the first direction, and the second pre-charge gate 322 and the second isolation gate 312 Arranged sequentially in two directions; wherein, the second pre-charge gate 322 is used to receive the pre-charge signal PRE; When receiving the preset voltage V BLP ; the second active layer 302 located on both sides of the second precharge gate 322 and shared with the second isolation gate 312 is connected to the complementary bit line BLB. The second precharge gate 322 and the second active layer 302 are used to form the second precharge MOS transistor ⁇ 22>.
  • the layout of the first processing structure can be set such that the first isolation gate 311, the first pre-charge gate 321, the third pre-charge gate 323, and the equalization gate 331 are sequentially arranged in the second direction, and the second The processing structure board diagram may be set such that the second isolation gate 312 and the second pre-charge gate 322 are sequentially arranged in the second direction.
  • the first active layers 301 for electrically connecting the preset voltage V BLP are connected to each other, and the second active layers 301 for electrically connecting the preset voltage V BLP are connected to each other.
  • the source layers 302 are connected to each other.
  • the active transistors for connecting the preset voltage V BLP are connected to each other.
  • the active regions for connecting the preset voltage V BLP are connected to each other; arranged in the first direction Among the plurality of third precharging MOS transistors ⁇ 23>, the active regions for connecting to the preset voltage V BLP are connected to each other.
  • the active regions for connecting to the preset voltage V BLP are connected to each other.
  • the active regions for connecting to the preset voltage V BLP are connected to each other.
  • the active regions for connecting the preset voltage V BLP are connected to each other.
  • the active regions for connecting to the preset voltage V BLP are connected to each other.
  • this embodiment also provides multiple arrangements of the first processing structure layout, the second processing structure layout, the first NMOS layout, the second NMOS layout, the first PMOS layout, and the second PMOS layout.
  • the first layout mode is in the second direction, the first processing structure layout, the first NMOS layout, the first PMOS layout, the second PMOS layout, the second NMOS layout and the second processing structure layout in sequence arrangement.
  • the second layout mode is that in the second direction, the first processing structure layout, the first PMOS layout, the first NMOS layout, the second NMOS layout, the second PMOS layout, and the second processing structure layout in sequence arrangement.
  • the third layout mode is that in the second direction, the first NMOS layout, the first processing structure layout, the first PMOS layout, the second PMOS layout, the second processing structure layout and the second NMOS layout in sequence arrangement.
  • the fourth layout mode is that in the second direction, the first PMOS layout, the first processing structure layout, the first NMOS layout, the second NMOS layout, the second processing structure layout and the second PMOS layout are arranged in sequence.
  • the fifth layout mode is that in the second direction, the first PMOS layout, the first NMOS layout, the first processing structure, the second processing structure, the second NMOS layout and the second PMOS layout are arranged in sequence.
  • the sixth layout mode is that in the second direction, the first NMOS layout, the first PMOS layout, the first processing structure, the second processing structure, the second PMOS layout and the second NMOS layout are arranged in sequence.
  • the first active layer and the second active layer are connected. Further, referring to FIG. 15 , the fifth layout and the sixth layout are still applicable to the interconnection of the first active layers for electrically connecting the preset voltage V BLP , and the second active layers for electrically connecting the preset voltage V BLP The way the source layers are connected to each other.
  • the gate of the first PMOS transistor is connected to the complementary readout bit line, and the drain is connected to the readout bit line.
  • the first signal terminal is electrically connected to the readout bit line, and One signal end is used to receive the high level corresponding to the logic "1", that is, the first signal end receives the internal power supply voltage of the chip; at this time, the first PMOS transistor that is turned on affects the read based on the level and threshold voltage of the complementary read bit line.
  • the level of the bit line; the gate of the second PMOS transistor is connected to the read bit line, and the drain is connected to the complementary read bit line.
  • the first signal terminal is electrically connected to the read bit line, and the second One signal terminal is used to receive the high level corresponding to logic "1", that is, the internal power supply voltage of the chip at the first signal terminal; at this time, the second PMOS transistor that is turned on affects the complementary readout based on the level and threshold voltage of the readout bit line
  • the level of the bit line, the threshold voltage difference between the first PMOS transistor and the second PMOS transistor will cause the level difference between the read bit line and the complementary read bit line, that is, through the voltage of the read bit line and the complementary read bit line Flat, reflecting the offset noise of the first PMOS transistor and the second PMOS transistor.
  • the gate of the first NMOS transistor is connected to the complementary read bit line, and the drain is connected to the bit line; the gate of the second NMOS transistor is connected to the read bit line, and the drain is complementary to the bit line; since the first isolated MOS transistor ⁇ 11>
  • the connection mode with the second isolation MOS transistor ⁇ 12> when the offset elimination is in progress, the first isolation MOS transistor ⁇ 11> and the second isolation MOS transistor ⁇ 12> are not conducted, and the second signal terminal is also used to receive Corresponding to the high level of logic "1", that is, the first signal terminal receives the internal power supply voltage of the chip; so that the conduction difference between the first NMOS transistor and the second NMOS transistor does not affect the readout bit line and the complementary readout bit line, but It is to directly adjust the bit line voltage and the complementary bit line voltage.
  • the conduction degree of the first NMOS transistor is based on the voltage of the complementary read bit line and the threshold voltage of the first NMOS transistor are determined
  • the conduction degree of the second NMOS transistor is determined based on the level of the read bit line and the threshold voltage of the second NMOS transistor; at this time, the first NMOS transistor and the second NMOS transistor are respectively based on complementary
  • the adjusted bit line voltage and the complementary bit line reflect the offset noise of the first PMOS transistor and the second PMOS transistor, and simultaneously reflect the first NMOS transistor and the second PMOS transistor.
  • the layout of the readout circuit provided by this embodiment can avoid the layout shift and eliminate the MOS transistor, thereby reducing the layout area of the readout circuit.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)

Abstract

本申请实施例涉及半导体版图设计领域，特别涉及一种读出电路架构，包括：第一NMOS版图，包括第一N型有源层以及设置在第一N型有源层上分立排布的第一栅极层；第二NMOS版图，包括第二N型有源层以及设置在第二N型有源层上分立排布的第二栅极层；第一PMOS版图，包括第一P型有源层以及设置在第一P型有源层上分立排布的第三栅极层；第二PMOS版图，包括第二P型有源层以及设置在第二P型有源层上分立排布的第四栅极层；第一处理结构版图，第一有源层以及第一隔离栅极；第二处理结构版图，第二有源层以及第二隔离栅极，本申请实施例在不多引入偏移消除MOS管的前提下，以消除读出电路中的偏移噪声，有利于DRAM集成度的提高。

Description

读出电路架构
相关申请的交叉引用
本申请基于申请号为202111082961.8、申请日为2021年09月15日、申请名称为“读出电路架构”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此以引入方式并入本申请。
技术领域
本申请涉及半导体电路版图领域，特别涉及一种读出电路架构。
背景技术
动态随机存取存储存储器(Dynamic Random Access Memory，DRAM)通过单元电容中的电荷来写入数据；单元电容连接至位线和互补位线，在DRAM中，当执行读取操作或刷新操作时，读出放大器读出并放大位线和互补位线之间的电压差。
构成读出放大器的半导体器件可能由于工艺变化、温度等因素的影响从而具有不同的器件特性(例如，阈值电压)。不同的器件特性会导致读出放大器中的产生偏移噪声，而偏移噪声会降低读出放大器的有效读出裕度，并且会降低DRAM的性能。
发明内容
本申请实施例提供一种读出电路架构，在不多引入偏移消除金属氧化物半导体场效应晶体管(Metal Oxide Semiconductor Field Effect Transistor，MOSFET)管的前提下，以消除读出电路中的偏移噪声，有利于DRAM集成度的提高。
本申请实施例提供了一种读出电路架构，包括：第一N型金属-氧化物-半导体(N-Metal-Oxide-Semiconductor，NMOS)版图，包括在第一方向上分立排布的第一N型有源层，以及设置在第一N型有源层上分立排布的第一栅极层；第二NMOS版图，包括在第一方向上分立排布的第二N型有源层，以及设置在第二N型有源层上分立排布的第二栅极层；第一P型金属-氧化物-半导体(P-Metal-Oxide-Semiconductor，PMOS)版图，包括在第一方向上分立排布的第一P型有源层，以及设置在第一P型有源层上分立排布的第三栅极层；第二PMOS版图，包括在第一方向上分立排布的第二P型有源层，以及设置在第二P型有源层上分立排布的第四栅极层；第一处理结构版图，包括在第一方向上分立 排布且在第二方向上延伸的第一有源层，以及设置在第一有源层上，且在第二方向上延伸的第一隔离栅极；第二处理结构版图，包括在第一方向上分立排布且在第二方向上延伸的第二有源层，以及设置在第一有源层上，且在第二方向上延伸的第二隔离栅极；第一方向和第二方向相交，第一信号端用于接收第一电平信号、第二信号端用于接收第一电平信号和第二电平信号，第一电平信号大于第二电平信号。
在偏移消除过程中，第一PMOS管的栅极连接互补读出位线，漏极连接读出位线，第一PMOS管导通后第一信号端与读出位线电连接，且第一信号端用于接收对应逻辑“1”的高电平，即第一信号端接收芯片内部电源电压；此时导通后的第一PMOS管基于互补读出位线的电平和阈值电压影响读出位线的电平；第二PMOS管的栅极连接读出位线，漏极连接互补读出位线，第二PMOS管导通后第一信号端与读出位线电连接，且第一信号端用于接收对应逻辑“1”的高电平，即第一信号端芯片内部电源电压；此时导通后的第二PMOS管基于读出位线的电平和阈值电压影响互补读出位线的电平，第一PMOS管和第二PMOS管的阈值电压差异会导致读出位线和互补读出位线的电平差异，即通过读出位线和互补读出位线的电平，反应出第一PMOS管和第二PMOS管的偏移噪声。第一NMOS管的栅极连接至互补读出位线，漏极连接位线；第二NMOS管的栅极连接至读出位线，漏极互补位线；由于第一隔离MOS管<11>和第二隔离MOS管<12>的连接方式，在偏移消除进行时，第一隔离MOS管<11>和第二隔离MOS管<12>不导通，且第二信号端也用于接收对应逻辑“1”的高电平，即第一信号端接收芯片内部电源电压；使得第一NMOS管和第二NMOS管的导通差异并不影响读出位线和互补读出位线，而是直接调整位线电压和互补位线电压。另外，由于读出位线和互补读出位线的电平已反应出第一PMOS管和第二PMOS管的偏移噪声，且第一NMOS管的导通程度基于互补读出位线的电平和第一NMOS管的阈值电压确定，第二NMOS管的导通程度基于读出位线的电平和第二NMOS管的阈值电压确定；此时，第一NMOS管和第二NMOS管分别基于互补读出位线和读出位线导通后，使调整后的位线电压和互补位线反应出第一PMOS管和第二PMOS管的偏移噪声，并同时反应出第一NMOS管和第二NMOS管的偏移噪声，即完成读出电路的偏移消除操作。因此，本申请实施例提供的读出电 路的版图可以避免布局偏移消除MOS管，从而减小了读出电路的版图面积。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，这些附图示出了符合本申请实施例，并于说明书一起配置为说明本申请的技术方案。
图1为本申请实施例提供的读出电路的电路结构示意图；
图2～图15为本申请实施例提供的读出电路的版图结构示意图。
具体实施方式
构成读出放大器的半导体器件可能由于工艺变化、温度等因素的影响从而具有不同的器件特性(例如，阈值电压)。不同的器件特性会导致读出放大器中的产生偏移噪声，而偏移噪声会降低读出放大器的有效读出裕度，并且会降低DRAM的性能。
目前对DRAM的偏移噪声的消除过程中，需专门设计用于偏移消除的MOS管，从而增大感测放大电路所需的版图面积，不利于DRAM集成度的提高。因此，如何在不多引入偏移消除MOS管的前提下，以消除读出电路中的偏移噪声，是当下亟待解决的问题。
本申请实施例提供了一种读出电路架构，包括：第一NMOS版图，包括在第一方向上分立排布的第一N型有源层，以及设置在第一N型有源层上分立排布的第一栅极层；第二NMOS版图，包括在第一方向上分立排布的第二N型有源层，以及设置在第二N型有源层上分立排布的第二栅极层；第一PMOS版图，包括在第一方向上分立排布的第一P型有源层，以及设置在第一P型有源层上分立排布的第三栅极层；第二PMOS版图，包括在第一方向上分立排布的第二P型有源层，以及设置在第二P型有源层上分立排布的第四栅极层；第一处理结构版图，包括在第一方向上分立排布且在第二方向上延伸的第一有源层，以及设置在第一有源层上，且在第二方向上延伸的第一隔离栅极；第二处理结构版图，包括在第一方向上分立排布且在第二方向上延伸的第二有源层，以及设置在第一有源层上，且在第二方向上延伸的第二隔离栅极；第一方向和第二方向相交。
本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
图1为本实施例提供的读出电路的电路结构示意图，图2～图15为本实施例提供的读出电路的版图结构示意图，以下结合附图对本申请各实施例提供的读出电路架构作进一步详细说明，具体如下：
需要说明的是，在本实施例中，以第一方向与第二方向垂直进行举例说明，第一方向为横向(存储阵列间隙的延伸方向)，第二方向为纵向(存储阵列间隙的宽度方向)；由于垂直是相交的一种特殊情况，在其他实施例中，本领域技术人员可以根据任意角度设置第一方向和第二方向的相交的方式，本实施例依然适用。
参考图1和图2，读出电路架构，包括：
第一NMOS版图，包括在第一方向上分立排布的第一N型有源层101，以及设置在第一N型有源层101上分立排布的第一栅极层102；其中，第一栅极层102电连接互补读出位线SABLB，位于所述第一栅极层102两侧的第一N型有源层101分别电连接位线BL和第二信号端。
第一NMOS版图用于形成第一NMOS管<N1>，第一NMOS管<N1>连接在第二信号端和位线BL之间，且具有连接到互补读出位线SABLB的控制端子。在一些实施例中，第一NMOS管<N1>的源极连接第二信号端，漏极连接位线BL，栅极连接至互补读出位线SABLB。
第二NMOS版图，包括在第一方向上分立排布的第二N型有源层103，以及设置在第二N型有源层103上分立排布的第二栅极层104；其中，第二栅极层104电连接读出位线SABL，位于第二栅极层104两侧的第二N型有源层103分别电连接互补位线BLB和第二信号端。
第二NMOS版图用于形成第二NMOS管<N2>，第二NMOS管<N2>连接在第二信号端和互补位线BLB之间，且具有连接到读出位线SABL的控制端子。在一些实施例中，第二NMOS管<N2>的源极连接第二信号端，漏极连接互补位线BLB，栅极连接至读出位线SABL。
第一PMOS版图，包括在第一方向上分立排布的第一P型有源层201，以及设置在第一P型有源层201上分立排布的第三栅极层202；其中，第三栅极层202电连接互补读出位线SABLB，位于第三栅极层202两侧的第一P型有源层201分别电连接读出位线SABL和第一信号端。
第一PMOS版图用于形成第一PMOS管<P1>，第一PMOS管<P1>连接在第一信号端和读出位线SABL之间，且具有连接到互补读出位线SABLB的控制端子。在一些实施例中，第一PMOS管<P1>的源极连接第一信号端，漏极连接读出位线SABL，栅极连接至互补读出位线SABLB。
第二PMOS版图，包括在第一方向上分立排布的第二P型有源层203，以及设置在第二P型有源层203上分立排布的第四栅极层204；其中，第四栅极层204电连接读出位线SABL，位于第四栅极层204两侧的第二P型有源层203分别电连接互补读出位线SABLB和第一信号端。
第二PMOS版图用于形成第二PMOS管<P2>，第二PMOS管<P2>连接在第一信号端和互补读出位线SABLB之间，且具有连接到读出位线SABL的控制端子。在一些实施例中，第二PMOS管<P2>的源极连接第一信号端，漏极连接互补读出位线SABLB，栅极连接至读出位线SABL。
第一处理结构版图，包括在第一方向上分立排布且在第二方向上延伸的第一有源层301，以及设置在第一有源层301上，且在第二方向上延伸的第一隔离栅极311；其中，第一隔离栅极311由于接收隔离信号(Isolation Signal，ISO)，位于第一隔离栅极311两侧的第一有源层301分别电连接位线BL和读出位线SABL。
第一有源层301和第一隔离栅极311用于形成第一隔离MOS管<11>，第一隔离MOS管<11>源极连接位线BL，漏极连接读出位线SABL，栅极用于接收隔离信号ISO，第一隔离MOS管<11>用于根据隔离信号导通，使位线BL与读出位线SABL电连接。
第二处理结构版图，包括在第一方向上分立排布且在第二方向上延伸的第二有源层302，以及设置在第二有源层302上，且在第二方向上延伸的第二隔离栅极312；其中，第二隔离栅极312用于接收隔离信号ISO，位于第二隔离栅极312两侧的第二有源层302分别电连接互补位线BLB和互补读出位线SABLB。
第二有源层302和第二隔离栅极312用于形成第二隔离MOS管<12>，第二隔离MOS管<12>源极连接互补位线BLB，漏极连接互补读出位线SABLB，栅极用于接收隔离信号ISO，第二隔离MOS管<12>用于根据隔离信号导通，使互补位线BLB与互补读出位线SABLB电连接。
对于位线BL和互补位线BLB，位线BL连接相邻存储阵列400中一存储阵列400的存储单元<01>，互补位线BLB连接相邻存储阵列400中另一存储阵列400的存储单元<02>。
在偏移消除过程中，第一信号端和第二信号端都用于接收对应逻辑“1”的高电平；在数据读出过程中，第一信号端用于接收对应逻辑“1”的高电平，第二信号端用于接收对应逻辑“0”的低电平。在本实施例中，第一电平信号(Positive Cell Storing Signal，PCS)的电压大于第二电平信号(Negative Cell Storing Signal，NCS)的电压，即第一电平信号PCS为对应逻辑“1”的高电平，第二电平信号NCS为对应逻辑“0”的低电平；在其他实施例中，同样可以设置为，第一电平信号的电压小于第二电平信号的电压，即第一电平信号为对应逻辑“0”的低电平，第二电平信号为对应逻辑“1”的高电平。
对于存储器而言，在数据读出之前，存储器会将位线BL、互补位线BLB、读出位线SABL和互补读出位线SABLB预充电至预设电压。
对于本实施例的读出电路而言，在第一读出阶段，即存储器的偏移消除阶段，向第一信号端和第二信号端提供第一电平信号PCS；第一PMOS管<P1>的栅极连接互补读出位线SABLB，漏极连接读出位线SABL，源极连接第一信号端，第一PMOS管<P1>基于互补读出位线SABLB的预设电压导通后，第一信号端与读出位线SABL电连接，读出位线SABL在第一电平信号PCS的作用下被拉高；第二PMOS管<P2>的栅极连接读出位线SABL，漏极连接互补读出位线SABLB，源极连接第一信号端，第二PMOS管<P2>基于读出位线SABL的预设电压导通后，第一信号端与互补读出位线SABLB电连接，互补读出位线SABLB在第一电平信号PCS的作用下被拉高。
读出位线SABL和互补读出位线SABLB的电平拉高后，第一PMOS管<P1>和第二PMOS管<P2>关断。但由于构成读出放大器的半导体器件可能由于工艺变化、温度等因素的影响从而具有不同的器件特性(例如，阈值电压)，即由于外部因素或形成工艺的影响，导致第一PMOS管<P1>和第二PMOS管<P2>的阈值电压存在差异，即第一PMOS管<P1>和第二PMOS管<P2>基于预设电压导通后的导通能力不同，第一PMOS管<P1>和第二PMOS管<P2>导通后，读出位线SABL和互补读出位线SABLB的电平存在差异，即第一PMOS管<P1>和第二 PMOS管<P2>的偏移噪声，由于第一隔离MOS管<11>和第二隔离MOS管<12>的连接方式，在偏移消除过程中，第一隔离MOS管<11>和第二隔离MOS管<12>不导通，此时，读出位线SABL的电平并不同步至位线BL，互补读出位线SABLB的电平并不同步至互补位线BLB。
读出位线SABL和互补读出位线SABLB的电平拉高后，由于第一NMOS管<N1>的栅极连接至互补读出位线SABLB，漏极连接位线BL，源极连接第二信号端，第一NMOS管<N1>基于拉高后的互补读出位线SABLB导通，第一NMOS管<N1>导通后位线BL与第二信号端电连接，位线BL在第一电平信号PCS的作用下被拉高；由于第二NMOS管<N2>的栅极连接至读出位线SABL，漏极互补位线BLB，源极连接第二信号端，第二NMOS管<N2>基于拉高后的读出位线SABL导通，第二NMOS管<N2>导通后互补位线BLB与第二信号端电连接，互补位线BLB在第一电平信号PCS的作用下被拉高。
由于构成读出放大器的半导体器件可能由于工艺变化、温度等因素的影响从而具有不同的器件特性(例如，阈值电压)，即由于外部因素或形成工艺的影响，导致第一NMOS管<N1>和第二NMOS管<N2>的阈值电压存在差异，即第一NMOS管<N1>和第二NMOS管<N2>基于预设电压导通后的导通能力不同，第一NMOS管<N1>和第二NMOS管<N2>导通后，位线BL和互补位线BLB的电平存在差异，且第一NMOS管<N1>和第二NMOS管<N2>的导通电压中包括第一PMOS管<P1>和第二PMOS管<P2>的偏移噪声，此时位线BL和互补位线BLB的电平差异包括第一PMOS管<P1>和第二PMOS管<P2>的偏移噪声以及第一NMOS管<N1>和第二NMOS管<N2>的偏移噪声。假设以第一PMOS管<P1>和第一NMOS管<N1>为标准，第二PMOS管<P2>和第二NMOS管<N2>的阈值电压皆小于第一PMOS管<P1>和第一NMOS管<N1>，偏移消除后基于上述论述可知，位线BL的电压小于互补位线BLB的电压。
在数据共享阶段，将目标存储单元的电压分享至位线BL上，将目标存储单元的电压分享至互补位线BLB上，此时，由于偏移消除过程的执行，位线BL的实际电压比理论电压偏小，从而实现在第二读出阶段，即实际读出放大阶段中，第一隔离MOS管<11>和第二隔离MOS管<12>导通，位线BL与读出位线SABL电连接，互补位线BLB与互补读出位线SABLB电连接，使得原本阈值电压较 小的第二PMOS管<P2>和第二NMOS管<N2>接收到的栅极电压偏小，从而实现读出电路的偏移消除。
综上所述，本实施例提供的读出电路的版图可以避免布局偏移消除MOS管，从而减小了读出电路的版图面积。
在一个实施例中，参考图2，读出电路架构，还包括：
第一处理结构版图还包括：第一预充栅极321，设置在第一有源层301上，在第一方向上延伸，且第一预充栅极321和第一隔离栅极311在第二方向上依次排布；其中，第一预充栅极321用于接收预充电信号(Precharge Signal，PRE)，位于第一预充栅极321两侧且远离第一隔离栅极311的第一有源层301用于接收预设电压V BLP；位于第一预充栅极321两侧且与第一隔离栅极311共用的第一有源层301连接位线BL。
第一预充栅极321和第一有源层301用于形成第一预充电MOS管<21>，第一预充电MOS管<21>的一端子连接位线BL，另一端子用于接收预设电压V BLP，控制端子用于接收预充电信号PRE，第一预充电MOS管<21>被配置为基于预充电信号PRE导通。在本实施例中，第一预充电MOS管<21>的源极连接位线BL，漏极用于接收预设电压V BLP，栅极用于接收预充电信号PRE。
在本实施例中，预设电压V BLP＝1/2V DD，其中，V DD为芯片内部电源电压；在其他实施例中，预设电压V BLP可以根据具体应用场景进行设置。
第二处理结构版图还包括：第二预充栅极322和第三预充栅极323，设置在第二有源层302上，在第一方向上延伸，且第二预充栅极322、第二隔离栅极312和第三预充栅极323在第二方向上依次排布；其中，第二预充栅极322用于接收预充电信号；位于第二预充栅极322两侧且远离第二隔离栅极312的第二有源层302用于接收预设电压V BLP；位于第二预充栅极322两侧且与第二隔离栅极312共用的第二有源层302连接互补位线BLB；第三预充栅极323用于接收预充电信号；位于第三预充栅极323两侧且远离第二隔离栅极312的第二有源层302用于接收预设电压V BLP；位于第三预充栅极323两侧且与第二隔离栅极312共用的第二有源层302连接读出位线SABL或互补读出位线SABLB。
第二预充栅极322和第二有源层302用于形成第二预充电MOS管<22>，第二预充电MOS管<22>的一端子连接互补位线BLB，另一端子用于接收预设电压 V BLP，控制端子用于接收预充电信号PRE，第二预充电MOS管<22>被配置为基于预充电信号PRE导通。在本实施例中，第二预充电MOS管<22>的源极连接互补位线BLB，漏极用于接收预设电压V BLP，栅极用于接收预充电信号PRE。
在一个具体的例子中，第一预充电MOS管<21>接收预设电压V BLP的端子和第二预充电MOS管<22>接收预设电压V BLP的端子相连接，在一些实施例中，第一预充电MOS管<21>的漏极和第二预充电MOS管<22>的漏极相连接，用于接收预设电压V BLP。
在一些实施例中，第一预充电MOS管<21>的控制端子和第二预充电MOS管<22>的控制端子相连接，即第一预充电MOS管<21>的栅极和第二预充电MOS管<22>的栅极相连接，用于接收预充电信号PRE。
第三预充栅极323和第二有源层302用于形成第三预充电MOS管<23>，第三预充电MOS管<23>的一端子连接读出位线SABL或互补读出位线SABLB，另一端子用于接收预设电压V BLP，控制端子用于接收预充电信号PRE，第三预充电MOS管<23>被配置为基于预充电信号PRE导通。在本实施例中，第三预充电MOS管<23>的源极连接读出位线SABL或互补读出位线SABLB，漏极用于接收预设电压V BLP，栅极用于接收预充电信号PRE。
进一步地，第一处理结构版图还包括：均衡栅极331，设置在第一有源层301上，在第一方向上延伸，且第一预充栅极321、第一隔离栅极311和均衡栅极331在第二方向上依次排布；其中，均衡栅极331用于接收均衡信号(Equalizing Signal，EQ)；位于均衡栅极331两侧且远离第一隔离栅极311的第一有源层301连接互补读出位线SABLB；位于均衡栅极331两侧且与第一隔离栅极311共用的第一有源层301连接SABL。
均衡栅极331和第一有源层301用于形成均衡MOS管<31>，均衡MOS管<31>连接在读出位线SABL和互补读出位线SABLB之间，且具有接收均衡信号EQ的控制端子。在本实施例中，均衡MOS管<31>的源极连接读出位线SABL，漏极连接互补读出位线SABLB，栅极用于接收均衡信号EQ。
在偏移消除过程中，位线BL和读出位线BLB的电平仅受第一NMOS管<N1>和第二NMOS管<N2>的影响，即在偏移消除过程中，还可以提供均衡信号EQ以导通均衡MOS管<31>，从而使读出位线SABL与互补读出位线SABLB电连 接，以忽略第一PMOS管<P1>和第二PMOS管<P2>的偏移影响，从而更加准确地消除第一NMOS管<N1>和第二NMOS管<N2>的偏移噪声。
在另一个实施例中，参考图3和图4，读出电路架构，还包括：
参考图3，第一处理结构版图还包括：第一预充栅极321和第三预充栅极323，设置在在第一有源层301上，在第一方向上延伸，且第一预充栅极321、第一隔离栅极311和第三预充栅极323在第二方向上依次排布；其中，第一预充栅极321用于接收预充电信号PRE，位于第一预充栅极321两侧且远离第一隔离栅极311的第一有源层301用于接收预设电压V BLP；位于第一预充栅极321两侧且与第一隔离栅极311共用的第一有源层301连接位线BL；第三隔离栅极323用于接收预充电信号PRE，位于第三预充栅极323两侧且远离第一隔离栅极311的第一有源层301用于接收预设电压V BLP；位于第三预充栅极323两侧且与第一隔离栅极311共用的第一有源层301连接读出位线SABL或者互补读出位线SABLB。第一预充栅极321和第一有源层301用于形成第一预充电MOS管<21>，第三预充栅极323和第一有源层301用于形成第三预充电MOS管<23>。
进一步地，第一处理结构版图还包括：均衡栅极331，设置在第一有源层301上，在第一方向上延伸，且第一预充栅极321、第一隔离栅极311、均衡栅极331和第三预充栅极323在第二方向上依次排布；其中，均衡栅极331用于接收均衡信号EQ；位于均衡栅极331两侧且与第三预充栅极323共用的第一有源层301连接读出位线SABL；位于均衡栅极331两侧且与第一隔离栅极311共用的第一有源层301连接互补读出位线SABLB。均衡栅极331和第一有源层301用于形成均衡MOS管<31>。
第二处理结构版图还包括：第二预充栅极322，设置在第二有源层302上，在第一方向上延伸，且第二预充栅极322和第二隔离栅极312在第二方向上依次排布；其中，第二预充栅极322用于接收预充电信号PRE；位于第二预充栅极322两侧且远离第二隔离栅极312的第二有源层302用于接收预设电压V BLP；位于第二预充栅极322两侧且与第二隔离栅极312共用的第二有源层302连接互补位线BLB。第二预充栅极322和第二有源层302用于形成第二预充电MOS管<22>。
参考图4，第一处理结构版图可以设置为第一隔离栅极311、第一预充栅极 321、第三预充栅极323和均衡栅极331在第二方向上依次排布，第二处理结构板图可以设置为，第二隔离栅极312和第二预充栅极322在第二方向上依次排布。
在一个例子中，参考图5～图7，在第一方向上，用于电连接预设电压V BLP的第一有源层301相互连接，用于电连接预设电压V BLP的第二有源层302相互连接。
在一些实施例中，参考图5，在第一有源层中301中，在第一方向上排列的多个第一预充电MOS管<21>中，用于连接预设电压V BLP的有源区相互连接。在第二有源层302中，在第一方向上排列的多个第二预充电MOS管<22>中，用于连接预设电压V BLP的有源区相互连接；在第一方向上排列的多个第三预充电MOS管<23>中，用于连接预设电压V BLP的有源区相互连接。
在一些实施例中，参考图6，在第一有源层中301中，在第一方向上排列的多个第一预充电MOS管<21>中，用于连接预设电压V BLP的有源区相互连接；在第一方向上排列的多个第三预充电MOS管<23>中，用于连接预设电压V BLP的有源区相互连接。在第二有源层302中，在第一方向上排列的多个第二预充电MOS管<22>中，用于连接预设电压V BLP的有源区相互连接。
在一些实施例中，参考图7，在第一有源层中301中，在第一方向上排列的多个第一预充电MOS管<21>和多个第三预充电MOS管<23>中，用于连接预设电压V BLP的有源区相互连接。在第二有源层302中，在第一方向上排列的多个第二预充电MOS管<22>中，用于连接预设电压V BLP的有源区相互连接。
另外，本实施例还给出了多种第一处理结构版图、第二处理结构版图、第一NMOS版图、第二NMOS版图、第一PMOS版图和第二PMOS版图的排布方式。
参考图2～图7，第一布局方式即在第二方向上，第一处理结构版图、第一NMOS版图、第一PMOS版图、第二PMOS版图、第二NMOS版图和第二处理结构版图依次排列。
参考图8～图10，第二布局方式即在第二方向上，第一处理结构版图、第一PMOS版图、第一NMOS版图、第二NMOS版图、第二PMOS版图和第二处理结构版图依次排列。
需要说明的是，本方式同样适用于用于电连接预设电压V BLP的第一有源层301相互连接，用于电连接预设电压V BLP的第二有源层302相互连接的方式， 但本实施例中并未给出相应附图，本领域技术人员可以依据第一布局方式所公开的内容合理推导得知。
参考图11和图12，第三布局方式即在第二方向上，第一NMOS版图、第一处理结构版图、第一PMOS版图、第二PMOS版图、第二处理结构版图和第二NMOS版图依次排列。
第四布局方式即在第二方向上，第一PMOS版图、第一处理结构版图、第一NMOS版图、第二NMOS版图、第二处理结构版图和第二PMOS版图依次排列。
参考图13，第五布局方式即在第二方向上，第一PMOS版图、第一NMOS版图、第一处理结构、第二处理结构、第二NMOS版图和第二PMOS版图依次排列。
参考图14，第六布局方式即在第二方向上，第一NMOS版图、第一PMOS版图、第一处理结构、第二处理结构、第二PMOS版图和第二NMOS版图依次排列。
需要说明的是，在第五布局方式和第六布局方式中，第一有源层和第二有源层相连接。进一步地，参考图15，第五布局方式和第六布局方式依然适用于用于电连接预设电压V BLP的第一有源层相互连接，用于电连接预设电压V BLP的第二有源层相互连接的方式。
需要说明的是，上述各个晶体管定义的具体“源极”和“漏极”的连接方式，并不构成对本实施例的限定，在其他实施例中，可以采用“漏极”替换“源极”，“源极”替换“漏极”的连接方式。
在偏移消除过程中，第一PMOS管的栅极连接互补读出位线，漏极连接读出位线，第一PMOS管导通后第一信号端与读出位线电连接，且第一信号端用于接收对应逻辑“1”的高电平，即第一信号端接收芯片内部电源电压；此时导通后的第一PMOS管基于互补读出位线的电平和阈值电压影响读出位线的电平；第二PMOS管的栅极连接读出位线，漏极连接互补读出位线，第二PMOS管导通后第一信号端与读出位线电连接，且第一信号端用于接收对应逻辑“1”的高电平，即第一信号端芯片内部电源电压；此时导通后的第二PMOS管基于读出位线的电平和阈值电压影响互补读出位线的电平，第一PMOS管和第二PMOS 管的阈值电压差异会导致读出位线和互补读出位线的电平差异，即通过读出位线和互补读出位线的电平，反应出第一PMOS管和第二PMOS管的偏移噪声。第一NMOS管的栅极连接至互补读出位线，漏极连接位线；第二NMOS管的栅极连接至读出位线，漏极互补位线；由于第一隔离MOS管<11>和第二隔离MOS管<12>的连接方式，在偏移消除进行时，第一隔离MOS管<11>和第二隔离MOS管<12>不导通，且第二信号端也用于接收对应逻辑“1”的高电平，即第一信号端接收芯片内部电源电压；使得第一NMOS管和第二NMOS管的导通差异并不影响读出位线和互补读出位线，而是直接调整位线电压和互补位线电压。另外，由于读出位线和互补读出位线的电平已反应出第一PMOS管和第二PMOS管的偏移噪声，且第一NMOS管的导通程度基于互补读出位线的电平和第一NMOS管的阈值电压确定，第二NMOS管的导通程度基于读出位线的电平和第二NMOS管的阈值电压确定；此时，第一NMOS管和第二NMOS管分别基于互补读出位线和读出位线导通后，使调整后的位线电压和互补位线反应出第一PMOS管和第二PMOS管的偏移噪声，并同时反应出第一NMOS管和第二NMOS管的偏移噪声，即完成读出电路的偏移消除操作。因此，本实施例提供的读出电路的版图可以避免布局偏移消除MOS管，从而减小了读出电路的版图面积。
需要说明的是，为了突出本申请的创新部分，本实施例中并没有将与解决本申请所提出的技术问题关系不太密切的单元引入，但这并不表明本实施例中不存在其它的单元；本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。
本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。

Claims (15)

  1. 一种读出电路架构，包括：
    第一NMOS版图，包括在第一方向上分立排布的第一N型有源层，以及设置在所述第一N型有源层上分立排布的第一栅极层；
    第二NMOS版图，包括在所述第一方向上分立排布的第二N型有源层，以及设置在所述第二N型有源层上分立排布的第二栅极层；
    第一PMOS版图，包括在所述第一方向上分立排布的第一P型有源层，以及设置在所述第一P型有源层上分立排布的第三栅极层；
    第二PMOS版图，包括在所述第一方向上分立排布的第二P型有源层，以及设置在所述第二P型有源层上分立排布的第四栅极层；
    第一处理结构版图，包括在所述第一方向上分立排布且在第二方向上延伸的第一有源层，以及设置在第一有源层上，且在所述第二方向上延伸的第一隔离栅极；
    第二处理结构版图，包括在所述第一方向上分立排布且在所述第二方向上延伸的第二有源层，以及设置在第一有源层上，且在所述第二方向上延伸的第二隔离栅极；
    所述第一方向和所述第二方向相交，第一信号端用于接收第一电平信号、第二信号端用于接收所述第一电平信号和第二电平信号，所述第一电平信号大于所述第二电平信号。
  2. 根据权利要求1所述的读出电路架构，其中，包括：
    所述第一处理结构版图还包括：第一预充栅极，设置在所述第一有源层上，在所述第一方向上延伸，且所述第一预充栅极和所述第一隔离栅极在所述第二方向上依次排布；
    所述第二处理结构版图还包括：第二预充栅极和第三预充栅极，设置在所述第二有源层上，在所述第一方向上延伸，且所述第二预充栅极、所述第二隔离栅极和所述第三预充栅极在所述第二方向上依次排布。
  3. 根据权利要求2所述的读出电路架构，其中，所述第一处理结构版图还包括：均衡栅极，设置在所述第一有源层上，在所述第一方向上延伸，且所述第一预充栅极、所述第一隔离栅极和所述均衡栅极在所述第二方向上依次排布。
  4. 根据权利要求1所述的读出电路架构，其中，包括：
    所述第一处理结构版图还包括：第一预充栅极和第三预充栅极，设置在所述第一有源层上，在所述第一方向上延伸，且所述第一预充栅极、所述第一隔离栅极和所述第三预充栅极在所述第二方向上依次排布；
    所述第二处理结构版图还包括：第二预充栅极，设置在所述第二有源层上，在所述第一方向上延伸，且所述第二预充栅极和所述第二隔离栅极在所述第二方向上依次排布。
  5. 根据权利要求4所述的读出电路架构，其中，所述第一处理结构版图还包括：均衡栅极，设置在所述第一有源层上，在所述第一方向上延伸，且所述第一预充栅极、所述第一隔离栅极、所述均衡栅极和所述第三预充栅极在所述第二方向上依次排布。
  6. 根据权利要求1～5任一项所述的读出电路架构，其中，在所述第一方向上，用于电连接预设电压的第一有源层相互连接。
  7. 根据权利要求1～5任一项所述的读出电路架构，其中，在所述第一方向上，用于电连接预设电压的第二有源层相互连接。
  8. 根据权利要求1所述的读出电路架构，其中，在所述第二方向上，所述第一处理结构版图、所述第一NMOS版图、所述第一PMOS版图、所述第二PMOS版图、所述第二NMOS版图和所述第二处理结构版图依次排列。
  9. 根据权利要求1所述的读出电路架构，其中，在所述第二方向上，所述第一处理结构版图、所述第一PMOS版图、所述第一NMOS版图、所述第二NMOS版图、所述第二PMOS版图和所述第二处理结构版图依次排列。
  10. 根据权利要求1所述的读出电路架构，其中，在所述第二方向上，所述第一NMOS版图、所述第一处理结构版图、所述第一PMOS版图、所述第二PMOS版图、所述第二处理结构版图和所述第二NMOS版图依次排列。
  11. 根据权利要求1所述的读出电路架构，其中，在所述第二方向上，所述第一PMOS版图、所述第一处理结构版图、所述第一NMOS版图、所述第二NMOS版图、所述第二处理结构版图和所述第二PMOS版图依次排列。
  12. 根据权利要求1所述的读出电路架构，其中，在所述第二方向上，所述第一PMOS版图、所述第一NMOS版图、所述第一处理结构、所述第二处理结 构、所述第二NMOS版图和所述第二PMOS版图依次排列。
  13. 根据权利要求1所述的读出电路架构，其中，在所述第二方向上，所述第一NMOS版图、所述第一PMOS版图、所述第一处理结构、所述第二处理结构、所述第二PMOS版图和所述第二NMOS版图依次排列。
  14. 根据权利要求12或13所述的读出电路架构，其中，所述第一有源层和所述第二有源层相连接。
  15. 根据权利要求1所述的读出电路架构，其中，所述第一方向和所述第二方向相垂直。
PCT/CN2022/072740 2021-09-15 2022-01-19 读出电路架构 WO2023040158A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US18/151,466 US20230162782A1 (en) 2021-09-15 2023-01-08 Sense amplifier circuit architecture

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202111082961.8A CN115810371A (zh) 2021-09-15 2021-09-15 读出电路架构
CN202111082961.8 2021-09-15

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/151,466 Continuation US20230162782A1 (en) 2021-09-15 2023-01-08 Sense amplifier circuit architecture

Publications (1)

Publication Number Publication Date
WO2023040158A1 true WO2023040158A1 (zh) 2023-03-23

Family

ID=85482051

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/072740 WO2023040158A1 (zh) 2021-09-15 2022-01-19 读出电路架构

Country Status (3)

Country Link
US (1) US20230162782A1 (zh)
CN (1) CN115810371A (zh)
WO (1) WO2023040158A1 (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103928402A (zh) * 2013-01-11 2014-07-16 中芯国际集成电路制造(上海)有限公司 共用栅极的半导体结构及对应的形成方法
CN112582372A (zh) * 2019-09-30 2021-03-30 长鑫存储技术有限公司 Dram阵列版图及dram存储器
CN112992892A (zh) * 2021-02-05 2021-06-18 长鑫存储技术有限公司 标准单元版图模板以及半导体结构

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103928402A (zh) * 2013-01-11 2014-07-16 中芯国际集成电路制造(上海)有限公司 共用栅极的半导体结构及对应的形成方法
CN112582372A (zh) * 2019-09-30 2021-03-30 长鑫存储技术有限公司 Dram阵列版图及dram存储器
CN112992892A (zh) * 2021-02-05 2021-06-18 长鑫存储技术有限公司 标准单元版图模板以及半导体结构

Also Published As

Publication number Publication date
CN115810371A (zh) 2023-03-17
US20230162782A1 (en) 2023-05-25

Similar Documents

Publication Publication Date Title
WO2022170720A1 (zh) 灵敏放大器及其控制方法
TWI489455B (zh) 不具專用通閘電晶體之差動感測放大器
WO2022021775A1 (zh) 灵敏放大器、存储器和灵敏放大器的控制方法
WO2021196841A1 (zh) 灵敏放大器、存储器和数据读出方法
WO2022048073A1 (zh) 灵敏放大器、存储器和灵敏放大器的控制方法
WO2024007521A1 (zh) 存储器及其访问方法、电子设备
US7230842B2 (en) Memory cell having p-type pass device
US11862285B2 (en) Sense amplifier, memory and control method of sense amplifier
WO2023273554A1 (zh) 读出电路结构
WO2023040158A1 (zh) 读出电路架构
WO2023082548A1 (zh) 读出电路的版图结构和数据读出方法
EP4246520A1 (en) Sensing amplification circuit and data readout method
US8542547B2 (en) Semiconductor device and data processing system
US7609572B2 (en) Semiconductor memory device
CN115411035A (zh) 读出电路版图、结构以及存储器版图
JP2012027983A (ja) 半導体装置
WO2023024640A1 (zh) 感测放大电路和数据读出方法
WO2023133975A1 (zh) 读出电路版图
WO2023024608A1 (zh) 感测放大结构和存储器架构
CN115565562B (zh) 读出电路结构
US6765830B2 (en) Memory device with SRAM interface and DRAM cells
WO2023093095A1 (zh) 感测放大电路以及数据读出方法
WO2023133973A1 (zh) 本地放大电路、数据读出方法和存储器
CN115565568B (zh) 读出电路结构
US20230162762A1 (en) Sense amplifier circuit and data read method

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22868539

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE