WO2022037243A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2022037243A1
WO2022037243A1 PCT/CN2021/101436 CN2021101436W WO2022037243A1 WO 2022037243 A1 WO2022037243 A1 WO 2022037243A1 CN 2021101436 W CN2021101436 W CN 2021101436W WO 2022037243 A1 WO2022037243 A1 WO 2022037243A1
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Prior art keywords
trench
layer
forming
semiconductor structure
filling
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PCT/CN2021/101436
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English (en)
French (fr)
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严勋
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长鑫存储技术有限公司
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Priority to US17/530,561 priority Critical patent/US11984347B2/en
Publication of WO2022037243A1 publication Critical patent/WO2022037243A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/101—Forming openings in dielectrics
    • H01L2221/1015—Forming openings in dielectrics for dual damascene structures

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for forming the same.
  • the size of the conductive interconnect lines in the integrated circuit and the distance between the conductive interconnect lines are continuously reduced, resulting in a corresponding increase in the arrangement density of the conductive interconnect lines.
  • the arrangement density of the conductive interconnects increases, a short circuit phenomenon between the conductive interconnects is easily induced, thereby causing the performance of the semiconductor device to be degraded or even fail.
  • one aspect of the present application provides a method for forming a semiconductor structure, including:
  • first mask layer with a first opening on the dielectric layer, the first opening exposes the first filling layer and part of the dielectric layer
  • Conductive material is formed in the first trench and the second trench.
  • another aspect of the present application provides a semiconductor structure formed using the above-described method for forming a semiconductor structure.
  • the method for forming a semiconductor structure includes: providing a substrate; forming a dielectric layer having a first trench on the substrate; forming a first filling layer partially filling the first trench; A first mask layer with an opening, the first opening exposes the first filling layer and part of the dielectric layer; the dielectric layer is etched using the first mask layer as a mask to form a second trench; the first filling layer is removed; Conductive material is formed in a trench and a second trench.
  • the height of the first filling layer can be adjusted to the alignment of the semiconductor structure.
  • the cloth density is matched, so as to avoid excessive lateral etching of the dielectric layer caused by the etching process, thereby avoiding the short circuit phenomenon of the conductive material, and improving the electrical performance of the semiconductor structure.
  • a second trench with a width larger than that of the first trench is formed by an etching process, so that the first trench and the second trench can be used to deposit conductive materials together to form contact performance and structural reliability. better semiconductor structures.
  • FIG. 1 is a flowchart of a method for forming a semiconductor structure according to an embodiment
  • FIG. 2 is a schematic cross-sectional view of the substrate 100 provided by an embodiment
  • step S200 is a schematic cross-sectional view of the semiconductor structure after step S200;
  • FIG. 4 is a schematic cross-sectional view of the semiconductor structure after step S300 according to an embodiment
  • step S400 is a schematic cross-sectional view of the semiconductor structure after step S400 according to an embodiment
  • FIG. 6 is a schematic cross-sectional view of the semiconductor structure after step S500 in an embodiment
  • FIG. 7 is a schematic top view of the semiconductor structure of the embodiment of FIG. 6;
  • step S700 is a schematic cross-sectional view of the semiconductor structure after step S700 in an embodiment
  • step S800 is a schematic cross-sectional view of the semiconductor structure after step S800 in an embodiment
  • FIG. 10 is a flowchart of a method for forming a semiconductor structure according to another embodiment
  • step S310 is a schematic cross-sectional view of the semiconductor structure after step S310 in another embodiment
  • step S410 is a schematic cross-sectional view of the semiconductor structure after step S410 in another embodiment
  • FIG. 13 is a schematic cross-sectional view of a semiconductor structure including a first region and a second region according to another embodiment
  • FIG. 14 is a schematic cross-sectional view of a prior art semiconductor structure.
  • FIG. 1 is a flowchart of a method for forming a semiconductor structure according to an embodiment.
  • the method for forming a semiconductor structure includes steps S100 to S700 .
  • the substrate 100 is provided.
  • FIG. 2 is a schematic cross-sectional view of a substrate 100 according to an embodiment.
  • a first conductive layer 110 and a first dielectric layer 120 have been formed in the substrate 100 .
  • the first conductive layer 110 may be, but is not limited to, structures such as conductive interconnect lines.
  • the first conductive layer 110 may transmit electrical signals to the substrate.
  • the first dielectric layer 120 is used to isolate the adjacent first conductive layers 110, so as to avoid short circuit or leakage current between the first conductive layers 110, thereby improving the electrical reliability of the device.
  • the first conductive layer 110 and the first dielectric layer 120 may be obtained by forming trenches in the substrate 100 and filling them, or by directly depositing them on the surface of the substrate 100 .
  • This embodiment does not specifically limit the first conductive layer 110 and a method for forming the first dielectric layer 120 .
  • FIG. 3 is a schematic cross-sectional view of the semiconductor structure after step S200 .
  • the first trench 210 exposes part of the first conductive layer 110 in the direction perpendicular to the substrate 100 , so as to In the subsequent steps, a conductive material in contact with the first conductive layer 110 is formed, so as to realize the transmission of signals in the first conductive layer 110 .
  • the dielectric layer 200 may be formed on the surface of the substrate 100 first, and then the dielectric layer 200 may be etched to form the first trench 210; or the surface of the substrate 100 may be formed first in the position and size of the first trench 210.
  • the matching sacrificial layer is formed, and then a dielectric layer 200 is formed in the gap of the sacrificial layer, and finally the sacrificial layer is cleaned and removed to form the first trench 210 .
  • the thickness of the dielectric layer 200 is 100 nm to 1500 nm, such as 500 nm, 1000 nm, etc.
  • the specific thickness of the dielectric layer 200 is determined by the height of the second conductive layer 600 to be formed.
  • the dielectric layer 200 may be formed by chemical vapor deposition (Chemical Vapor Deposition, CVD) or physical vapor deposition (Physical Vapour Deposition, PVD) and other processes.
  • the material of the dielectric layer 200 may be a low-K (dielectric constant) material, such as at least one of silicon dioxide (SiO 2 ), silicon oxycarbide (SiCO), or fluorinated silicon glass (FSG).
  • FIG. 4 is a schematic cross-sectional view of the semiconductor structure after step S300 in an embodiment.
  • the sidewall of the first filling layer 211 is in contact with the inner wall of the first trench 210 , that is, the first The projection of the filling layer 211 on the substrate 100 completely covers the exposed substrate 100 , or completely covers the exposed first conductive layer 110 , and the top of the first filling layer 211 is lower than the top of the dielectric layer 200 . It can be understood that, in the subsequent steps of etching to form other trench structures, if the first conductive layer 110 and the dielectric layer 200 are completely exposed to the etching liquid or the etching gas, the first conductive layer 110 and the dielectric layer 200 will be damaged. .
  • step S300 by covering the exposed first conductive layer 110 and part of the sidewalls of the first trench 210 with the first filling layer 211, in the subsequent etching step, the first filling layer 211 in the substrate 100 can be prevented from Damage to the conductive layer 110 can also prevent lateral etching of the sidewalls of the covered dielectric layer 200, thereby improving the reliability of the semiconductor structure.
  • FIG. 5 is a schematic cross-sectional view of the semiconductor structure after step S400 in an embodiment.
  • the first opening 310 on the first mask layer 300 exposes the first filling layer 211 , and Part of the dielectric layer 200 is exposed, and the position and size of the first opening 310 correspond to the position and size of the second trench 220 to be formed, so that the second trench 220 is formed based on the first mask layer 300 in a subsequent step.
  • the first mask layer 300 can be a photoresist layer or a hard mask layer, such as silicon nitride, silicon oxynitride, etc.
  • an appropriate first mask layer 300 can be selected according to the etching time and the etchant. s material.
  • S500 etching the dielectric layer 200 by using the first mask layer 300 as a mask to form the second trench 220 .
  • FIG. 6 is a schematic cross-sectional view of the semiconductor structure after step S500 in an embodiment
  • FIG. 7 is a schematic top view of the semiconductor structure in the embodiment of FIG. 6 .
  • only one second trench 220 is shown in FIG. 7 . and the corresponding first filling layer 211 .
  • the extending direction of the first trench 210 , the extending direction of the first filling layer 211 and the extending direction of the second trench 220 are all the same, and the first trench 210 is parallel to the extending direction
  • the axis of symmetry in the extending direction coincides with the axis of symmetry of the second trench 220 parallel to the extending direction, so as to ensure the etching effect of the second trench 220 .
  • the method may further include: removing the first mask layer 300 on the surface of the substrate 100 .
  • the cross-sections of the first trench 210 and the first filling layer 211 in a direction parallel to the surface of the substrate 100 are circular or square, and then the first trench 210 is filled with conductors to form conductive plugs, and the second trench 210 is filled with conductors to form conductive plugs.
  • the cross section of the groove 220 in the direction parallel to the surface of the substrate 100 is a line shape, and the second groove 220 is subsequently filled with conductors to form conductive lines.
  • the width of the second trench 220 is greater than the width of the first trench 210, and the width of the trench refers to the dimension of the trench in a direction parallel to the substrate 100 and perpendicular to the axis of symmetry of the trench. Specifically, it may be It should be understood that the width of the first filling layer 211 is the same as the width of the first trench 210. Referring to FIG. 7, the width of the first trench 210 is d1 and the width of the second trench 220 is d2. If the width of the second trench 220 is greater than the width of the first trench 210, the target structure of the second conductive layer 600 can be formed in the subsequent steps.
  • FIG. 8 is a schematic cross-sectional view of the semiconductor structure after step S700 in an embodiment.
  • the first filling layer 211 remaining in the first trenches 210 and the second trenches 220 is completely removed, thereby The sidewalls of the dielectric layer 200 and the top of the first conductive layer 110 are completely exposed to fill the first trenches 210 and the second trenches 220 with conductive material in subsequent steps.
  • the first filling layer 211 in the first trench 210 and the second trench 220 can be completely removed by wet etching, and the first filling layer 211 and the dielectric layer with a larger etching selection ratio can be selected.
  • the etching selectivity ratio between the dielectric layer 200 and the first filling layer 211 can be set to be greater than 7, for example, the etching selectivity ratio can be set to 8, so as to reduce the damage to the dielectric layer 200 during the wet etching process, so as to avoid residual dielectric
  • the layer 200 is too thin, thereby preventing the second conductive layer 600 formed in the adjacent second trenches 220 from short-circuiting, that is, improving the reliability of the semiconductor structure.
  • FIG. 9 is a schematic cross-sectional view of the semiconductor structure after step S800 in an embodiment.
  • the first trenches 210 and the second trenches 220 are completely filled with conductive materials, and the first trenches 210 and 220 are completely filled with conductive materials.
  • the conductive materials in the second trenches 220 together constitute the second conductive layer 600 , that is, the bottom of the second conductive layer 600 is in contact with the top of the first conductive layer 110 in the substrate 100 , and the sidewalls of the second conductive layer 600 are in contact with each other.
  • the top of the second conductive layer 600 extends upward to be flush with the top of the dielectric layer 200 or higher than the top of the dielectric layer 200 .
  • the conductive material may be a metal material, such as copper, aluminum, and the like.
  • a barrier layer such as titanium nitride, tantalum nitride, etc., is also formed on the sidewall surface of the dielectric layer 200 to prevent the material of the second conductive layer 600 from diffusing into the dielectric Layer 200.
  • the method for forming a semiconductor structure includes: providing a substrate 100; forming a dielectric layer 200 having a first trench 210 on the substrate 100; forming a first filling layer 211 partially filling the first trench 210; A first mask layer 300 having a first opening 310 is formed on the dielectric layer 200, and the first opening 310 exposes the first filling layer 211 and part of the dielectric layer 200; the dielectric layer 200 is etched by using the first mask layer 300 as a mask to form the second trench 220 ; remove the first filling layer 211 ; and form a conductive material in the first trench 210 and the second trench 220 .
  • the height of the first filling layer 211 can be The arrangement densities of the semiconductor structures are matched, thereby avoiding excessive lateral etching of the dielectric layer 200 by the etching process, avoiding the short circuit phenomenon of the conductive material, and improving the electrical performance of the semiconductor structure.
  • the second trench 220 is formed with a wider width than the first trench 210 through an etching process, so that the first trench 210 and the second trench 220 can be used together for depositing conductive materials to form contact properties and Semiconductor structures with better structural reliability.
  • the method further includes: forming a first barrier layer 400 on the substrate 100 .
  • a first barrier layer 400 is formed on the substrate 100 .
  • the dielectric layer 200 is formed on the first barrier layer 400 .
  • the material of the first barrier layer 400 is silicide, such as at least one of silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), or silicon oxynitride (SiCNO).
  • the first barrier layer 400 can prevent the mutual diffusion of the first conductive layer 110 and the dielectric layer 200 to avoid the degradation of the electrical performance of the semiconductor structure, and the first barrier layer 400 can also protect the substrate 100 to prevent The first conductive layer 110 in the substrate 100 is damaged during the subsequent etching process.
  • step S200 further includes: forming a second barrier layer 500 on the dielectric layer 200 .
  • the second barrier layer 500 can protect the dielectric layer 200 in the subsequent etching process to prevent the top of the dielectric layer 200 from being damaged, thereby improving the performance of the semiconductor structure.
  • the material of the second barrier layer 500 may be the same as or different from the material of the first barrier layer 400 , which is not specifically limited in this embodiment.
  • first barrier layer 400 , the dielectric layer 200 and the second barrier layer 500 may be sequentially formed on the surface of the substrate 100 , and the second barrier layer 500 , the dielectric layer 200 and the first barrier layer 400 may be sequentially etched through a one-step etching process up to the surface of the substrate 100 , thereby simplifying the process flow.
  • FIG. 10 is a flowchart of a method for forming a semiconductor structure according to another embodiment.
  • step S300 includes steps S310 to S320 .
  • FIG. 11 is a schematic cross-sectional view of the semiconductor structure after step S310 in an embodiment.
  • the top of the initial first filling layer 212 is higher than the second barrier layer 500 .
  • chemical vapor deposition or physical vapor deposition can be used to form the initial first filling layer 212, and after the initial first filling layer 212 is formed, the initial first filling layer 212 is filled by chemical mechanical planarization (chemical mechanical planarization, CMP).
  • CMP chemical mechanical planarization
  • the etch back depth is H3
  • the semiconductor structure as shown in the figure can be formed through the etch back in step S320.
  • step S320 all the initial first filling layers 212 on the dielectric layer 200 and a part of the initial first filling layers 212 in the first trenches 210 are etched back, and the remaining initial first filling layers 212 are used as the first filling layers 212.
  • the filling layer 211 includes: etch back all the initial first filling layer 212 on the dielectric layer 200 and part of the initial first filling layer 212 in the first trench 210, so that the height ratio of the first filling layer 211 satisfies a preset range , the remaining initial first filling layer 212 is used as the first filling layer 211 ; wherein, the height ratio is the ratio of the height of the first filling layer 211 along the direction perpendicular to the substrate 100 to the depth of the first trench 210 .
  • the height of the first filling layer 211 along the direction perpendicular to the substrate 100 is H4, the depth of the first trench 210 is H1, and the height ratio is H4/H1. It can be understood that if the height ratio is too large, that is, the height of the first filling layer 211 is too high, in the subsequent step of removing the first filling layer 211, the etchant cannot accurately reach the bottom of the first filling layer 211, so that the As a result, the first filling layer 211 cannot be fully peeled off effectively, thereby reducing the contact area between the second conductive layer 600 and the first conductive layer 110, increasing the contact resistance, and degrading the electrical performance of the semiconductor structure.
  • the etchback time when the first filling layer 211 is formed by the etchback method is long, which is likely to cause damage to the top of the dielectric layer 200 , thereby causing short circuits between adjacent second conductive layers 600 . Therefore, it is necessary to select an appropriate height ratio to obtain better device performance.
  • the height ratio of the first filling layer 211 is between 0.7 and 0.9.
  • the height ratio of the first filling layer 211 may be 0.8, that is, the height ratio of the first filling layer 211 in the direction perpendicular to the substrate 100 is 0.8.
  • the ratio of the height to the depth of the first trench 210 is 0.8.
  • step S400 includes steps S410 to S420.
  • the first mask layer 300 covers the top of the first filling layer 211 and completely fills the first trench 210 , and the first mask layer The top of 300 is higher than the second barrier layer 500 .
  • the first mask layer 300 is a photoresist layer, and the patterning method of the photoresist layer is relatively simple, and in this embodiment, the etching step using the first mask layer 300 as a mask is relatively simple Less, that is, the first mask layer 300 using the photoresist layer can withstand the etching process without causing damage to the semiconductor structure.
  • the first mask layer 300 can be exposed through a mask, wherein the pattern of the mask and the second trench 220 to be formed are on the substrate
  • the projection on 100 is the same, and after exposure, the photoresist layer is developed, so as to remove all the first mask layer 300 in the first trench 210 and part of the first hard mask layer on the dielectric layer 200 to form as shown in Fig. 5 shows the device structure.
  • the step S500 uses the first mask layer 300 as a mask to etch the dielectric layer 200 to form the second trench 220, including: using the first mask layer 300 as a mask to etch the dielectric layer 200 to form the first Two trenches 220 , wherein the depth of the second trench 220 is smaller than the depth of the first trench 210 , and the bottom of the second trench 220 is lower than the top of the first filling layer 211 .
  • the height of the first filling layer 211 can affect the etching rate of the second trench 220
  • the adjustment function specifically, the first filling layer 211 occupies the opening space of the first trench 210, so that the number of etching ions entering the first trench 210 is reduced, thereby reducing the lateral etching rate of the second trench 220, reducing the The size of the second trenches 220 in the direction of the substrate surface prevents adjacent second trenches 220 from being connected.
  • the ratio of the depth of the second trench 220 to the depth of the first trench 210 is between 0.5 and 0.8, that is, the ratio of the depth of the second trench 220 to the depth of the first trench 210
  • the ratio may be, for example, 0.5, 0.7, and the like.
  • the depth of the first trench 210 refers to the vertical distance between the top of the second barrier layer 500 and the surface of the substrate 100
  • the depth of the second trench 220 refers to the second The vertical distance between the top of the barrier layer 500 and the bottom of the second trench 220 . Referring to FIG.
  • the contact area is greater than that with the first trench 220 .
  • the ratio of the depth of the second trench 220 to the depth of the first trench 210 is between 0.5 and 0.8, so that the conductive material and the dielectric layer can be improved without affecting the performance of the device. 200 connection strength, thereby improving the reliability of the semiconductor structure.
  • the substrate 100 includes a first region 130 and a second region 140, the first trenches 210 and the second trenches 220 are both located in the first region 130 and the second region 140, and the first trenches The density of the first trenches 210 in the first region 130 is greater than the density of the first trenches 210 in the second region 140 .
  • FIG. 13 is a schematic cross-sectional view of a semiconductor structure including a first region 130 and a second region 140 according to an embodiment.
  • the first region 130 is a region where elements and wirings are densely distributed.
  • the second area 140 is an area where the components and wirings are sparsely distributed.
  • first area 130 and the second area 140 are only divided according to the distribution density.
  • the layout of the device structure can be better matched, thereby obtaining higher the integration level of the device.
  • the height ratio of the first filling layer 211 in the first region 130 is greater than the height ratio of the first filling layer 211 in the second region 140 .
  • the depths of the first trenches 210 in the first region 130 and the first trenches 210 in the second region 140 are the same, and the height of the first filling layer 211 in the first region 130 is greater than that in the second region 140 by adjusting the height of the first filling layer 211 in the first region 130
  • the height of the second trench 220 in the first region 130 is lower than the lateral etching rate of the second trench 220 in the second region 140 to ensure that the conductive material formed in the first region 130 will not short circuit.
  • the depth of the second trenches 220 in the second region 140 is equal to the depth of the second trenches 220 in the first region 130 such that the conductive material formed in the second region 140 and the first region 130
  • the electrical properties of the conductive materials formed in the same are the same, and the electrical properties of the semiconductor device are improved.
  • the width of the second trench 220 in the second region 140 is equal to the width of the second trench 220 in the first region 130 , and the width is the dimension of the second trench 220 along the surface of the substrate 100 .
  • the depth of the second trenches 220 in the second region 140 is greater than the depth of the second trenches 220 in the first region 130 .
  • FIG. 14 is a schematic cross-sectional view of a semiconductor structure in the prior art. Referring to FIG. 14 , it can be understood that the lateral etching problem of the dielectric layer 200 is more likely to occur in the first region 130 due to the higher arrangement density of the structure, and further A short circuit phenomenon of the second conductive layer 600 is induced. Referring to FIG. 13 , in this embodiment, by setting the depth of the second trenches 220 in the second region 140 to be greater than the depth of the second trenches 220 in the first region 130 , the conduction of the second region 140 can be ensured. The connection strength of the material also avoids the short circuit phenomenon of the conductive material in the first region 130, thereby providing a semiconductor structure with better performance.
  • a semiconductor structure is formed by the above-mentioned method for forming a semiconductor structure.
  • the semiconductor structure includes: a substrate 100;
  • the second trench 220 exposes the first trench 210 in the vertical direction;
  • the second conductive layer 600 which is formed of a conductive material, is disposed in the first trench 210 and the second trench 220 .
  • FIG. 1 and FIG. 10 are shown in sequence according to the arrows, these steps are not necessarily executed in the sequence shown by the arrows. Unless explicitly stated herein, the execution of these steps is not strictly limited to the order, and these steps may be performed in other orders. Moreover, at least a part of the steps in FIG. 1 and FIG. 10 may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but may be executed at different times. These sub-steps or The order of execution of the stages is also not necessarily sequential, but may be performed alternately or alternately with other steps or sub-steps of other steps or at least a portion of a stage.

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Abstract

一种半导体结构及其形成方法，所述半导体结构的形成方法包括：提供衬底；在衬底上形成具有第一沟槽的介质层；形成部分填充第一沟槽的第一填充层；在介质层上形成具有第一开口的第一掩膜层，第一开口暴露出第一填充层以及部分介质层；以第一掩膜层为掩膜蚀刻介质层以形成第二沟槽；去除第一填充层；在第一沟槽和第二沟槽中形成导电材料。本申请实施例通过先形成第一沟槽，在第一沟槽中部分填充第一填充层并在形成第二沟槽后再去除的方法，可以使第一填充层的高度与半导体结构的排布密度相匹配。

Description

半导体结构及其形成方法
相关申请的交叉引用
本申请要求于2020年8月18日提交中国专利局、申请号为2020108296771、发明名称为“半导体结构及其形成方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，特别是涉及一种半导体结构及其形成方法。
技术背景
随着半导体集成电路技术的不断发展，集成电路中导电互连线的尺寸以及导电互连线之间的距离不断缩小，从而导致导电互连线的排布密度也相应地不断增加。随着导电互连线的排布密度的增加，容易引发导电互连线之间的短路现象，从而造成半导体器件的性能降低甚至失效。
发明内容
根据一些实施例，本申请一方面提供一种半导体结构的形成方法，包括：
提供衬底；
在所述衬底上形成具有第一沟槽的介质层；
形成部分填充所述第一沟槽的第一填充层；
在所述介质层上形成具有第一开口的第一掩膜层，所述第一开口暴露出所述第一填充层以及部分所述介质层；
以所述第一掩膜层为掩膜蚀刻所述介质层以形成第二沟槽；
去除所述第一填充层；
在所述第一沟槽和所述第二沟槽中形成导电材料。
根据一些实施例，本申请另一方面提供一种半导体结构，采用如上述的半导体结构的形成方法形成。
本申请实施例的半导体结构的形成方法包括：提供衬底；在衬底上形成具有第一沟槽的介质层；形成部分填充第一沟槽的第一填充层；在介质层上形成具有第一开口的第一掩膜层，第一开口暴露出第一填充层以及部分介质层；以第一掩膜层为掩膜蚀刻介质层以形成第二沟槽；去除第一填充层；在第一沟槽和第二沟槽中形成导电材料。本申请实施例通过先形成第一沟槽，在第一沟槽中部分填充第一填充层并在形成第二沟槽后再去除的方法，可以使第一填充层的高度与半导体结构的排布密度相匹配，从而避免蚀刻工艺对介质层造成过度的横向蚀刻，从而避免了导电材料的短路现象，改善了半导体结构的电学性能。而且，本申请实施例通过蚀刻工艺形成比第一沟槽宽度更大的第二沟槽，可以使第一沟槽和第二沟槽共同用于沉积导电材料，以形成接触性能和结构可靠性更好的半导体结构。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一实施例的半导体结构的形成方法的流程图；
图2为一实施例提供的衬底100的剖面示意图；
图3为步骤S200后的半导体结构的剖面示意图；
图4为一实施例的步骤S300后的半导体结构的剖面示意图；
图5为一实施例的步骤S400后的半导体结构的剖面示意图；
图6为一实施例的步骤S500后的半导体结构的剖面示意图；
图7为图6实施例的半导体结构的俯视示意图；
图8为一实施例的步骤S700后的半导体结构的剖面示意图；
图9为一实施例的步骤S800后的半导体结构的剖面示意图；
图10为另一实施例的半导体结构的形成方法的流程图；
图11为另一实施例的步骤S310后的半导体结构的剖面示意图；
图12为另一实施例的步骤S410后的半导体结构的剖面示意图；
图13为另一实施例的包括第一区和第二区的半导体结构的剖面示意图；
图14为现有技术的半导体结构的剖面示意图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。需要注意的是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
在本申请的描述中，需要理解的是，术语“上”、“下”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方法或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
图1为一实施例的半导体结构的形成方法的流程图，参考图1，在本实施例中，半导体结构的形成方法包括步骤S100至S700。
S100：提供衬底100。
图2为一实施例提供的衬底100的剖面示意图，参考图2，在本实施例中，衬底100中已形成有第一导电层110和第一介质层120。示例性地，第一导电层110可以是但不局限于导电互连线等结构，示例性地，当第一导电层110为导电互连线时，第一导电层110可以传输电信号至衬底100中的半导体器件，如晶体管。第一介质层120用于隔离相邻的第一导电层110，从而避免第一导电层110之间发生短路或漏电流等现象，进而提高器件的电学可靠性。其中，第一导电层110和第一介质层120可以通过在衬底100中形成沟槽并填充获得，也可以通过直接在衬底100表面沉积获得，本实施例不具体限定第一导电层110和第一介质层120的形成方法。
S200：在衬底100上形成具有第一沟槽210的介质层200。
具体地，图3为步骤S200后的半导体结构的剖面示意图，参考图3，在本实施例中，第一沟槽210在垂直于衬底100的方向上暴露部分第一导电层110，以在后续步骤中形成与第一导电层110接触的导电材料，从而实现第一导电层110中的信号的传输。示例性地，可以先在衬底100表面形成介质层200，再对介质层200进行蚀刻形成第一沟槽210；也可以先在衬底100表面形成与第一沟槽210的位置和尺寸相匹配的牺牲层，再在牺牲层的间隙中形成介质层200，最后清洗去除牺牲层从而形成第一沟槽210。
进一步地，介质层200的厚度为100nm至1500nm，例如为500nm、1000nm等，介质层200的具体厚度由待形成的第二导电层600的高度决定。介质层200可以通过化学气相沉积(Chemical Vapor Deposition，CVD)或物理气相沉积(Physical Vapour Deposition，PVD)等工艺方法形成。介质层200的材料可以为低K(介电常数)材料，例如为二氧化硅(SiO 2)、碳氧化硅(SiCO)或氟化硅玻璃(FSG)中的至少一种。
S300：形成部分填充第一沟槽210的第一填充层211。
图4为一实施例的步骤S300后的半导体结构的剖面示意图，参考图4，在本实施例中，第一填充层211的侧壁与第一沟槽210的内壁相贴合，即第一填充层211在衬底100上的投影完全覆盖暴露的衬底100，或者说是完全覆盖暴露的第一导电层110，且第一填充层211的顶部低于介质层200的顶部。可以理解的是，在后续蚀刻以形成其他沟槽结构的步骤中，若第一导电层110和介质层200完全暴露于蚀刻液体或蚀刻气体中，会导致第一导电层110和介质层200损伤。因此，在步骤S300中，通过使第一填充层211覆盖暴露的第一导电层110和第一沟槽210的部分侧壁，在后续的蚀刻步骤中，既可以防止衬底100中的第一导电层110受到损伤，还可以防止被覆盖的介质层200的侧壁被横向蚀刻，从而提高半导体结构的可靠性。
S400：在介质层200上形成具有第一开口310的第一掩膜层300，第一开口310暴露出第一填充层211以及部分介质层200。
具体地，图5为一实施例的步骤S400后的半导体结构的剖面示意图，参考图5，在本实施例中，第一掩膜层300上的第一开口310暴露第一填充层211， 并暴露部分介质层200，第一开口310的位置和尺寸与待形成的第二沟槽220的位置和尺寸相对应，从而在后续步骤中基于第一掩膜层300形成第二沟槽220。其中，第一掩膜层300可以为光刻胶层，也可以为硬掩膜层，例如氮化硅、氮氧化硅等，具体可根据蚀刻时长和蚀刻剂选择恰当的第一掩膜层300的材料。
S500：以第一掩膜层300为掩膜蚀刻介质层200以形成第二沟槽220。
图6为一实施例的步骤S500后的半导体结构的剖面示意图，图7为图6实施例的半导体结构的俯视示意图，为了简化附图，在图7中仅示出了一条第二沟槽220和对应的第一填充层211。参考图6和图7，在本实施例中，第一沟槽210的延伸方向、第一填充层211的延伸方向与第二沟槽220的延伸方向均相同，且第一沟槽210的平行于延伸方向的对称轴与第二沟槽220的平行于延伸方向的对称轴相重合，从而确保第二沟槽220的蚀刻效果。进一步地，步骤S500后还可以包括：去除衬底100表面的第一掩膜层300。
在其他实施例中，第一沟槽210和第一填充层211在平行衬底100表面方向上的截面为圆形或方形，后续在第一沟槽210填充导体形成导电插塞，第二沟槽220在平行衬底100表面方向上的截面为线条形，后续在第二沟槽220填充导体形成导电线。
其中，第二沟槽220的宽度大于第一沟槽210的宽度，沟槽的宽度是指，沟槽平行于衬底100且垂直于沟槽的对称轴的方向上的尺寸，具体地，可以理解的是，第一填充层211的宽度与该第一沟槽210的宽度相同，参考图7，第一沟槽210的宽度为d1，第二沟槽220的宽度为d2，通过在步骤S500中设置第二沟槽220的宽度大于第一沟槽210的宽度，即可在后续步骤中形成目标的第二导电层600的结构。
S600：去除第一填充层211。
图8为一实施例的步骤S700后的半导体结构的剖面示意图，参考图8，在本实施例中，完全去除第一沟槽210和第二沟槽220中剩余的第一填充层211，从而完全暴露介质层200的侧壁和第一导电层110的顶部，以在后续步骤中在第一沟槽210和第二沟槽220中填充导电材料。
进一步地，可以采用湿法蚀刻的方式完全去除第一沟槽210和第二沟槽220 中的第一填充层211，而且，可以通过选择较大蚀刻选择比的第一填充层211和介质层200，例如，可以使介质层200与第一填充层211的蚀刻选择比大于7，例如可以使蚀刻选择比为8，以减少湿法蚀刻过程中对介质层200的损伤，从而避免残留的介质层200过薄，进而防止形成于相邻的第二沟槽220中的第二导电层600发生短路，即提高了半导体结构的可靠性。
S700：在第一沟槽210和第二沟槽220中形成导电材料。
图9为一实施例的步骤S800后的半导体结构的剖面示意图，参考图9，在本实施例中，第一沟槽210和第二沟槽220中完全填充导电材料，第一沟槽210和第二沟槽220中的导电材料共同构成第二导电层600，即，第二导电层600的底部与衬底100中的第一导电层110的顶部相接触，第二导电层600的侧壁与介质层200的侧壁相贴合设置，第二导电层600的顶部向上延伸至与介质层200的顶部相齐平或高于介质层200的顶部。进一步地，导电材料可以为金属材料，例如铜、铝等。
在其他实施例中，在形成第二导电层600之前，还在介质层200的侧壁表面形成阻挡层，如氮化钛，氮化钽等，以防止第二导电层600的材质扩散进介质层200。
在本实施例中，半导体结构的形成方法包括：提供衬底100；在衬底100上形成具有第一沟槽210的介质层200；形成部分填充第一沟槽210的第一填充层211；在介质层200上形成具有第一开口310的第一掩膜层300，第一开口310暴露出第一填充层211以及部分介质层200；以第一掩膜层300为掩膜蚀刻介质层200以形成第二沟槽220；去除第一填充层211；在第一沟槽210和第二沟槽220中形成导电材料。本实施例通过先形成第一沟槽210，在第一沟槽210中部分填充第一填充层211并在形成第二沟槽220后再去除的方法，可以使第一填充层211的高度与半导体结构的排布密度相匹配，从而避免蚀刻工艺对介质层200造成过度的横向蚀刻，避免了导电材料的短路现象，改善了半导体结构的电学性能。而且，本实施例通过蚀刻工艺形成比第一沟槽210宽度更大的第二沟槽220，可以使第一沟槽210和第二沟槽220共同用于沉积导电材料，以形成接触性能和结构可靠性更好的半导体结构。
在其中一个实施例中，步骤S200前还包括：在衬底100上形成第一阻挡层400。具体地，参考图3，若衬底100表面形成有第一阻挡层400，则介质层200形成于第一阻挡层400上。其中，第一阻挡层400的材料为硅化物，例如氮化硅(Si 3N 4)或氮氧化硅(SiON)或氮碳氧化硅(SiCNO)等中的至少一种。在本实施例中，第一阻挡层400可以防止第一导电层110和介质层200的相互扩散，以避免半导体结构的电学性能下降，而且第一阻挡层400还可以保护衬底100，从而防止在后续蚀刻过程中衬底100中的第一导电层110受到损伤。
在其中一个实施例中，继续参考图3，步骤S200还包括：在介质层200上形成第二阻挡层500。第二阻挡层500可以在后续蚀刻过程中对介质层200进行保护，以防止介质层200的顶部收到损伤，从而提高半导体结构的性能。其中，第二阻挡层500的材料可以与第一阻挡层400的材料相同，也可以不同，本实施例不具体进行限定。进一步地，可以先在衬底100表面依次形成第一阻挡层400、介质层200和第二阻挡层500，并通过一步蚀刻工艺依次蚀刻第二阻挡层500、介质层200和第一阻挡层400直至衬底100表面，从而简化工艺流程。
图10为另一实施例的半导体结构的形成方法的流程图，参考图10，在本实施例中，步骤S300包括步骤S310至S320。
S310：在第一沟槽210中和介质层200上形成初始第一填充层212。
图11为一实施例的步骤S310后的半导体结构的剖面示意图，参考图11，在本实施例中，初始第一填充层212的顶部高于第二阻挡层500。进一步地，可以采用化学气相沉积或物理气相沉积的方法形成初始第一填充层212，并在形成初始第一填充层212后，通过化学机械平坦化(chemical mechanical planarization，CMP)对初始第一填充层212的顶部进行处理，以在后续步骤中更加准确地进行目标深度的回刻，从而提高半导体结构的工艺良率。
S320：回刻介质层200上的全部初始第一填充层212和第一沟槽210中的部分初始第一填充层212，剩余的初始第一填充层212作为第一填充层211。可以理解的是，若第一阻挡层400、介质层200和第二阻挡层500的整体高度为H1，第二阻挡层500表面的初始第一填充层212的高度为H2，则回刻深度为H3，即可在第一沟槽210中形成目标高度H4的第一填充层211，其中，H4＝H1+H2-H3， 高度和深度均指垂直于衬底100方向上的尺寸，在本实施例中，通过步骤S320的回刻即可形成如图所示的半导体结构。
在其中一个实施例中，步骤S320回刻介质层200上的全部初始第一填充层212和第一沟槽210中的部分初始第一填充层212，剩余的初始第一填充层212作为第一填充层211，包括：回刻介质层200上的全部初始第一填充层212和第一沟槽210中的部分初始第一填充层212，以使第一填充层211的高度比满足预设范围，剩余的初始第一填充层212作为第一填充层211；其中，高度比为第一填充层211沿垂直于衬底100方向的高度与第一沟槽210深度的比值。
具体地，继续参考图4，在图4所示的实施例中，第一填充层211沿垂直于衬底100方向的高度即为H4，第一沟槽210深度即为H1，高度比即为H4/H1。可以理解的是，若高度比过大，即第一填充层211的高度过高，则在后续去除第一填充层211的步骤中，蚀刻剂无法准确的到达第一填充层211的底部，从而导致第一填充层211不能被全部有效剥离，进而导致第二导电层600与第一导电层110的接触面积减小，接触电阻增大，半导体结构的电学性能下降。若高度比过小，则采用回刻方法形成第一填充层211时的回刻时间较长，容易导致介质层200顶部的损伤，从而造成相邻的第二导电层600之间发生短路。因此，需要选择恰当的高度比，从而获得较好的器件性能。
在其中一个实施例中，第一填充层211的高度比介于0.7与0.9之间，例如第一填充层211的高度比可以为0.8，即第一填充层211沿垂直于衬底100方向的高度与第一沟槽210深度的比值为0.8。采用本实施例高度比范围，可以在对介质层200的顶部的损伤较小的前提下，在步骤S600中实现较好的第一填充层211的去除效果。
在其中一个实施例中，步骤S400包括步骤S410至S420。
S410：在第一沟槽210中和介质层200上形成第一掩膜层300。
图12为一实施例的步骤S410后的半导体结构的剖面示意图，参考图12，第一掩膜层300覆盖第一填充层211的顶部并完全填充第一沟槽210，且第一掩膜层300的顶部高于第二阻挡层500。在其中一个实施例中，第一掩膜层300为光刻胶层，光刻胶层的图形化方法较为简单，而且本实施例中以第一掩膜层300作 为掩膜进行蚀刻的步骤较少，即，采用光刻胶层的第一掩膜层300可以承受蚀刻的过程，而不会对半导体结构造成损伤。
S420：去除第一沟槽210中的全部第一掩膜层300和介质层200上的部分第一掩膜层300。
具体地，以第一掩膜层300为光刻胶层为例，可以通过光罩对第一掩膜层300进行曝光，其中，光罩的图形与待形成的第二沟槽220在衬底100上的投影相同，曝光后对光刻胶层进行显影，从而去除第一沟槽210中的全部第一掩膜层300和介质层200上的部分第一硬掩模层，以形成如图5所示的器件结构。
在其中一个实施例中，步骤S500以第一掩膜层300为掩膜蚀刻介质层200以形成第二沟槽220，包括：以第一掩膜层300为掩膜蚀刻介质层200以形成第二沟槽220，其中，第二沟槽220的深度小于第一沟槽210的深度，且第二沟槽220的底部低于第一填充层211的顶部。当第二沟槽220的底部低于第一填充层211的顶部时，在形成第二沟槽220的过程中，第一填充层211的高度可以对第二沟槽220的刻蚀速率起到调节作用，具体的，第一填充层211占有第一沟槽210的开口空间，使得进入第一沟槽210中的刻蚀离子数量减少，进而降低第二沟槽220的横向刻蚀速率，降低第二沟槽220沿衬底表面方向上的尺寸，防止相邻的第二沟槽220相连。
在其中一个实施例中，第二沟槽220的深度与第一沟槽210的深度的比值介于0.5与0.8之间，即，第二沟槽220的深度与第一沟槽210的深度的比值例如可以为0.5、0.7等。其中，当形成有第二阻挡层500时，第一沟槽210的深度是指第二阻挡层500的顶部与衬底100表面之间的垂直距离，第二沟槽220的深度是指第二阻挡层500的顶部与第二沟槽220的底部之间的垂直距离。参考图8，可以理解的是，由于第二沟槽220的宽度大于第一沟槽210的宽度，所以当导电材料与第二沟槽220对应的介质层200区域接触时，接触面积大于与第一沟槽210对应的介质层200区域接触时的面积，接触面积越大对应的粘附力和稳固性也越强，而若第二沟槽220的深度过大，则会导致衬底100中的第一导电层110暴露，从而影响器件性能。因此，在本实施例中，通过第二沟槽220的深度与第一沟槽210的深度的比值介于0.5与0.8之间，可以在不影响器件性能的前提下，提高导 电材料与介质层200之间的连接强度，从而提高半导体结构的可靠性。
在其中一个实施例中，衬底100包括第一区130和第二区140，第一沟槽210和第二沟槽220均位于第一区130和第二区140中，且第一沟槽210在第一区130中的密度大于第一沟槽210在第二区140中的密度。具体地，图13为一实施例的包括第一区130和第二区140的半导体结构的剖面示意图，参考图13，在本实施例中，第一区130即元件和布线分布较密集的区域，第二区140即元件和布线分布较稀疏的区域，需要说明的是，第一区130和第二区140仅以分布密度进行划分。在本实施例中，通过使第一沟槽210在第一区130中的密度大于第一沟槽210在第二区140中的密度，可以更好地匹配器件结构的布局，从而获取较高的器件的集成度。
在其中一个实施例中，第一填充层211在第一区130中的高度比大于第一填充层211在第二区140中的高度比。具体的，第一区130中的第一沟槽210和第二区140中的第一沟槽210的深度相同，通过调节第一填充层211在第一区130中的高度大于第二区140中的高度，使得第一区130中第二沟槽220的横向刻蚀速率小于第二区140中第二沟槽220的横向刻蚀速率，保证第一区130中后续形成的导电材料不会短路。
在其中一个实施例中，第二区140中的第二沟槽220的深度等于第一区130中的第二沟槽220的深度，使得第二区140中形成的导电材料和第一区130中形成的导电材料的电学性质相同，提高半导体器件的电学性能。优选的，第二区140中的第二沟槽220的宽度等于第一区130中的第二沟槽220的宽度，所述宽度为第二沟槽220沿衬底100表面方向上的尺寸。
在其中一个实施例中，第二区140中的第二沟槽220的深度大于第一区130中的第二沟槽220的深度。图14为现有技术的半导体结构的剖面示意图，参考图14，可以理解的是，在第一区130由于结构的排布密度更高，因此更容易发生介质层200的横向蚀刻问题，并进一步引发第二导电层600的短路现象。参考图13，在本实施例中，通过设置第二区140中的第二沟槽220的深度大于第一区130中的第二沟槽220的深度，可以既保证了第二区140的导电材料的连接强度，又避免了第一区130的导电材料的短路现象，从而提供了一种性能更好的半导体结 构。
一种半导体结构，采用如上述的半导体结构的形成方法形成，参考图9，半导体结构包括：衬底100；介质层200，设置于衬底100上，介质层200中具有第一沟槽210和第二沟槽220，第二沟槽220在垂直方向上暴露第一沟槽210；第二导电层600，由导电材料构成，设置于第一沟槽210和第二沟槽220中。上述半导体结构通过设置比第一沟槽210宽度更大的第二沟槽220，可以使第一沟槽210和第二沟槽220共同用于沉积导电材料，以形成接触性能和结构可靠性更好的第二导电层600。
应该理解的是，虽然图1和图10的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，图1和图10中的至少一部分步骤可以包括多个子步骤或者多个阶段，这些子步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些子步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤的子步骤或者阶段的至少一部分轮流或者交替地执行。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (14)

  1. 一种半导体结构的形成方法，包括：
    提供衬底；
    在所述衬底上形成具有第一沟槽的介质层；
    形成部分填充所述第一沟槽的第一填充层；
    在所述介质层上形成具有第一开口的第一掩膜层，所述第一开口暴露出所述第一填充层以及部分所述介质层；
    以所述第一掩膜层为掩膜蚀刻所述介质层以形成第二沟槽；
    去除所述第一填充层；
    在所述第一沟槽和所述第二沟槽中形成导电材料。
  2. 根据权利要求1所述的半导体结构的形成方法，其中，所述在所述第一沟槽中形成第一填充层，包括：
    在所述第一沟槽中和所述介质层上形成初始第一填充层；
    回刻所述介质层上的全部所述初始第一填充层和所述第一沟槽中的部分所述初始第一填充层，剩余的所述初始第一填充层作为所述第一填充层。
  3. 根据权利要求2所述的半导体结构的形成方法，其中，所述回刻所述介质层上的全部所述初始第一填充层和所述第一沟槽中的部分所述初始第一填充层，剩余的所述初始第一填充层作为所述第一填充层，包括：
    回刻所述介质层上的全部所述初始第一填充层和所述第一沟槽中的部分所述初始第一填充层，以使所述第一填充层的高度比满足预设范围，剩余的所述初始第一填充层作为所述第一填充层；
    其中，所述高度比为所述第一填充层沿垂直于所述衬底方向的高度与所述第一沟槽深度的比值。
  4. 根据权利要求3所述的半导体结构的形成方法，其中，所述衬底包括第一区和第二区，所述第一沟槽和所述第二沟槽均位于所述第一区和所述第二区中，且所述第一沟槽在所述第一区中的密度大于所述第一沟槽在所述第二区中的密度。
  5. 根据权利要求4所述的半导体结构的形成方法，其中，所述第一填充层的高度比介于0.7与0.9之间。
  6. 根据权利要求5所述的半导体结构的形成方法，其中，所述第二沟槽的深度与所述第一沟槽的深度的比值介于0.5与0.8之间。
  7. 根据权利要求4所述的半导体结构的形成方法，其中，所述第二区中的所述第二沟槽的深度大于所述第一区中的所述第二沟槽的深度。
  8. 根据权利要求2所述的半导体结构的形成方法，其中，所述介质层与所述第一填充层的蚀刻选择比大于7。
  9. 根据权利要求1所述的半导体结构的形成方法，其中，所述在所述介质层上形成具有第一开口的第一掩膜层，所述第一开口暴露出所述第一填充层以及部分所述介质层，包括：
    在所述第一沟槽中和所述介质层上形成所述第一掩膜层；
    去除所述第一沟槽中的全部所述第一掩膜层和所述介质层上的部分所述第一掩膜层。
  10. 根据权利要求9所述的半导体结构的形成方法，其中，所述第一掩膜层为光刻胶层。
  11. 根据权利要求1所述的半导体结构的形成方法，其中，所述以所述第一掩膜层为掩膜蚀刻所述介质层以形成第二沟槽，包括：
    以所述第一掩膜层为掩膜蚀刻所述介质层以形成所述第二沟槽，其中，所述第二沟槽的深度小于所述第一沟槽的深度，且所述第二沟槽的底部低于所述第一填充层的顶部。
  12. 根据权利要求4所述的半导体结构的形成方法，其中，所述第一填充层在所述第一区中的高度比大于所述第一填充层在所述第二区中的高度比。
  13. 根据权利要求12所述的半导体结构的形成方法，其中，所述第二区中的所述第二沟槽的深度等于所述第一区中的所述第二沟槽的深度。
  14. 一种半导体结构，采用如权利要求1至13中任一项所述的半导体结 构的形成方法形成。
PCT/CN2021/101436 2020-08-18 2021-06-22 半导体结构及其形成方法 WO2022037243A1 (zh)

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