WO2020238912A1 - 阵列基板及其制造方法、光检测方法及组件、显示装置 - Google Patents

阵列基板及其制造方法、光检测方法及组件、显示装置 Download PDF

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Publication number
WO2020238912A1
WO2020238912A1 PCT/CN2020/092374 CN2020092374W WO2020238912A1 WO 2020238912 A1 WO2020238912 A1 WO 2020238912A1 CN 2020092374 W CN2020092374 W CN 2020092374W WO 2020238912 A1 WO2020238912 A1 WO 2020238912A1
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Prior art keywords
unit
light
electrode
light detection
switch unit
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PCT/CN2020/092374
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English (en)
French (fr)
Inventor
刘清召
王珂
王国强
董水浪
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京东方科技集团股份有限公司
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Priority to US17/256,678 priority Critical patent/US11568673B2/en
Publication of WO2020238912A1 publication Critical patent/WO2020238912A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J1/00—Photometry, e.g. photographic exposure meter
    • G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
    • G01J1/44—Electric circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V10/00—Arrangements for image or video recognition or understanding
    • G06V10/10—Image acquisition
    • G06V10/12—Details of acquisition arrangements; Constructional details thereof
    • G06V10/14—Optical characteristics of the device performing the acquisition or on the illumination arrangements
    • G06V10/141—Control of illumination
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1318—Sensors therefor using electro-optical elements or layers, e.g. electroluminescent sensing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J1/00—Photometry, e.g. photographic exposure meter
    • G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
    • G01J1/44—Electric circuits
    • G01J2001/4446—Type of detector
    • G01J2001/448—Array [CCD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/042—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by opto-electronic means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14678—Contact-type imagers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations

Definitions

  • the application relates to an array substrate, a manufacturing method thereof, a light detection method and components, and a display device.
  • display products integrated with light detection units can detect the ambient light of the environment where the display product is located.
  • the light detection unit can be integrated on the array substrate of the display product.
  • the application provides an array substrate, a manufacturing method thereof, a light detection method and components, and a display device.
  • the technical solution of this application is as follows:
  • an array substrate including:
  • a base substrate having a pixel area
  • the light detection unit, the switch unit, and the light emitting unit are located in the pixel area, and the light detection unit and the light emitting unit share the switch unit.
  • the switch unit is located on a side away from the photosensitive layer of the light detection unit, the switch unit is insulated from the light detection unit, and the orthographic projection of the light detection unit on the base substrate is The orthographic projection of the switch unit on the base substrate at least partially overlap;
  • the switch unit is electrically connected with the light-emitting unit.
  • the orthographic projection of the switch unit on the base substrate covers the orthographic projection of the light detection unit on the base substrate.
  • the light detection unit includes a first electrode, a photosensitive layer, and a second electrode that are sequentially stacked in a direction close to the switch unit;
  • the switch unit includes an active layer, and a control electrode, a first electrode, and a second electrode located on a side of the active layer away from the light detection unit, and the first electrode and the second electrode are One is the source and the other is the drain.
  • the material of the second electrode is a light-shielding material, and the orthographic projection of the second electrode on the base substrate and the orthographic projection of the active layer on the base substrate at least partially overlap.
  • the orthographic projection of the second electrode on the base substrate covers the orthographic projection of the active layer on the base substrate.
  • the light-emitting unit is an electroluminescence unit
  • the first pole of the switch unit is electrically connected to the anode of the light-emitting unit.
  • the array substrate further includes:
  • An insulating layer located between the light detection unit and the switch unit;
  • a flat layer located between the switch unit and the light emitting unit;
  • the pixel defining layer located on the side of the flat layer away from the switch unit, and the light emitting unit is located in the pixel opening defined by the pixel defining layer.
  • the light detection unit, the switch unit, and the light-emitting unit are sequentially distributed along a direction away from the base substrate, and the array substrate further includes:
  • An encapsulation layer located on a side of the light emitting unit away from the base substrate.
  • a light detection method for use in the array substrate of the first aspect or any one of the optional modes of the first aspect.
  • the light detection unit of the array substrate includes a first electrode, a photosensitive layer, and a second electrode , The method includes:
  • a voltage is applied to the first electrode of the light detection unit to make the second electrode of the light detection unit have a potential, wherein, under the action of the light irradiated to the first electrode, the second electrode The potential of the electrode changes, causing the output current of the switch unit to change;
  • the intensity of light irradiated to the first electrode is determined according to the amount of change in the output current of the switch unit.
  • the light irradiated to the first electrode is light reflected by a fingerprint.
  • Fingerprint detection is performed according to the amount of change in the output current of the plurality of switch units.
  • a light detection assembly for use in the array substrate according to the first aspect or any optional manner of the first aspect.
  • the light detection unit of the array substrate includes a first electrode, a photosensitive layer, and a second electrode ,
  • the light detection component includes:
  • a control module for controlling the switch unit to work in an opening transition area, the opening transition area being the area between the opening area and the closing area of the switching unit;
  • the pressure module is used to apply a voltage to the first electrode of the light detection unit so that the second electrode of the light detection unit has a potential, wherein the light irradiated to the first electrode is Next, the potential of the second electrode changes, causing the output current of the switch unit to change;
  • the first determining module is used to determine the amount of change in the output current of the switch unit
  • the second determining module is configured to determine the intensity of light irradiated to the first electrode according to the amount of change in the output current of the switch unit.
  • the light irradiated to the first electrode is light reflected by a fingerprint
  • the light detection component further includes:
  • the detection module is used to perform fingerprint detection according to the variation of the output current of the plurality of switch units.
  • a manufacturing method of an array substrate including:
  • the base substrate having a pixel area
  • a light detection unit, a switch unit, and a light emitting unit are formed in the pixel area, and the light detection unit and the light emitting unit share the switch unit.
  • a light detection unit, a switch unit, and a light emitting unit in the pixel area, and the light detection unit and the light emitting unit share the switch unit, including:
  • a switch unit is formed on the side of the light detection unit away from the photosensitive side of the light detection unit, the switch unit is insulated from the light detection unit, and the orthographic projection of the light detection unit on the base substrate is The orthographic projection of the switch unit on the base substrate at least partially overlap;
  • a light emitting unit is formed on a side of the switch unit away from the light detecting unit, and the light emitting unit is electrically connected to the switch unit.
  • forming a light detection unit in the pixel area includes:
  • a switch unit is formed on the side of the light detection unit away from the photosensitive side of the light detection unit, including:
  • a control electrode, a first electrode and a second electrode are formed on the side of the active layer away from the light detection unit, one of the first electrode and the second electrode is a source electrode, and the other is a drain electrode .
  • the method further includes:
  • a switch unit is formed on the side of the light detection unit away from the photosensitive side of the light detection unit, including:
  • a switch unit is formed on the side of the insulating layer away from the light detection unit.
  • the method further includes:
  • Forming a light-emitting unit on the side of the switch unit away from the light detection unit includes:
  • the method further includes forming a pixel defining layer on a side of the flat layer away from the switch unit, and the light emitting unit is located in a pixel opening defined by the pixel defining layer.
  • the method further includes:
  • An encapsulation layer is formed on the light emitting unit away from the base substrate.
  • a display device which includes the array substrate according to the first aspect or any optional manner of the first aspect.
  • the display device further includes the light detection component of the third aspect or an optional manner of the third aspect.
  • FIG. 1 is a front view of an array substrate provided by an embodiment of the present application
  • FIG. 2 is a cross-sectional view of a part a-a of the array substrate shown in FIG. 1;
  • FIG. 3 is a front view of another array substrate provided by an embodiment of the present application.
  • FIG. 4 is a cross-sectional view of a part a-a of the array substrate shown in FIG. 3;
  • FIG. 5 is a schematic diagram of light detection performed by a light detection unit provided by an embodiment of the present application.
  • FIG. 6 is a curve diagram of illumination time and the potential of the first electrode provided by an embodiment of the present application.
  • FIG. 7 is a graph showing the change of control voltage and output current of a switch unit provided by an embodiment of the present application.
  • FIG. 8 is an equivalent circuit diagram of an array substrate provided by an embodiment of the present application.
  • FIG. 9 is a graph of transfer characteristics of a switch unit provided by an embodiment of the present application.
  • FIG. 10 is a method flowchart of a manufacturing method of an array substrate provided by an embodiment of the present application.
  • FIG. 11 is a method flowchart of another method for manufacturing an array substrate provided by an embodiment of the present application.
  • 12 to 16 are schematic diagrams of a manufacturing process of an array substrate provided by embodiments of the present application.
  • FIG. 17 is a method flowchart of a light detection method provided by an embodiment of the present application.
  • FIG. 18 is a method flowchart of another light detection method provided by an embodiment of the present application.
  • FIG. 19 is a block diagram of a light detection component provided by an embodiment of the present application.
  • FIG. 20 is a block diagram of another light detection component provided by an embodiment of the present application.
  • the light detection unit can be integrated on the array substrate, so that the array substrate can realize the light detection function.
  • the array substrate integrated with the light detection unit can detect the ambient light in the environment where the array substrate is located, and for example, the array substrate integrated with the light detection unit can detect the light emitted by the light-emitting unit of the array substrate.
  • the array substrate integrated with the light detection unit includes: a base substrate and a light-emitting unit, a light detection unit and a thin film transistor (English: Thin Film Transistor; abbreviation: TFT) located on the base substrate.
  • the base substrate has an array arrangement
  • each pixel area is provided with a light-emitting unit, a light detection unit and two TFTs.
  • the two TFTs are distributed in the same layer, and the light-emitting unit and the light detection unit are independently controlled by the two TFTs.
  • such an array substrate has a large number of TFTs, resulting in a complex structure of the array substrate. Moreover, because the two TFTs are distributed in the same layer, the light-emitting unit and the light-detecting unit occupy a relatively low proportion in the pixel area, resulting in low pixel filling rate and detection resolution of the array substrate.
  • FIG. 1 is a front view of an array substrate provided by an embodiment of the present application
  • FIG. 2 is a cross-sectional view of the aa portion of the array substrate shown in FIG. 1.
  • the array The substrate includes: a base substrate 11 having a pixel area P; a light detection unit 12, a switch unit 13 and a light emitting unit 14 located in the pixel area P, and the light detection unit 12 and the light emitting unit 14 share the switch unit 13.
  • the base substrate 11 has a plurality of pixel regions P arranged in an array.
  • each pixel region P is provided with a light detection unit 12, a switch unit 13 and a light emitting unit.
  • the light detecting unit 12 and the light emitting unit 14 in each pixel area P share the switch unit 13 in the pixel area P.
  • the light-emitting unit and the light detection unit share a switch unit, which helps to reduce the number of switch units on the array substrate and simplify the structure of the array substrate. .
  • the light detection unit 12 has a photosensitive side
  • the switch unit 13 is located on the side facing away from the photosensitive side of the light detection unit 12
  • the switch unit 13 is insulated from the light detection unit 12
  • the light detection unit 12 is located on the base substrate 11.
  • the projection and the orthographic projection of the switch unit 13 on the base substrate 11 at least partially overlap, and the switch unit 13 is electrically connected to the light-emitting unit 14.
  • the photosensitive side of the light detection unit 12 is the side of the light detection unit 12 close to the base substrate 11. As shown in FIG. 2, the switch unit 13 is located on the side away from the photosensitive side of the light detection unit 12, that is, The switch unit 13 is located on the side of the light detection unit 12 away from the base substrate 11.
  • the photodetection unit 12 can generate current, and the current generated by the photodetection unit 12 can affect the output current of the switch unit 13.
  • the switch unit 13 works in the turn-on transition zone
  • the current generated by the photodetection unit 12 affects the switch.
  • the influence of the output current of the unit 13 is more obvious. Therefore, the amount of change in the output current of the switch unit 13 when the switch unit 13 is operating in the turn-on transition zone can be used to determine the intensity of the light irradiated to the light detection unit 12 (that is, the light The intensity of the light from the detection unit 12).
  • the switch unit 13 can be controlled to work in the turn-on transition zone, so that the switch unit 13 controls the light detection unit 12 to perform light detection, and since the switch unit 13 is electrically connected to the light-emitting unit 14, the switch unit 13 can control the light-emitting unit 14 emits light, so that the switch unit 13 can control the light detecting unit 12 and the light emitting unit 14 so that the light detecting unit 12 and the light emitting unit 14 share the switch unit 13.
  • the turn-on transition area is the area between the turn-on area and the turn-off area of the switch unit.
  • the area between the turn-on area and the turn-off area of the TFT is the subthreshold swing (English: Subthreshold swing; abbreviation: SS) area.
  • the turn-on transition zone can be an SS zone.
  • the orthographic projection of the light detection unit 12 on the base substrate 11 and the orthographic projection of the switch unit 13 on the base substrate 11 at least partially overlap.
  • the orthographic projection of the switch unit 13 on the base substrate 11 covers the orthographic projection of the light detection unit 12 on the base substrate 11. Since the switch unit 13 is located on the side of the light detection unit 12 away from the base substrate 11, the orthographic projection of the light detection unit 12 on the base substrate 11 and the orthographic projection of the switch unit 13 on the base substrate 11 at least partially overlap, so the switch The unit 13 and the light detection unit 12 are vertically distributed, which helps to reduce the occupied area of the switch unit 13 in the pixel area P and improve the pixel filling rate and detection resolution of the array substrate.
  • vertical distribution refers to distribution along a direction perpendicular to the surface of the base substrate 11. It is easy to understand that when the orthographic projection of the switch unit 13 on the base substrate 11 covers the orthographic projection of the light detection unit 12 on the base substrate 11, it helps to reduce the switch unit 13 in the pixel area P to the greatest extent. Occupy area, improve the pixel filling rate and detection resolution of the array substrate.
  • the light detection unit 12 includes a first electrode 121, a photosensitive layer 122, and a second electrode 123 that are sequentially stacked in a direction close to the switch unit 13;
  • the switch unit 13 includes an active layer 131, and
  • the first pole 133 and the second pole 134 are electrically connected to the active layer 131 respectively.
  • the array substrate determines the intensity of light irradiated to the light detection unit 12 according to the influence of the current generated by the light detection unit 12 on the output current of the switch unit 13 under the irradiation of light, the light detection is performed, and the output current of the switch unit 13 has The source layer 131 is related. If the control electrode 132 is located on the side of the active layer 131 close to the light detection unit 12, the control electrode 132 will shield the active layer 131, resulting in the current generated by the light detection unit 12 to the output current of the switch unit 13 The influence of the light is reduced or even disappeared, and it is difficult to realize light detection.
  • the control electrode 132 since the control electrode 132 is located on the side of the active layer 131 away from the light detection unit 12, it helps to prevent the control electrode 132 from shielding the active layer 131, thereby preventing the current generated by the light detection unit 12 from affecting the switch. The influence of the output current of the unit 13 is reduced or even disappeared, which facilitates the realization of light detection.
  • the light irradiated to the light detection unit 12 may be the light emitted by the light-emitting unit 14 or the light in the environment where the array substrate is located, which is not limited in the embodiment of the present application.
  • the light detection unit 12 may be a photodiode
  • the photosensitive layer 122 may be a PIN layer
  • the switch unit 13 may be a TFT
  • the control electrode 132 may be a gate
  • the first electrode 133 may be a drain
  • the second electrode 134 may be As the source electrode
  • the first electrode 133 and the second electrode 134 can be distributed in the same layer
  • the first electrode 133 and the second electrode 134 can be prepared by the same patterning process. As shown in FIG.
  • the switch unit 13 further includes a gate insulating layer 135 between the active layer 131 and the control electrode 132, and an interlayer dielectric between the control electrode 132 and the first electrode 133 and the second electrode 134
  • Layer 136, the gate insulating layer 135 and the interlayer dielectric layer 136 have connected first connection holes (for example, drain vias) and connected second connection holes (for example, source vias), and the first electrode 133 passes through the layer in turn
  • the first connection hole on the interlayer dielectric layer 135 and the first connection hole on the gate insulating layer 135 are electrically connected to the active layer 131, and the second electrode 134 sequentially passes through the second connection hole on the interlayer dielectric layer 135 and the gate insulating layer
  • the second connection hole on 135 is electrically connected to the active layer 131.
  • the material of the second electrode 123 may be a light-shielding material, and the orthographic projection of the second electrode 123 on the base substrate 11 and the orthographic projection of the active layer 131 on the base substrate 11 at least partially overlap.
  • the orthographic projection of the second electrode 123 on the base substrate 11 covers the orthographic projection of the active layer 131 on the base substrate 11.
  • the LS) layer shields the active layer 131 to prevent light from irradiating the active layer 131 from the side of the base substrate 11 to affect the characteristics of the active layer 131, thereby avoiding the influence of light on the switching characteristics of the switch unit 13.
  • the material of the first electrode 121 may be indium tin oxide (English: Indium tin oxide; abbreviation: ITO), indium zinc oxide (English: Indium zinc oxide; abbreviation: IZO) or aluminum-doped zinc oxide (English: aluminum -doped zinc oxide; abbreviation: ZnO:Al) and other transparent conductive materials
  • the thickness of the first electrode 121 can range from 50nm to 130nm (Chinese: nanometer);
  • the photosensitive layer 122 (such as the PIN layer) can include stacked The P-type semiconductor layer, the intrinsic semiconductor layer and the N-type semiconductor layer.
  • the P-type semiconductor layer may be close to the first electrode 121 or far away from the first electrode 121 relative to the N-type semiconductor layer.
  • the P-type semiconductor layer may be a P-type doped semiconductor layer.
  • the thickness of the P-type semiconductor layer can range from 10nm to 20nm, and the intrinsic semiconductor layer can be a-Si film, which is less than the thickness of the intrinsic semiconductor layer.
  • the value range can be 500nm ⁇ 1000nm
  • the N-type semiconductor layer can be an N-type doped a-Si film layer
  • the thickness of the N-type semiconductor layer can range from 10nm to 20nm, for example, the P-type semiconductor layer is doped There are boron ions, and the N-type semiconductor layer is doped with phosphorus ions
  • the material of the second electrode 123 can be metallic Mg (Chinese: magnesium), metallic Ag (Chinese: silver), metallic Mo (molybdenum), metallic Cu (copper), Metal Al (aluminum), metal Au (gold) and alloy materials thereof
  • the thickness of the second electrode 123 may be in the range of 200 nm to 400 nm.
  • the active layer 131 may be an oxide (English: Oxide) active layer, a-Si active layer, or a p-Si active layer.
  • the oxide active layer may be, for example, indium gallium zinc oxide (English: indium gallium zinc oxide).
  • gate insulating layer 135 can be SiO 2 (Chinese : Silicon dioxide), SiOx (Chinese: silicon oxide), SiNx (Chinese: silicon nitride), Al 2 O 3 (Chinese: alumina) or SiOxNx (Chinese: silicon oxynitride) and other transparent insulating materials, gate insulating layer 135 can be a single-layer or multi-layer structure.
  • the gate insulating layer 135 can be a SiO 2 single-layer structure or a SiN/SiO 2 multilayer structure (that is, a multilayer structure composed of alternately superimposed SiN film layers and SiO 2 film layers). ), the thickness of the gate insulating layer 135 can range from 80 nm to 150 nm; the material of the control electrode 132 can be metal Mo, metal Cu, metal Al, metal Au and their alloy materials, and the thickness of the control electrode 132 can range from It can be 200nm-400nm; the material of the interlayer dielectric layer 136 can be a transparent insulating material such as SiO 2 , SiOx, SiNx, Al 2 O 3 or SiOxNx, and the interlayer dielectric layer 136 can be a single-layer or multilayer structure, for example, a layer The interlayer dielectric layer 136 may be a SiO 2 single-layer structure or a SiN/SiO 2 multilayer structure, and the thickness of the interlayer dielectric layer 136 may be
  • the light-emitting unit 14 may be an electroluminescent unit. As shown in FIG. 1, the light-emitting unit 14 includes an anode 141, an electroluminescent layer 142, and a cathode 143 that are sequentially stacked along a direction away from the base substrate 11. The first pole 133 is electrically connected.
  • the electroluminescent unit can be an organic light-emitting diode (English: Organic Light-Emitting Diode; abbreviation: OLED) unit or a quantum dot light-emitting diode (English: Quantum Dot Light Emitting Diodes; abbreviation: QLED) unit
  • the material of the anode 141 can be It is metal Mg, metal Ag, metal Mo, metal Cu, metal Al, metal Au and their alloy materials
  • the material of the cathode 143 can be conductive materials such as ITO, IZO or metal Ag, for example, the cathode 143 is ITO/Ag/ITO Multi-layer structure, wherein the thickness of the ITO film layer is 8 nm, and the thickness of the Ag film layer is 100 nm.
  • the electroluminescence unit includes two electrodes and an electroluminescence layer sandwiched between the two electrodes.
  • the two electrodes include an anode 141 and a cathode 143, and are connected to the switch unit.
  • the electrode electrically connected to the first pole 133 of the switch unit 13 is the anode
  • the electrode that is not electrically connected to the switch unit 13 is the cathode.
  • the cathode may be an electrode electrically connected to the first pole 133 of the switch unit 13 in practical applications.
  • the anode may be an electrode that is not electrically connected to the switch unit 13, and in different scenarios, the names of the above two electrodes may also be other names.
  • the light-emitting unit 14 shown in FIGS. 1 and 2 is only exemplary. In practical applications, the light-emitting unit 14 may also include a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. The application embodiments are not repeated here.
  • the array substrate further includes a plurality of gate lines 19 and a plurality of data lines 20, the plurality of gate lines 19 and the plurality of data lines 20 are insulated and crossed to define a plurality of pixel regions P, and a switch unit 13
  • the control electrode 132 (for example, the gate) of the switch unit 13 may be electrically connected to the gate line 19
  • the second electrode 134 for example, the source
  • the gate line 19 is used to apply a control voltage to the control electrode 132.
  • the data line 20 is used to apply a data voltage to the second electrode 134.
  • the gate line 19 and the control electrode 132 can be distributed in the same layer, and the gate line 19 and the control electrode 132 can be prepared by the same patterning process.
  • the data line 20 and the second electrode 134 are distributed in the same layer, and the data line 20 and the The diode 134 can be prepared by the same patterning process.
  • the array substrate further includes an insulating layer 15 located between the light detection unit 12 and the switch unit 13; a flat layer 16 located between the switch unit 13 and the light emitting unit 14; and
  • the pixel defining layer 17 on the side of the layer 16 away from the switch unit 13 defines the pixel opening K.
  • the orthographic projection of the pixel opening K on the base substrate 11 is located in the pixel area P, and the light emitting unit 14 is located on the pixel defining layer 17 defined in the pixel opening K.
  • the insulating layer 15 may include a superimposed organic insulating layer and an inorganic insulating layer, the material of the organic insulating layer may be resin, and the difference between the thickness of the organic insulating layer and the thickness of the light detecting unit 12 may range from 1.2 ⁇ m to 3 ⁇ m (Chinese : Micrometers), the inorganic insulating layer can be a single layer or a multilayer structure, for example, the inorganic insulating layer can be a SiO 2 single layer structure or a SiN/SiO 2 multilayer structure; the material of the flat layer 16 can be resin, and the thickness of the flat layer 16 The value range of is 2 ⁇ m to 3 ⁇ m; the material of the pixel defining layer 17 may be a resin with strong liquid repellency (for example, hydrophobicity).
  • the electroluminescent layer 142 is usually formed by inkjet printing process or solution process, and the pixel defining layer
  • the material of 17 is a resin with strong lyophobicity, which can facilitate printing of the solution in the pixel opening K, so that the pixel defining layer 17 can define the light emitting unit 14 in the pixel opening K.
  • FIG. 4 is a front view of another array substrate provided by an embodiment of the present application, and FIG. 4 is a cross-sectional view of the aa portion of the array substrate shown in FIG. 2, see FIG. 4, in FIG.
  • the array substrate further includes an encapsulation layer 18, which is located on the side of the light-emitting unit 14 away from the base substrate 11.
  • the encapsulation layer 18 covers the light-emitting unit 14 and the pixel defining layer 17, and the encapsulation layer 18 is used to package the array The light-emitting unit 14 of the substrate.
  • the encapsulation layer 18 may be a thin film encapsulation (English: Thin Film Encapsulation; TFE for short) layer or an encapsulation cover plate.
  • the TFE layer may include an inorganic layer and an organic layer alternately superimposed, and the material of the inorganic layer may be SiO 2 , Transparent insulating materials such as SiOx, SiNx, Al 2 O 3 or SiOxNx, the material of the organic layer may be organic resin, and the packaging cover plate may be a cover plate made of materials such as glass, which is not limited in the embodiment of the application.
  • the array substrate provided by the embodiment of the application may be a bottom emission array substrate or a top emission array substrate.
  • the switch unit and the light emitting unit are distributed in a direction away from the base substrate, in the bottom emission array substrate, the switch unit is on the base substrate There is no overlapping area between the orthographic projection and the orthographic projection of the light-emitting unit on the base substrate to prevent the switch unit from blocking the light emitted by the light-emitting unit and affect the light output rate of the array substrate.
  • the top-emitting array substrate even if the switch unit is on the substrate There is an overlap area between the orthographic projection on the base substrate and the orthographic projection of the light-emitting unit on the base substrate, and the switch unit will not block the light emitted by the light-emitting unit, thereby not affecting the light output rate of the array substrate.
  • the top emission array substrate has a higher aperture ratio.
  • the bottom emission array substrate may be as shown in FIGS. 1 and 2
  • the top emission array substrate may be as shown in FIGS. 3 and 4.
  • both the bottom emission array substrate and the top emission array substrate may include an encapsulation layer.
  • the array substrate may also include a pixel circuit and a protective layer on the sidewall of the photosensitive layer.
  • the material of the protective layer may be SiO (Chinese: silicon oxide), SiN (Chinese: silicon nitride),
  • the thickness of the protective layer may range from 50 nm to 150 nm, which will not be repeated in the embodiment of the present application.
  • the light detection unit 12 may perform light detection under the control of the switch unit 13.
  • the principle of light detection by the light detection unit 12 will be described below with reference to FIGS. 1 to 4.
  • the light detection unit 12 is a photodiode with a PIN layer (that is, the photosensitive layer 122).
  • the light detection unit 12 can also be called a PIN junction photodiode.
  • the light detection unit 12 is very sensitive to light and can accurately sense light. Signal, and based on the photovoltaic effect (English: photovoltaic effect) to convert the optical signal into an electrical signal.
  • the first electrode 121 is used to sense light signals, so the first electrode 121 can be referred to as a photosensitive electrode (or called a photosensitive surface, a photosensitive surface, etc.) of the light detection unit 12.
  • FIG. 5 shows a principle diagram of a light detection unit 12 for light detection provided by an embodiment of the present application. In FIG.
  • the P area corresponds to the P-type semiconductor layer of the light detection unit 12
  • the I area corresponds to the light
  • the N region corresponds to the N-type semiconductor layer of the light detection unit 12.
  • the working principle of the light detection unit 12 is: when light irradiates the first electrode 121, the energy of the light will make P The electrons in the zone and the electrons in the N zone undergo transitions to produce electron-hole pairs. Under the action of the internal electric field in the I zone, the electrons (energy hv) move to the positively charged N zone and accumulate in the N zone.
  • FIG. 6 shows a curve diagram of the illumination time t and the electric potential U1 of the first electrode 121 when the light is irradiated to the first electrode 121
  • the curve Q1 represents that the light with a wavelength of 600 nm is irradiated to the first electrode 121
  • the curve Q2 represents the relationship between the illumination time t and the potential U1 of the first electrode 121 when the light with a wavelength of 800 nanometers is irradiated to the first electrode 121
  • the curve Q3 represents the relationship between the illumination time t and the potential U1 of the first electrode 121 when light with a wavelength of 900 nm is irradiated to the first electrode 121
  • the curve Q4 represents the light time when the light with a wavelength of 1200 nm is irradiated to the first electrode 121 The relationship between t and the potential U1 of the first electrode 121.
  • the curve Q5 shows the relationship between the illumination time t and the potential U1 of the first electrode 121 when white light is irradiated to the first electrode 121. See FIG. When light is irradiated to the first electrode 121, the electric potential U1 generated by the first electrode 121 is different.
  • Illumination can cause the potential of the first electrode 121 and the second electrode 123 (that is, the LS layer) to change, and the change of the potential of the second electrode 123 can cause the control voltage of the switch unit 13 (that is, the voltage of the control electrode 132, For example, the gate voltage) Vg changes, and the control voltage Vg of the switch unit 13 changes, which can cause the output current Id of the switch unit 13 to change. Therefore, according to the change in the output current Id of the switch unit 13 caused by light, the irradiation to the first The light intensity of an electrode 121 (that is, the intensity of light irradiated to the first electrode 121), thereby realizing light detection. Please refer to FIG.
  • U2 represents the potential of the second electrode 123, each curve corresponds to a U2, U2 increases in the direction indicated by the arrow, It can be seen that the curves corresponding to different U2 are different, so the potential of the second electrode 123 has a significant effect on the threshold voltage Vth of the switch unit 13.
  • FIG. 8 shows an equivalent circuit diagram of an array substrate provided by an embodiment of the present application.
  • bias represents the first electrode 121 of the light detection unit 12
  • LS represents the second electrode of the light detection unit 12.
  • the electrode 123, the control electrode (for example, gate, English: Gate) of the switch unit 13 is electrically connected to the gate line (not shown in FIG. 8) in the array substrate, and the second electrode S (for example, the source) of the switch unit 13 is connected to
  • the data line (not shown in FIG. 8) in the array substrate is electrically connected, and the first pole D (for example, the drain) of the switch unit 13 is electrically connected to the light emitting unit 14.
  • the first pole D of the switch unit 13 is also connected to The light detection component outside the array substrate is electrically connected.
  • the light detection component may be a chip or a functional component in the chip, and the chip may be an integrated circuit chip.
  • FIG. 9 shows a transfer characteristic curve diagram of a switch unit 13 provided by an embodiment of the present application.
  • the switch unit 13 taking the switch unit 13 as a TFT as an example, the turn-on transition region of the switch unit 13 is also SS
  • the photo-generated bias generated by the light detection unit 12 has little effect on the switch unit 13. Therefore, the change in the output current Id of the switch unit 13 is usually small.
  • the switch unit 13 When the switch unit 13 is working in the OFF region or the ON region, the change in the output current Id of the switch unit 13 caused by the light irradiated to the first electrode 121 of the light detection unit 12 is usually difficult to measure, and when the switch When the unit 13 is working in the SS area, the change in the output current Id of the switch unit 13 caused by the light irradiated to the first electrode 121 of the light detection unit 12 is easy to measure, so it can be irradiated to The amount of change in the output current Id of the switch unit 13 caused by the light of the first electrode 121 of the light detection unit 12 determines the light intensity irradiated to the first electrode 121 of the light detection unit 12, that is, the switch unit 13 can be controlled to work at In the SS area, the switch unit 13 is used to control the light detection unit 13 for light detection.
  • the process of determining the light intensity according to the change in the output current Id of the switch unit 13 caused by the light irradiated to the first electrode 121 of the light detection unit 12 can be performed by the light detection component in FIG. 8. 8 and 9, in the embodiment of the present application, when the switch unit 13 is working in the ON zone, the switch unit 13 is in the on state, and the switch unit 13 controls the light-emitting unit 14 to emit light. When the switch unit 13 is working in the OFF zone, The switch unit 13 is in the off state. When the switch unit 13 is working in the SS area, the switch unit 13 is between the on state and the off state, and the switch unit 13 controls the light detection unit 13 to perform light detection.
  • the process of the switch unit 13 controlling the light detection unit 12 to perform light detection may include: first, applying a positive voltage to the first electrode 121 (that is, bias) of the light detection unit 12 to make the PIN layer (that is, the photosensitive layer 122) positively biased , Remove the residual charge in the PIN layer (the PIN layer is equivalent to a wire when the PIN layer is positively biased, so the charge stored in the PIN layer is derived); then, the control voltage Vg is applied to the switch unit 13 to make the switch unit 13 work in the SS area, and the detection The first electrode 121 of the unit 12 applies a negative voltage to reverse bias the PIN layer.
  • the PIN layer When the PIN layer is reverse biased, it is equivalent to a capacitor and can store charges; when light is irradiated to the first electrode 121, the PIN layer stores charges and generates a bias voltage (can be With reference to the working principle of the light detection unit 12 above), the potential of the second electrode 123 is changed, which causes the threshold voltage Vth of the switch unit 13 to drift. The threshold voltage Vth of the switch unit 13 drifts while the control voltage Vg of the switch unit 13 does not change.
  • the output current Id of the switch unit 13 will change in the SS area, and the amount of change in the output current Id of the switch unit 13 before and after illumination can be determined, and the illumination can be determined according to the amount of change in the output current Id of the switch unit 13 before and after illumination.
  • the light intensity to the first electrode 121 Experiments have proved that the signal intensity detected by the array substrate provided by the embodiments of the application is 2 to 3 orders of magnitude, or even 4 orders of magnitude greater than the signal intensity detected by the traditional array substrate. Therefore, the array substrate provided by the embodiments of the present application is beneficial to implementation. High-resolution detection.
  • the process of the switch unit 13 controlling the light emitting unit 14 to emit light may include: applying a control voltage Vg to the switch unit 13 to make the switch unit 13 work in the ON region, and applying a positive voltage to the first electrode 121 of the detection unit 12 to make the PIN layer forward bias. , The switch unit 13 controls the light-emitting unit 14 to turn on so that the light-emitting unit 14 emits light.
  • the pressure difference generated by the PIN layer has little or no influence on the output current of the switch unit 13, so when the switch unit 13 is working in the ON zone, the photo-generated bias of the PIN layer is not It will affect the light-emitting effect of the light-emitting unit 14 and will not affect the display effect of the array substrate. Therefore, the light detecting unit 12 and the light-emitting unit 14 can share the switch unit 13.
  • the light-emitting unit and the light detection unit share a switch unit, which helps to reduce the number of switch units on the array substrate and simplify the structure of the array substrate. .
  • FIG. 10 shows a method flowchart of a manufacturing method of an array substrate provided by an embodiment of the present application.
  • the manufacturing method of the array substrate can be used to manufacture the array substrate shown in FIG. 1 or FIG. 4, see FIG. 10.
  • the method may include the following steps:
  • step 101 a base substrate is provided, and the base substrate has a pixel area.
  • step 102 a light detection unit, a switch unit, and a light emitting unit are formed in the pixel area, and the light detection unit and the light emitting unit share the switch unit.
  • the light-emitting unit and the light detection unit share one switch unit in the pixel area, it helps to reduce the number of switch units on the array substrate and simplify the array.
  • the structure of the substrate since the light-emitting unit and the light detection unit share one switch unit in the pixel area, it helps to reduce the number of switch units on the array substrate and simplify the array.
  • step 102 includes:
  • a switch unit is formed on the side of the light detection unit away from the photosensitive side of the light detection unit.
  • the switch unit is insulated from the light detection unit.
  • the orthographic projection of the light detection unit on the base substrate and the orthographic projection of the switch unit on the base substrate are at least Partly overlap
  • a light emitting unit is formed on the side of the switch unit away from the light detecting unit, and the light emitting unit is electrically connected to the switch unit.
  • forming a light detection unit in the pixel area includes:
  • a switch unit is formed on the side of the light detection unit away from the photosensitive side of the light detection unit, including:
  • a control electrode, a first electrode and a second electrode are formed on the side of the active layer away from the light detection unit.
  • the material of the second electrode is a light-shielding material, and the orthographic projection of the second electrode on the base substrate and the orthographic projection of the active layer on the base substrate at least partially overlap.
  • the orthographic projection of the second electrode on the base substrate covers the orthographic projection of the active layer on the base substrate.
  • the method further includes:
  • a switch unit on the side of the light detecting unit away from the photosensitive side of the light detecting unit including:
  • a switch unit is formed on the side of the insulating layer away from the light detection unit.
  • the method further includes:
  • forming the light emitting unit on the side of the switch unit away from the light detecting unit includes:
  • the method further includes: a pixel defining layer on a side of the flat layer away from the switching unit, and the light emitting unit is located in the pixel opening defined by the pixel defining layer.
  • the method further includes: forming an encapsulation layer on a side of the light-emitting unit away from the flat layer.
  • FIG. 11 shows a method flowchart of another method for manufacturing an array substrate provided by an embodiment of the present application.
  • the method for manufacturing an array substrate can be used to manufacture the array substrate shown in FIG. 1 or FIG.
  • the application embodiment takes the manufacture of the array substrate shown in FIG. 3 as an example for description. Referring to Figure 11, the method may include the following steps:
  • step 201 a base substrate is provided, and the base substrate has a pixel area.
  • the base substrate may be a transparent substrate.
  • the base substrate may be a rigid substrate made of glass, quartz or transparent resin with a certain degree of robustness and non-metallic materials;
  • a flexible substrate made of flexible materials such as polyimide (English: Polyimide; PI).
  • step 202 a light detection unit is formed in the pixel area.
  • FIG. 12 shows a schematic diagram of a photodetection unit 12 formed on a base substrate 11 provided by an embodiment of the present application.
  • the photodetection unit 12 includes a first layer stacked in a direction away from the base substrate 11.
  • the photosensitive layer 122 may be a PIN layer, including a P-type semiconductor layer, an intrinsic semiconductor layer, and an N-type semiconductor layer stacked in sequence.
  • the P-type semiconductor layer can be compared to the N-type semiconductor layer. It is close to the first electrode 121 and can also be far away from the first electrode 121.
  • the P-type semiconductor layer may be a P-type doped a-Si film layer
  • the thickness of the P-type semiconductor layer may range from 10 nm to 20 nm
  • the intrinsic semiconductor layer may be an a-Si film layer.
  • the thickness of the layer may range from 500 nm to 1000 nm
  • the N-type semiconductor layer may be an N-type doped a-Si film layer, and the thickness of the N-type semiconductor layer may range from 10 nm to 20 nm
  • the first electrode 121 The material of can be transparent conductive materials such as ITO, IZO or ZnO:Al, the thickness of the first electrode 121 can range from 50nm to 130nm
  • the material of the second electrode 123 is a light-shielding material, for example, the material of the second electrode 123 is For metal Mo, metal Cu, metal Al, metal Au, and alloy materials thereof, the thickness of the second electrode 123 may range from 200 nm to 400 nm.
  • forming the light detection unit 12 in the pixel area may include the following three steps:
  • Step (1) by magnetron sputtering, thermal evaporation or plasma enhanced chemical vapor deposition (English: Plasma Enhanced Chemical Vapor Deposition; abbreviation: PECVD) and other processes to form a thickness on the base substrate 11
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • the ITO material layer is processed through a patterning process to obtain the first electrode 121, and the first electrode 121 is located in the pixel area of the base substrate 11.
  • Step (2) on the side of the first electrode 121 away from the base substrate 11, a P-type semiconductor material layer with a thickness of between 10nm and 20nm, an intrinsic semiconductor material layer with a thickness of between 500nm and 1000nm and a thickness of
  • the P-type semiconductor material layer, the intrinsic semiconductor material layer and the N-type semiconductor material layer are processed through a patterning process to obtain the P-type semiconductor material layer sequentially superimposed with the first electrode 121
  • forming the P-type semiconductor material layer may include: first depositing an intrinsic semiconductor material through a PECVD process to form an intrinsic semiconductor material layer, and then performing P-type doping on the intrinsic semiconductor material layer to obtain a P-type semiconductor material layer; The semiconductor material is P-type doped to obtain a P-type semiconductor material, and then the P-type semiconductor material is deposited through a PECVD process to obtain a P-type semiconductor material layer.
  • the formation process of the N-type semiconductor material layer is similar to this, and will not be repeated here. It is easy for those skilled in the art to understand that the embodiment of the present application takes the simultaneous formation of a P-type semiconductor layer, an intrinsic semiconductor layer and an N-type semiconductor layer as an example.
  • a semiconductor material layer for example, a P-type semiconductor layer
  • the semiconductor material layer is processed to obtain a corresponding semiconductor layer (for example, a P-type semiconductor layer), which is not limited in the embodiment of the present application.
  • Step (3) forming a metallic Mo material layer with a thickness between 200 nm and 400 nm on the side of the photosensitive layer 122 away from the base substrate 11 by any of the magnetron sputtering, thermal evaporation or PECVD processes, and pass it once The patterning process processes the metallic Mo material layer to obtain the second electrode 123 superimposed on the photosensitive layer 122.
  • step 203 an insulating layer is formed on the side of the light detecting unit away from the photosensitive side of the light detecting unit.
  • FIG. 13 shows a schematic diagram of an insulating layer 15 formed on the side of the light detecting unit 12 away from the photosensitive side of the light detecting unit 12 according to an embodiment of the present application, and the insulating layer 15 covers the light detecting unit 12 ,
  • the side of the insulating layer 15 away from the light detecting unit 12 is a flat surface.
  • the side of the light detecting unit 12 away from the photosensitive side of the light detecting unit 12 is the side of the light detecting unit 12 away from the base substrate 11.
  • the insulating layer 15 may include a superimposed organic insulating layer and an inorganic insulating layer, the material of the organic insulating layer may be resin, the thickness of the organic insulating layer and the thickness of the light detecting unit 12 may differ from 1.2 ⁇ m to 3 ⁇ m, and the inorganic insulating layer may It has a single-layer or multi-layer structure.
  • the inorganic insulating layer may have a SiO 2 single-layer structure or a SiN/SiO 2 multi-layer structure.
  • forming the insulating layer 15 on the side of the light detecting unit 12 away from the photosensitive side of the light detecting unit 12 may include the following two steps:
  • Step (1) Deposit a layer of resin as an organic insulating layer on the side of the photodetecting unit 12 away from the photosensitive side of the photodetecting unit 12 by any of magnetron sputtering, thermal evaporation, or PECVD. The layer covers the light detection unit 12.
  • Step (2) First, form a SiN layer on the side of the organic insulating layer away from the light detection unit 12 by any of magnetron sputtering, thermal evaporation, or PECVD, and then use magnetron sputtering, thermal evaporation, or PECVD In any of the other processes, an SiO 2 layer is formed on the side of the SiN layer away from the SiN layer, and the SiN layer and the SiO 2 layer are superimposed to form an inorganic insulating layer.
  • a superimposed organic insulating layer and an inorganic insulating layer can be obtained, and the superimposed organic insulating layer and the inorganic insulating layer constitute the insulating layer 15.
  • a switch unit is formed on the side of the insulating layer away from the light detection unit, and the orthographic projection of the switch unit on the base substrate and the orthographic projection of the light detection unit on the base substrate at least partially overlap.
  • FIG. 14 shows a schematic diagram of a switch unit 13 formed on the side of the insulating layer 15 away from the light detection unit 12 according to an embodiment of the present application.
  • the orthographic projection of the switch unit 13 on the base substrate 11 The orthographic projection of the light detection unit 12 on the base substrate 11 at least partially overlaps.
  • the orthographic projection of the switch unit 13 on the base substrate 11 covers the orthographic projection of the light detection unit 12 on the base substrate 11.
  • the switch unit 13 includes an active layer 131, and a control electrode 132, a first electrode 133 and a second electrode 134 located on the side of the active layer 131 away from the light detection unit 12, the first electrode 133 and the second electrode 134.
  • the two poles 134 are distributed in the same layer, the first pole 133 and the second pole 134 can be prepared by the same patterning process, and the first pole 133 and the second pole 134 are electrically connected to the active layer 131 respectively.
  • the switch unit 13 may be a TFT.
  • the switch unit 13 further includes a gate insulating layer 135 located between the active layer 131 and the control electrode 132, and located between the control electrode 132 and the first electrode.
  • the interlayer dielectric layer 136 between the 133 and the second electrode 134, the gate insulating layer 135 and the interlayer dielectric layer 136 have a connected first connection hole and a connected second connection hole, and the first electrode 133 (such as a drain) It is electrically connected to the active layer 131 through the first connection hole on the interlayer dielectric layer 136 and the first connection hole on the gate insulating layer 135 in turn, and the second electrode 134 (for example, the source electrode) sequentially passes through the first connection hole on the interlayer dielectric layer 136.
  • the second connection hole and the second connection hole on the gate insulating layer 135 are electrically connected to the active layer 131, and the orthographic projection of the second electrode 123 on the base substrate 11 covers the orthographic projection of the active layer 131 on the base substrate 11 .
  • the active layer 131 may be an Oxide active layer, a-Si active layer or p-Si active layer.
  • the Oxide active layer is for example an IGZO active layer or an ITZO active layer.
  • the material of the gate insulating layer 135 can be a transparent insulating material such as SiO 2 , SiOx, SiNx, Al 2 O 3 or SiOxNx, and the gate insulating layer 135 can be a single Layer or multilayer structure, the thickness of the gate insulating layer 135 can range from 80nm to 150nm;
  • the material of the control electrode 132 can be metal Mo, metal Cu, metal Al, metal Au and its alloy materials, and the thickness of the control electrode 132 The value range of can be 200nm ⁇ 400nm;
  • the material of the interlayer dielectric layer 136 can be transparent insulating materials such as SiO 2 , SiOx, SiNx, Al 2 O 3 or SiOxNx, and the interlayer dielectric layer 136 can be a single-layer or multi-layer structure
  • the thickness of the interlayer dielectric layer 136 can range from 80 nm to 150 nm; the material of the first
  • forming the switch unit 13 on the side of the insulating layer 15 away from the light detection unit 12 may include the following six steps:
  • Step (1) forming an IGZO material layer on the side of the insulating layer 15 away from the light detection unit 12 by any of magnetron sputtering, thermal evaporation or PECVD processes, and processing the IGZO material layer through a patterning process.
  • the active layer 131 is used for connecting the first electrode and the second electrode on the active layer 131 through any of doping (English: doping), plasma (English: plasma) treatment, or atmosphere annealing, etc. Conduction treatment is performed on the part to increase the carrier concentration of the part and ensure that the part and the corresponding electrode (for example, the first electrode or the second electrode) achieve ohmic contact.
  • Step (2) forming a SiO 2 layer with a thickness between 80 nm and 150 nm on the side of the active layer 131 away from the light detection unit 12 as gate insulation by any of magnetron sputtering, thermal evaporation, or PECVD processes ⁇ 135.
  • Step (3) forming a metal Mo material layer with a thickness between 200 nm and 400 nm on the side of the gate insulating layer 135 away from the light detection unit 12 by any of the magnetron sputtering, thermal evaporation or PECVD processes, and pass The metal Mo material layer is processed by one patterning process to obtain the control electrode 132.
  • an interlayer dielectric layer 136 is formed on the side of the control electrode 132 away from the light detection unit 12.
  • the formation process of the interlayer dielectric layer 136 can refer to the formation process of the gate insulating layer 135.
  • Step (5) processing the interlayer dielectric layer 136 and the gate insulating layer 135 through a patterning process to form a connected first connecting hole and a connected second connecting hole on the interlayer dielectric layer 136 and the gate insulating layer 135
  • the part of the active layer 131 for connecting with the first electrode (for example, the drain) is exposed through the first connection hole
  • the part for connecting with the second electrode (for example, the source) is exposed through the second connecting hole.
  • Step (6) forming a metallic Mo material layer with a thickness between 200 nm and 400 nm on the side of the interlayer dielectric layer 136 away from the light detection unit 12 by any of magnetron sputtering, thermal evaporation or PECVD processes,
  • the first electrode 133 and the second electrode 134 are obtained by processing the metal Mo material layer through a patterning process.
  • the first electrode 133 sequentially passes through the first connection hole on the interlayer dielectric layer 136 and the first connection hole on the gate insulating layer 135
  • the second electrode 134 is electrically connected to the active layer 131, and the second electrode 134 is electrically connected to the active layer 131 through the second connection hole on the interlayer dielectric layer 136 and the second connection hole on the gate insulating layer 135 in turn.
  • step 205 a flat layer is formed on the side of the switch unit away from the insulating layer.
  • FIG. 15 shows a schematic diagram of a flat layer 16 formed on the side of the switch unit 13 away from the insulating layer 15 provided by an embodiment of the present application.
  • the side of the flat layer 16 away from the switch unit 13 is a flat surface.
  • 16 has an anode via G through which the first pole 133 of the switch unit 13 is exposed.
  • the material of the flat layer 16 may be resin.
  • a resin layer with a thickness between 2 ⁇ m and 3 ⁇ m is formed as the flat layer 16 on the side of the switch unit 13 away from the insulating layer 15 by any of magnetron sputtering, thermal evaporation, or PECVD.
  • a light emitting unit and a pixel defining layer are formed on the side of the flat layer away from the switch unit, the light emitting unit is located in the pixel opening defined by the pixel defining layer, the light emitting unit is electrically connected to the switch unit, and the light emitting unit and the light detection unit share a switch unit.
  • FIG. 16 shows a schematic diagram of the light emitting unit 14 and the pixel defining layer 17 formed on the side of the flat layer 16 away from the switch unit 13 provided by the embodiment of the present application.
  • the light emitting unit 14 is located on the pixel defining layer 17 In the pixel opening K, the light-emitting unit 14 includes an anode 141, an electroluminescent layer 142, and a cathode 143 stacked in a direction away from the base substrate 11.
  • the anode 141 passes through the anode via G and the first electrode 133 on the flat layer 16 Electric connection.
  • the material of the anode 141 can be metal Mg, metal Ag, metal Mo, metal Cu, metal Al, metal Au and alloy materials thereof
  • the material of the electroluminescent layer 142 can be electroluminescent material
  • the material of the cathode 143 can be Conductive materials such as ITO, IZO, and metal Ag.
  • the cathode 143 is a multilayer structure of ITO/Ag/ITO, wherein the thickness of the ITO film is 8nm, the thickness of the Ag film is 100nm, and the material of the pixel defining layer 17 can be A resin with strong liquid repellency.
  • forming the light-emitting unit 14 and the pixel defining layer 17 on the side of the flat layer 16 away from the switch unit 13 may include the following four steps:
  • Step (1) by any one of magnetron sputtering, thermal evaporation or PECVD and other processes, deposit a layer of magnesium-silver alloy on the side of the flat layer 16 away from the switch unit 13 to obtain an alloy material layer.
  • the alloy material layer is processed to obtain the anode 141, and the anode 141 is electrically connected to the first electrode 133 through the anode via G.
  • Step (2) deposit a layer of resin on the side of the anode 141 away from the first electrode 133 by any one of magnetron sputtering, thermal evaporation or PECVD processes to obtain a resin material layer, and use a patterning process to the resin material
  • the layer is processed to obtain the pixel defining layer 17, the side surface of the anode 141 is located in the pixel defining layer 17, and the upper surface of the anode 141 is partially exposed through the pixel opening K.
  • Step (3) A layer of electroluminescent material is formed and printed in the pixel opening K through an inkjet printing process, and the printed electroluminescent material is dried to obtain the electroluminescent layer 142.
  • Step (4) forming an ITO material layer, an Ag material layer and an ITO material layer sequentially superimposed on the side of the electroluminescent layer 142 away from the anode 141 by any of magnetron sputtering, thermal evaporation or PECVD processes,
  • the thickness of the ITO material layer may be 8 nm, and the thickness of the Ag material layer may be 100 nm.
  • the cathode 143 is obtained by processing the ITO material layer, the Ag material layer and the ITO material layer through a patterning process.
  • step 207 an encapsulation layer is formed on the side of the light-emitting unit away from the flat layer.
  • the encapsulation layer 18 covers the light emitting unit 14 and the pixel defining layer 17.
  • the encapsulation layer 18 can be a TFE layer or a encapsulation cover plate.
  • the TFE layer includes an inorganic layer and an organic layer alternately superimposed.
  • the material of the inorganic layer can be a transparent insulating material such as SiO 2 , SiOx, SiNx, Al 2 O 3 or SiOxNx.
  • the organic layer The material of can be organic resin, and the package cover can be a cover made of glass and other materials.
  • forming the packaging layer 18 on the side of the light-emitting unit 14 away from the flat layer 16 may include: any one of magnetron sputtering, thermal evaporation or PECVD processes A layer of SiOx is deposited on the side of the unit 14 away from the flat layer 16 to obtain a SiOx material layer, and the SiOx material layer is processed through a patterning process to obtain an inorganic layer; a inkjet printing process is used to print a layer of the inorganic layer away from the flat layer 16 Layer an organic resin, and dry the printed organic resin to obtain an organic layer, thereby obtaining an encapsulation layer.
  • the one patterning process involved in the embodiments of this application includes photoresist coating, exposure, development, etching and photoresist stripping.
  • the processing of the material layer (such as ITO material layer) through one patterning process includes: in the material layer ( For example, ITO material layer) is coated with a layer of photoresist to form a photoresist layer, and a mask is used to expose the photoresist layer so that the photoresist layer forms a fully exposed area and a non-exposed area, and then uses a development process to process , The photoresist in the fully exposed area is completely removed, and the photoresist in the non-exposed area is all retained.
  • the etching process is used to etch the area corresponding to the fully exposed area on the material layer (such as ITO material layer), and finally the non-exposed area is stripped
  • the photoresist in the exposed area has a corresponding structure (for example, the first electrode 121).
  • the photoresist is a positive photoresist as an example.
  • the process of one patterning process can refer to the description in this paragraph, and the embodiments of this application will not be omitted here. Repeat.
  • the manufacturing method of the array substrate since the light-emitting unit and the light detection unit share one switch unit in the pixel area, it helps to reduce the number of switch units on the array substrate and simplify the array.
  • the structure of the substrate In the manufacturing method of the array substrate provided by the embodiment of the present application, since the light detection unit is manufactured first and then the switch unit is manufactured, the influence of the process of manufacturing the light detection unit on the active layer of the switch unit can be avoided.
  • FIG. 17 shows a method flow chart of a photodetection method provided by an embodiment of the present application.
  • the photodetection method can be used in the array substrate provided by the above embodiment, and each pixel area of the array substrate is provided There are a light detection unit, a switch unit and a light emitting unit, and the light detection unit in each pixel area shares the switch unit in the pixel area with the light emitting unit in the pixel area.
  • the light detection unit includes a first electrode, a photosensitive layer and a second electrode, and the light detection method can be executed by a light detection component. Referring to Figure 17, the method may include the following steps:
  • step 301 the switch unit is controlled to work in the opening transition zone, which is the area between the opening zone and the closing zone of the switching unit.
  • step 302 a voltage is applied to the first electrode of the photodetection unit to make the second electrode of the photodetection unit have a potential. Under the action of the light irradiated to the first electrode, the potential of the second electrode changes, causing the switch The output current of the unit changes.
  • step 303 the amount of change in the output current of the switching unit is determined.
  • step 304 the intensity of light irradiated to the first electrode is determined according to the amount of change in the output current of the switch unit.
  • the method further includes: performing fingerprint detection according to changes in the output currents of the multiple switch units.
  • the light-emitting unit and the light detection unit share a switch unit in each pixel area of the array substrate, it helps to reduce the number of switch units on the array substrate. , Simplify the structure of the array substrate.
  • FIG. 18 shows a method flow chart of another light detection method provided by an embodiment of the present application.
  • the light detection method can be used in the array substrate provided in the above embodiment, and each pixel area of the array substrate A light detection unit, a switch unit, and a light emitting unit are provided, and the light detection unit in each pixel area and the light emitting unit in the pixel area share the switch unit in the pixel area.
  • the light detection unit includes a first electrode, a photosensitive layer and a second electrode, and the light detection method can be executed by a light detection component.
  • the method may include the following steps:
  • step 401 the switch unit is controlled to work in the turn-on transition area, which is the area between the turn-on area and the turn-off area of the switch unit.
  • the light detection component may be electrically connected to the control electrode (for example, gate) of the switch unit, and the light detection component may apply a control voltage (for example, gate voltage) to the switch unit to make the switch unit work in the turn-on transition region.
  • a control voltage for example, gate voltage
  • the turn-on transition area is the area between the turn-on area and the turn-off area of the switch unit.
  • the switch unit is a TFT
  • the turn-on transition area is also a sub-threshold swing area.
  • step 402 a voltage is applied to the first electrode of the photodetection unit to make the second electrode of the photodetection unit have a potential, wherein under the action of the light irradiated to the first electrode, the potential of the second electrode changes, causing the switch The output current of the unit changes.
  • the light detection component may be electrically connected to the first electrode of the light detection unit, and the light detection component may apply a voltage to the first electrode of the light detection unit.
  • the photosensitive layer for example, The PIN layer
  • the photosensitive layer can accumulate electric charges, so that the second electrode of the photodetection component has a potential.
  • the photodetection unit when light is irradiated on the first electrode, the photodetection unit will generate a photo-generated bias, which can change the potential of the second electrode, and the change of the potential of the second electrode will cause the output of the switch unit
  • the photodetection unit when light is irradiated on the first electrode, the photodetection unit will generate a photo-generated bias, which can change the potential of the second electrode, and the change of the potential of the second electrode will cause the output of the switch unit
  • a positive voltage can be applied to the first electrode of the photodetection unit to positively bias the photosensitive layer to remove residual charges in the photosensitive layer, and then step 402 is performed to avoid residual charges in the photosensitive layer. The effect of charge on the photodetection process.
  • step 403 the amount of change in the output current of the switching unit is determined.
  • the output current of the switch unit is also the leakage current of the switch unit.
  • the light detection component can be electrically connected to the first pole (that is, the drain) of the switch unit, and the output current of the switch unit will be transmitted to the light detection component through the first pole of the switch unit.
  • the size of the output current and the size of the output current of the switch unit after illumination determine the amount of change in the output current of the switch unit.
  • step 404 according to the amount of change in the output current of the switch unit, the intensity of light irradiated to the first electrode is determined.
  • the intensity of light irradiated to the first electrode is also the intensity of light irradiated to the first electrode.
  • the light detection unit can maintain the correlation between the current change and the light intensity, and the light detection unit can determine the amount of light irradiated to the first electrode according to the change of the output current of the switch unit and the correlation between the current change and the light intensity. Light intensity.
  • step 405 fingerprint detection is performed according to the amount of change in the output current of the plurality of switch units.
  • the fingerprint of the finger can reflect the light emitted by the array substrate to generate reflected light, and the reflected light can enter the light detection unit of at least one pixel area, and The reflected light formed by the reflection of the “ridge” and “groove” of the fingerprint is different.
  • the reflected light formed by the reflection of the “ridge” and “groove” of the fingerprint can enter the photodetection unit of different pixel area, causing the different pixel area
  • the output current of the switch unit changes, and the amount of change in the output current of the switch unit in the different pixel areas is different. Therefore, the "ridges" and “grooves” of the fingerprint can be imaged according to the amount of change in the output current of the switch units in different pixel areas. "The outline of the fingerprint detection.
  • the light detection unit can also detect the ambient light where the array substrate is located, and the light detection unit can transmit the detected intensity of the ambient light to the light detection component.
  • the array substrate is applied to a smart terminal such as a mobile phone
  • the light detection component can adjust the screen brightness of the smart terminal according to the ambient light intensity detected by the light detection unit, so as to realize the automatic adjustment of the screen brightness of the smart terminal, which will not be repeated in the embodiments of the present application.
  • the light-emitting unit and the light detection unit share a switch unit in each pixel area of the array substrate, it helps to reduce the number of switch units on the array substrate. , Simplify the structure of the array substrate.
  • FIG. 19 shows a block diagram of a light detection assembly 500 provided by an embodiment of the present application.
  • the light detection assembly 500 may be used to implement the light detection method provided by the embodiment shown in FIG. 17 or FIG. 18.
  • the light detection assembly 500 may include but is not limited to:
  • the control module 510 is used for controlling the switch unit to work in the opening transition zone, the opening transition zone being the area between the opening zone and the closing zone of the switching unit;
  • the pressurizing module 520 is used to apply a voltage to the first electrode of the light detection unit to make the second electrode of the light detection unit have a potential, wherein the potential of the second electrode changes under the action of the light irradiated to the first electrode, Cause the output current of the switch unit to change;
  • the first determining module 530 is configured to determine the amount of change in the output current of the switch unit
  • the second determining module 540 is configured to determine the intensity of light irradiated to the first electrode according to the amount of change in the output current of the switch unit.
  • the light irradiated to the first electrode is the light reflected by the fingerprint.
  • the light detection assembly 500 further includes: a detection module 550, which is used to detect The amount of output current change, fingerprint detection.
  • the light-emitting unit and the light detection unit share a switch unit in each pixel area of the array substrate, it helps to reduce the number of switch units on the array substrate. , Simplify the structure of the array substrate.
  • an embodiment of the present application also provides a display device, which includes the array substrate shown in FIGS. 1 to 4.
  • the display device further includes the light detection assembly shown in FIG. 19 or FIG. 20.
  • the display device may be an electroluminescent display device, for example, an OLED display device or a QLED display device.
  • the display device can be any product or component with display function such as electronic paper, display substrate, display panel, watch, bracelet, mobile phone, tablet computer, TV, monitor, notebook computer, digital photo frame or navigator.
  • the term “electrically connected” refers to the connection and the ability to transfer charges, but not necessarily charge transfer.
  • a and B are electrically connected to mean that A and B are connected and A and B can transfer charges, but A There is not necessarily charge transfer with B.
  • the term “at least one” means one or more, and multiple means two or more, unless specifically defined otherwise.
  • the terms “first”, “second” and “third” are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance.

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Abstract

一种阵列基板及其制造方法、光检测方法及组件、显示装置。该阵列基板包括：衬底基板（11），该衬底基板（11）具有像素区；位于该像素区中的光检测单元（12）、开关单元（13）和发光单元（14），该发光单元（14）与该光检测单元（12）共用该开关单元（13）。有助于简化阵列基板的结构。

Description

阵列基板及其制造方法、光检测方法及组件、显示装置
本申请要求于2019年05月28日提交的申请号为201910452554.8、发明名称为“阵列基板、光检测方法及组件、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及一种阵列基板及其制造方法、光检测方法及组件、显示装置。
背景技术
随着显示技术的发展，越来越多的显示产品集成有光检测单元，以实现光检测功能，例如集成有光检测单元的显示产品可以检测显示产品所处环境的环境光等。通常，可以将光检测单元集成在显示产品的阵列基板上。
发明内容
本申请提供一种阵列基板及其制造方法、光检测方法及组件、显示装置。本申请的技术方案如下：
第一方面，提供一种阵列基板，包括：
衬底基板，所述衬底基板具有像素区；
位于所述像素区中的光检测单元、开关单元和发光单元，所述光检测单元与所述发光单元共用所述开关单元。
可选地，所述开关单元位于背离所述光检测单元的感光层的一侧，所述开关单元与所述光检测单元绝缘，所述光检测单元在所述衬底基板上的正投影与所述开关单元在所述衬底基板上的正投影至少部分重叠；
所述开关单元与所述发光单元电连接。
可选地，所述开关单元在所述衬底基板上的正投影覆盖所述光检测单元在所述衬底基板上的正投影。
可选地，所述光检测单元包括沿靠近所述开关单元的方向依次叠加的第一电极、感光层和第二电极；
所述开关单元包括有源层，以及位于所述有源层远离所述光检测单元的一 侧的控制极、第一极和第二极，所述第一极和所述第二极中的一个为源极，另一个为漏极。
可选地，所述第二电极的材料为遮光材料，所述第二电极在所述衬底基板上的正投影与所述有源层在所述衬底基板上的正投影至少部分重叠。
可选地，所述第二电极在所述衬底基板上的正投影覆盖所述有源层在所述衬底基板上的正投影。
可选地，所述发光单元为电致发光单元，所述开关单元的所述第一极与所述发光单元的阳极电连接。
可选地，所述阵列基板还包括：
位于所述光检测单元与所述开关单元之间的绝缘层；
位于所述开关单元与所述发光单元之间的平坦层；以及，
位于所述平坦层远离所述开关单元的一侧的像素界定层，所述发光单元位于所述像素界定层限定的像素开口中。
可选地，所述光检测单元、所述开关单元和所述发光单元沿远离所述衬底基板的方向依次分布，所述阵列基板还包括：
位于所述发光单元远离所述衬底基板的一侧的封装层。
第二方面，提供一种光检测方法，用于第一方面或第一方面任一可选方式所述的阵列基板，所述阵列基板的光检测单元包括第一电极、感光层和第二电极，所述方法包括：
控制所述开关单元工作在开启过渡区，所述开启过渡区为所述开关单元的开启区与关闭区之间的区域；
向所述光检测单元的所述第一电极施加电压，使所述光检测单元的所述第二电极具有电势，其中，在照射至所述第一电极的光线的作用下，所述第二电极的电势变化，引起所述开关单元的输出电流变化；
确定所述开关单元的输出电流的变化量；
根据所述开关单元的输出电流的变化量，确定照射至所述第一电极的光照强度。
可选地，照射至所述第一电极的光线是经过指纹反射后的光线，在确定所述开关单元的输出电流的变化量之后，所述方法还包括：
根据多个所述开关单元的输出电流的变化量，进行指纹检测。
第三方面，提供一种光检测组件，用于第一方面或第一方面任一可选方式 所述的阵列基板，所述阵列基板的光检测单元包括第一电极、感光层和第二电极，所述光检测组件包括：
控制模块，用于控制所述开关单元工作在开启过渡区，所述开启过渡区为所述开关单元的开启区与关闭区之间的区域；
加压模块，用于向所述光检测单元的所述第一电极施加电压，使所述光检测单元的所述第二电极具有电势，其中，在照射至所述第一电极的光线的作用下，所述第二电极的电势变化，引起所述开关单元的输出电流变化；
第一确定模块，用于确定所述开关单元的输出电流的变化量；
第二确定模块，用于根据所述开关单元的输出电流的变化量，确定照射至所述第一电极的光照强度。
可选地，照射至所述第一电极的光线是经过指纹反射后的光线，所述光检测组件还包括：
检测模块，用于根据多个所述开关单元的输出电流的变化量，进行指纹检测。
第四方面，提供一种阵列基板的制造方法，包括：
提供衬底基板，所述衬底基板具有像素区；
在所述像素区中形成光检测单元、开关单元和发光单元，所述光检测单元与所述发光单元共用所述开关单元。
可选地，在所述像素区中形成光检测单元、开关单元和发光单元，所述光检测单元与所述发光单元共用所述开关单元，包括：
在所述像素区中形成光检测单元；
在所述光检测单元背离所述光检测单元的感光侧的一侧形成开关单元，所述开关单元与所述光检测单元绝缘，所述光检测单元在所述衬底基板上的正投影与所述开关单元在所述衬底基板上的正投影至少部分重叠；
在所述开关单元远离所述光检测单元的一侧形成发光单元，所述发光单元与所述开关单元电连接。
可选地，在所述像素区中形成光检测单元，包括：
在所述像素区中形成沿远离所述衬底基板的方向依次叠加的第一电极、感光层和第二电极；
在所述光检测单元背离所述光检测单元的感光侧的一侧形成开关单元，包括：
在所述光检测单元背离所述光检测单元的感光侧的一侧形成有源层；
在所述有源层远离所述光检测单元的一侧形成控制极、第一极和第二极，所述第一极和所述第二极中的一个为源极，另一个为漏极。
可选地，在所述光检测单元背离所述光检测单元的感光侧的一侧形成开关单元之前，所述方法还包括：
在所述光检测单元背离所述光检测单元的感光侧的一侧形成绝缘层；
在所述光检测单元背离所述光检测单元的感光侧的一侧形成开关单元，包括：
在所述绝缘层远离所述光检测单元的一侧形成开关单元。
可选地，在所述开关单元远离所述光检测单元的一侧形成发光单元之前，所述方法还包括：
在所述开关单元远离所述光检测单元的一侧形成平坦层；
在所述开关单元远离所述光检测单元的一侧形成发光单元，包括：
在所述平坦层远离所述光检测单元的一侧形成发光单元；
所述方法还包括：在所述平坦层远离所述开关单元的一侧形成像素界定层，所述发光单元位于所述像素界定层限定的像素开口中。
可选地，所述方法还包括：
在所述发光单元远离所述衬底基板的形成封装层。
第四方面，提供一种显示装置，包括第一方面或第一方面的任一可选方式所述的阵列基板。
可选地，所述显示装置还包括第三方面或第三方面的可选方式所述的光检测组件。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的一种阵列基板的正视图；
图2是图1所示的阵列基板的a-a部位的剖视图；
图3是本申请实施例提供的另一种阵列基板的正视图；
图4是图3所示的阵列基板的a-a部位的剖视图；
图5是本申请实施例提供的一种光检测单元进行光检测的原理图；
图6是本申请实施例提供的一种光照时间与第一电极的电势的曲线图；
图7是本申请实施例提供的一种开关单元的控制电压与输出电流的变化曲线图；
图8是本申请实施例提供的一种阵列基板的等效电路图；
图9是本申请实施例提供的一种开关单元的转移特性曲线图；
图10是本申请实施例提供的一种阵列基板的制造方法的方法流程图；
图11是本申请实施例提供的另一种阵列基板的制造方法的方法流程图；
图12至图16是本申请实施例提供的一种阵列基板的制造过程的示意图；
图17是本申请实施例提供的一种光检测方法的方法流程图；
图18是本申请实施例提供的另一种光检测方法的方法流程图；
图19是本申请实施例提供的一种光检测组件的框图；
图20是本申请实施例提供的另一种光检测组件的框图。
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本申请的实施例，并与说明书一起用于解释本申请的原理。
具体实施方式
为了使本申请的原理、技术方案和优点更加清楚，下面将结合附图对本申请作详细描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本申请保护的范围。
随着显示技术的发展，光检测单元可以集成在阵列基板上，以使阵列基板能够实现光检测功能。例如，集成有光检测单元的阵列基板能够检测该阵列基板所处环境的环境光，又例如，集成有光检测单元的阵列基板能够检测该阵列基板的发光单元发出的光线。目前，集成有光检测单元的阵列基板包括：衬底基板以及位于衬底基板上的发光单元、光检测单元和薄膜晶体管(英文：Thin Film Transistor；简称：TFT)，衬底基板具有阵列排布的多个像素区，目前，每个像素区中设置有一个发光单元、一个光检测单元和两个TFT，两个TFT同层分布，发光单元和光检测单元由该两个TFT分别独立控制。
但是，这样的阵列基板的TFT的数量较多，导致阵列基板的结构复杂。并 且由于两个TFT同层分布，因此发光单元和光检测单元在像素区的占比较低，导致阵列基板的像素填充率和检测分辨率均较低。
请参考图1和图2，图1是本申请实施例提供的一种阵列基板的正视图，图2是图1所示的阵列基板的a-a部位的剖视图，参见图1和图2，该阵列基板包括：衬底基板11，衬底基板11具有像素区P；位于像素区P中的光检测单元12、开关单元13和发光单元14，光检测单元12与发光单元14共用开关单元13。
本领域技术人员容易理解，衬底基板11具有阵列排布的多个像素区P，在本申请实施例中，每个像素区P中设置有一个光检测单元12、一个开关单元13和一个发光单元14，每个像素区P中的光检测单元12和发光单元14共用该像素区P中的开关单元13。
综上所述，本申请实施例提供的阵列基板，由于在像素区中，发光单元与光检测单元共用一个开关单元，因此有助于减少阵列基板上的开关单元的数量，简化阵列基板的结构。
可选地，光检测单元12具有感光侧，开关单元13位于背离光检测单元12的感光侧的一侧，开关单元13与光检测单元12绝缘，光检测单元12在衬底基板11上的正投影与开关单元13在衬底基板11上的正投影至少部分重叠，开关单元13与发光单元14电连接。可选地，光检测单元12的感光侧为光检测单元12靠近衬底基板11的一侧，则如图2所示，开关单元13位于背离光检测单元12的感光侧的一侧也即是开关单元13位于光检测单元12远离衬底基板11的一侧。在光线的照射下，光检测单元12可以产生电流，光检测单元12产生的电流可以影响开关单元13的输出电流，当开关单元13工作在开启过渡区时，光检测单元12产生的电流对开关单元13的输出电流的影响较为明显，因此可以根据开关单元13工作在开启过渡区时，开关单元13的输出电流的变化量来确定照射至光检测单元12的光照强度(也即是照射至光检测单元12的光线的强度)。在本申请实施例中，可以控制开关单元13工作在开启过渡区，使开关单元13控制光检测单元12进行光检测，并且由于开关单元13与发光单元14电连接，开关单元13可以控制发光单元14发光，从而开关单元13可以对光检测单元12和发光单元14进行控制，实现光检测单元12与发光单元14共用开关单元13。其中，开启过渡区为开关单元的开启区与关闭区之间的区域，例如TFT的开启区与关闭区之间的区域为亚阈值摆幅(英文：Subthreshold swing；简称： SS)区，当开关单元为TFT时，该开启过渡区可以为SS区。
可选地，光检测单元12在衬底基板11上的正投影与开关单元13在衬底基板11上的正投影至少部分重叠。例如，开关单元13在衬底基板11上的正投影覆盖光检测单元12在衬底基板11上的正投影。由于开关单元13位于光检测单元12远离衬底基板11的一侧，光检测单元12在衬底基板11上的正投影与开关单元13在衬底基板11上的正投影至少部分重叠，因此开关单元13与光检测单元12垂直分布，有助于减小开关单元13在像素区P中的占用面积，提高阵列基板的像素填充率和检测分辨率。其中，垂直分布指的是沿与衬底基板11的板面垂直的方向分布。容易理解，当开关单元13在衬底基板11上的正投影覆盖光检测单元12在衬底基板11上的正投影时，有助于在最大范围内减小开关单元13在像素区P中的占用面积，提高阵列基板的像素填充率和检测分辨率。
可选地，如图2所示，光检测单元12包括沿靠近开关单元13的方向依次叠加的第一电极121、感光层122和第二电极123；开关单元13包括有源层131，以及位于有源层131远离光检测单元12的一侧的控制极132、第一极133和第二极134，第一极133和第二极134中的其中一个为源极，另一个为漏极，第一极133和第二极134分别与有源层131电连接。由于阵列基板根据光线的照射下，光检测单元12产生的电流对开关单元13的输出电流的影响确定照射至光检测单元12的光照强度，从而进行光检测，而开关单元13的输出电流与有源层131相关，若控制极132位于有源层131靠近光检测单元12的一侧，则控制极132会将有源层131屏蔽，导致光检测单元12产生的电流对开关单元13的输出电流的影响减小甚至消失，难以实现光检测。本申请实施例中，由于控制极132位于有源层131远离光检测单元12的一侧，因此有助于避免控制极132将有源层131屏蔽，从而避免光检测单元12产生的电流对开关单元13的输出电流的影响减小甚至消失，便于实现光检测。在本申请实施例中，照射至光检测单元12的光线可以是发光单元14发射的光线，也可以是阵列基板所处环境中的光线，本申请实施例对此不作限定。
可选地，光检测单元12可以为光电二极管，感光层122可以为PIN层，开关单元13可以为TFT，控制极132可以为栅极、第一极133可以为漏极，第二极134可以为源极，第一极133和第二极134可以同层分布，且第一极133和第二极134可以通过同一次构图工艺制备。如图2所示，开关单元13还包括位于有源层131与控制极132之间的栅绝缘层135，以及，位于控制极132与第一 极133和第二极134之间的层间介质层136，栅绝缘层135和层间介质层136上具有连通的第一连接孔(例如漏极过孔)以及连通的第二连接孔(例如源极过孔)，第一极133依次通过层间介质层135上的第一连接孔和栅绝缘层135上的第一连接孔与有源层131电连接，第二极134依次通过层间介质层135上的第二连接孔和栅绝缘层135上的第二连接孔与有源层131电连接。
可选地，第二电极123的材料可以为遮光材料，第二电极123在衬底基板11上的正投影与有源层131在衬底基板11上的正投影至少部分重叠。可选地，第二电极123在衬底基板11上的正投影覆盖有源层131在衬底基板11上的正投影，这样一来，第二电极123可以作为遮光(英文：Light shield；简称：LS)层对有源层131进行遮挡，避免光线从衬底基板11所在侧照射至有源层131影响有源层131的特性，从而避免光照对开关单元13的开关特性的影响。
可选地，第一电极121的材料可以为氧化铟锡(英文：Indium tin oxide；简称：ITO)、氧化铟锌(英文：Indium zinc oxide；简称：IZO)或掺铝氧化锌(英文：aluminum-doped zinc oxide；简称：ZnO:Al)等透明导电材料，第一电极121的厚度的取值范围可以为50nm～130nm(中文：纳米)；感光层122(例如PIN层)可以包括依次叠加的P型半导体层、本征半导体层和N型半导体层，P型半导体层相对于N型半导体层可以靠近第一电极121，也可以远离第一电极121，该P型半导体层可以为P型掺杂的a-Si(中文：非晶硅)膜层，P型半导体层的厚度的取值范围可以为10nm～20nm，本征半导体层可以为a-Si膜层，本征半导体层的厚度的取值范围可以为500nm～1000nm，N型半导体层可以为N型掺杂的a-Si膜层，N型半导体层的厚度的取值范围可以为10nm～20nm，例如，P型半导体层掺杂有硼离子，N型半导体层掺杂有磷离子；第二电极123的材料可以为金属Mg(中文：镁)、金属Ag(中文：银)、金属Mo(钼)、金属Cu(铜)、金属Al(铝)、金属Au(金)及其合金材料，第二电极123的厚度的取值范围可以为200nm～400nm。
可选地，有源层131可以为氧化物(英文：Oxide)有源层、a-Si有源层或p-Si有源层，氧化物有源层例如铟镓锌氧化物(英文：indium gallium zinc oxide；简称：IGZO)有源层或铟锡锌氧化物(英文：indium tin zinc oxide；简称：ITZO)有源层，有源层131上与第一极133和第二极134连接的部位均进行了导体化处理，以增加该部位的载流子浓度，保证该部位和相应电极(例如第一极或第二极)实现欧姆接触；栅绝缘层135的材料可以为SiO 2(中文：二氧化硅)、 SiOx(中文：氧化硅)、SiNx(中文：氮化硅)、Al 2O 3(中文：氧化铝)或SiOxNx(中文：氮氧化硅)等透明绝缘材料，栅绝缘层135可以为单层或多层结构，例如，栅绝缘层135可以为SiO 2单层结构或SiN/SiO 2多层结构(也即是SiN膜层和SiO 2膜层交替叠加构成的多层结构)，栅绝缘层135的厚度的取值范围可以为80nm～150nm；控制极132的材料可以为金属Mo、金属Cu、金属Al、金属Au及其合金材料，控制极132的厚度的取值范围可以为200nm～400nm；层间介质层136的材料可以为SiO 2、SiOx、SiNx、Al 2O 3或SiOxNx等透明绝缘材料，层间介质层136可以为单层或多层结构，例如，层间介质层136可以为SiO 2单层结构或SiN/SiO 2多层结构，层间介质层136的厚度的取值范围可以为80nm～150nm；第一极133的材料和第二极134的材料均可以为金属Mg、金属Ag、属Mo、金属Cu、金属Al、金属Au及其合金材料，且第一极133的厚度和第二极134的厚度的取值范围可以为200nm～400nm。
可选地，发光单元14可以为电致发光单元，如图1所示，发光单元14包括沿远离衬底基板11的方向依次叠加的阳极141、电致发光层142和阴极143，阳极141与第一极133电连接。其中，电致发光单元可以为有机发光二极管(英文：Organic Light-Emitting Diode；简称：OLED)单元或量子点发光二极管(英文：Quantum Dot Light Emitting Diodes；简称：QLED)单元，阳极141的材料可以为金属Mg、金属Ag、金属Mo、金属Cu、金属Al、金属Au及其合金材料；阴极143的材料可以为ITO、IZO或金属Ag等导电材料，例如，阴极143为ITO/Ag/ITO的多层结构，其中ITO膜层的厚度为8nm，Ag膜层的厚度为100nm。本领域技术人员容易理解，电致发光单元包括两个电极以及夹设在两个电极之间的电致发光层，本申请实施例以该两个电极包括阳极141和阴极143，且与开关单元13的第一极133电连接的电极为阳极，未与开关单元13电连接的电极为阴极为例说明，实际应用中，阴极可以是与开关单元13的第一极133电连接的电极，而阳极可以是未与开关单元13电连接的电极，并且在不同的场景下，上述两个电极的名称还可以是其他名称。此外，图1和图2中示出的发光单元14仅仅是示例性的，实际应用中，发光单元14还可以包括空穴注入层、空穴传输层、电子传输层和电子注入层等，本申请实施例在此不再赘述。
可选地，如图1所示，该阵列基板还包括多条栅线19和多条数据线20，多条栅线19和多条数据线20绝缘交叉限定多个像素区P，开关单元13的控制极132(例如栅极)可以与栅线19电连接，开关单元13的第二极134(例如源极) 可以与数据线20电连接，栅线19用于向控制极132施加控制电压，数据线20用于向第二极134施加数据电压。可选地，栅线19与控制极132可以同层分布，且栅线19与控制极132可以通过同一次构图工艺制备，数据线20与第二极134同层分布，且数据线20与第二极134可以通过同一次构图工艺制备。
可选地，如图2所示，该阵列基板还包括位于光检测单元12与开关单元13之间的绝缘层15；位于开关单元13与发光单元14之间的平坦层16；以及，位于平坦层16远离开关单元13的一侧的像素界定层17，像素界定层17限定出像素开口K，像素开口K在衬底基板11上的正投影位于像素区P内，发光单元14位于像素界定层17限定的像素开口K中。其中，绝缘层15可以包括叠加的有机绝缘层和无机绝缘层，有机绝缘层的材料可以为树脂，有机绝缘层的厚度与光检测单元12的厚度的差值范围可以为1.2μm～3μm(中文：微米)，无机绝缘层可以为单层或多层结构，例如无机绝缘层可以为SiO 2单层结构或SiN/SiO 2多层结构；平坦层16的材料可以为树脂，平坦层16的厚度的取值范围可以为2μm～3μm；像素界定层17的材料可以为疏液性(例如疏水性)较强的树脂，电致发光层142通常采用喷墨打印工艺或者溶液制程形成，像素界定层17的材料为疏液性较强的树脂可以便于在像素开口K中打印溶液，从而便于像素界定层17能够将发光单元14限定在像素开口K中。
可选地，如图2所示，光检测单元12、开关单元13和发光单元14沿远离衬底基板11的方向依次分布。请参考图3和图4，图4是本申请实施例提供的另一种阵列基板的正视图，图4是图2所示的阵列基板的a-a部位的剖视图，参见图4，在图2的基础上，该阵列基板还包括封装层18，封装层18位于发光单元14远离衬底基板11的一侧，封装层18覆盖发光单元14以及像素界定层17，该封装层18用于封装该阵列基板的发光单元14。可选地，封装层18可以为薄膜封装(英文：Thin Film Encapsulation；简称：TFE)层或者封装盖板，TFE层可以包括交替叠加的无机层和有机层，无机层的材料可以为SiO 2、SiOx、SiNx、Al 2O 3或SiOxNx等透明绝缘材料，有机层的材料可以为有机树脂，封装盖板可以是采用玻璃等材料制备的盖板，本申请实施例对此不作限定。
本申请实施例提供的阵列基板可以为底发射阵列基板或顶发射阵列基板，当开关单元和发光单元沿远离衬底基板的方向分布时，在底发射阵列基板中，开关单元在衬底基板上的正投影与发光单元在衬底基板上的正投影不存在重叠区域，以避免开关单元遮挡发光单元发射出的光线，影响阵列基板的出光率， 在顶发射阵列基板中，即使开关单元在衬底基板上的正投影与发光单元在衬底基板上的正投影存在重叠区域，开关单元也不会遮挡发光单元发射出的光线，从而不会影响阵列基板的出光率，相比于底发射阵列基板，顶发射阵列基板具有较高的开口率。示例地，底发射阵列基板可以如图1和图2所示，顶发射阵列基板可以如图3和图4所示。本领域技术人员容易理解，图1至图4所示出的阵列基板仅仅是示例性的，实际应用中，底发射阵列基板和顶发射阵列基板均可以包括封装层，此外，除图1至图4示出的结构外，阵列基板还可以包括像素电路以及位于感光层的侧壁上的保护层等，保护层的材料可以为SiO(中文：氧化硅)、SiN(中文：氮化硅)，保护层的厚度的取值范围可以为50nm～150nm，本申请实施例在此不再赘述。
在本申请实施例中，光检测单元12可以在开关单元13的控制下进行光检测，下面结合图1至图4，对光检测单元12进行光检测的原理进行说明。
光检测单元12为具有PIN层(也即是感光层122)的光电二极管，该光检测单元12也可以称为PIN结光电二极管，该光检测单元12对光照十分敏感，可以准确感测到光信号，并基于光生伏特效应(英文：photovoltaic effect)将光信号转换为电信号。在光检测单元12中，第一电极121用于感测光信号，因此第一电极121可以称为光检测单元12的光敏电极(或称为光敏面、感光面等)。请参考图5，其示出了本申请实施例提供的一种光检测单元12进行光检测的原理图，在图5中，P区对应光检测单元12的P型半导体层，I区对应光检测单元12的本征半导体层，N区对应光检测单元12的N型半导体层，该光检测单元12的工作原理为：当光线照射到第一电极121上时，该光线的能量会使得P区的电子和N区的电子发生跃迁产生电子-空穴对，在I区的内电场的作用下，电子(能量为hv)向带有正电的N区移动并累积在N区，空穴向带有负电的P区移动并累积在P区，使P区和N区之间产生电压差(又称为光生偏压)，第一电极121和第二电极123(也即是LS层)均具有一定电势。
请参考图6，其示出了光线照射至第一电极121时，光照时间t与第一电极121的电势U1的曲线图，其中，曲线Q1表示波长为600纳米的光线照射至第一电极121时，光照时间t与第一电极121的电势U1的变化关系，曲线Q2表示波长为800纳米的光线照射至第一电极121时，光照时间t与第一电极121的电势U1的变化关系，曲线Q3表示波长为900纳米的光线照射至第一电极121时，光照时间t与第一电极121的电势U1的变化关系，曲线Q4表示波长为1200 纳米的光线照射至第一电极121时，光照时间t与第一电极121的电势U1的变化关系，曲线Q5表示白光照射至第一电极121时，光照时间t与第一电极121的电势U1的变化关系，参见图6可以看出，不同波长的光线照射至第一电极121时，第一电极121产生的电势U1不同。
光照可以引起第一电极121和第二电极123(也即是LS层)的电势发生变化，第二电极123的电势发生变化可以引起开关单元13的控制电压(也即是控制极132的电压，例如栅电压)Vg发生变化，开关单元13的控制电压Vg发生变化可以引起开关单元13的输出电流Id发生变化，因此可以根据光照引起的开关单元13的输出电流Id的变化量，确定照射至第一电极121的光照强度(也即是照射至第一电极121的光线的强度)，从而实现光检测。请参考图7，其示出了开关单元13的控制电压Vg与输出电流Id的变化曲线图，U2表示第二电极123的电势，每条曲线对应一个U2，U2按照箭头所示方向增大，可以看出，不同U2对应的曲线不同，因此第二电极123的电势对开关单元13的阈值电压Vth有显著影响。
请参考图8，其示出了本申请实施例提供的一种阵列基板的等效电路图，在图8中，bias表示光检测单元12的第一电极121，LS表示光检测单元12的第二电极123，开关单元13的控制极(例如栅极，英文：Gate)与阵列基板中的栅线(图8中未示出)电连接，开关单元13的第二极S(例如源极)与阵列基板中的数据线(图8中未示出)电连接，开关单元13的第一极D(例如漏极)与发光单元14电连接，此外，开关单元13的第一极D还与位于阵列基板外部的光检测组件电连接，该光检测组件可以为芯片，或者芯片中的功能组件，该芯片可以是集成电路芯片。请参考图9，其示出了本申请实施例提供的一种开关单元13的转移特性曲线图，该图9以开关单元13为TFT为例，则开关单元13的开启过渡区也即是SS区，光线照射至光检测单元12的第一电极121时，光检测单元12产生的光生偏压对开关单元13的影响较小，因此开关单元13的输出电流Id的变化量通常较小，当开关单元13工作在关闭(OFF)区或开启(ON)区时，照射至光检测单元12的第一电极121的光线引起的开关单元13的输出电流Id的变化量通常难于测量，而当开关单元13工作在SS区时，照射至光检测单元12的第一电极121的光线引起的开关单元13的输出电流Id的变化量易于测量，因此可以根据开关单元13工作在SS区时，照射至光检测单元12的第一电极121的光线引起的开关单元13的输出电流Id的变化量确定照射至光检测 单元12的第一电极121的光照强度，也即是，可以控制开关单元13工作在SS区，来利用开关单元13控制光检测单元13进行光检测。其中，根据照射至光检测单元12的第一电极121的光线引起的开关单元13的输出电流Id的变化量确定光照强度的过程可以由图8中的光检测组件执行。结合图8和图9，在本申请实施例中，当开关单元13工作在ON区时，开关单元13处于开启状态，开关单元13控制发光单元14发光，当开关单元13工作在OFF区时，开关单元13处于关闭状态，当开关单元13工作在SS区时，开关单元13处于开启状态与关闭状态之间，开关单元13控制光检测单元13进行光检测。
下面结合图1至图9，对开关单元13控制发光单元14发光，以及开关单元13控制光检测单元12进行光检测的过程进行说明。
开关单元13控制光检测单元12进行光检测的过程可以包括：首先，向光检测单元12的第一电极121(也即是bias)施加正电压使PIN层(也即是感光层122)正偏，去除PIN层中的残余电荷(PIN层正偏时相当于导线，因此PIN层中存储的电荷被导出)；然后，向开关单元13施加控制电压Vg使开关单元13工作在SS区，向检测单元12的第一电极121施加负电压使PIN层反偏，PIN层反偏时相当于电容，可以存储电荷；当光线照射至第一电极121时，PIN层中存储电荷而产生偏压(可参考上述光检测单元12的工作原理)，使得第二电极123的电势发生变化，从而引起开关单元13的阈值电压Vth漂移，在开关单元13的阈值电压Vth漂移而开关单元13的控制电压Vg不变的情况下，开关单元13的输出电流Id会在SS区内变化，可以确定光照前后开关单元13的输出电流Id的变化量，并根据光照前后开关单元13的输出电流Id的变化量确定照射至第一电极121的光照强度。实验证明，本申请实施例提供的阵列基板检测到的信号强度比传统的阵列基板检测到的信号强度大2～3个数量级，甚至4个数量级，因此本申请实施例提供的阵列基板有利于实现高分辨率检测。
开关单元13控制发光单元14发光的过程可以包括：向开关单元13施加控制电压Vg使开关单元13工作在ON区，向检测单元12的第一电极121施加正电压使PIN层正偏，此时，开关单元13控制发光单元14开启从而使发光单元14发光。由于在开关单元13工作在ON区时，PIN层产生的压差对开关单元13的输出电流的影响较小甚至没有影响，因此在开关单元13工作在ON区时，PIN层的光生偏压不会对发光单元14的发光效果产生影响，从而不会对阵列基板的显示效果产生影响，因此光检测单元12和发光单元14可以共用开关单元13。
综上所述，本申请实施例提供的阵列基板，由于在像素区中，发光单元与光检测单元共用一个开关单元，因此有助于减少阵列基板上的开关单元的数量，简化阵列基板的结构。
下述为本申请的阵列基板的制造方法的实施例，本申请中阵列基板的制造方法和制造原理可以参见下文各实施例中的描述。
请参考图10，其示出了本申请实施例提供的一种阵列基板的制造方法的方法流程图，该阵列基板的制造方法可以用于制造图1或图4所示的阵列基板，参见图10，该方法可以包括如下步骤：
在步骤101中、提供衬底基板，衬底基板具有像素区。
在步骤102中、在像素区中形成光检测单元、开关单元和发光单元，光检测单元与发光单元共用开关单元。
综上所述，本申请实施例提供的阵列基板的制造方法，由于在像素区中，发光单元与光检测单元共用一个开关单元，因此有助于减少阵列基板上的开关单元的数量，简化阵列基板的结构。
可选地，步骤102包括：
在像素区中形成光检测单元；
在光检测单元背离该光检测单元的感光侧的一侧形成开关单元，开关单元与光检测单元绝缘，光检测单元在衬底基板上的正投影与开关单元在衬底基板上的正投影至少部分重叠；
在开关单元远离光检测单元的一侧形成发光单元，发光单元与开关单元电连接。
可选地，在像素区中形成光检测单元，包括：
在像素区中形成沿远离衬底基板的方向依次叠加的第一电极、感光层和第二电极；
在光检测单元背离该光检测单元的感光侧的一侧形成开关单元，包括：
在光检测单元背离该光检测单元的感光侧的一侧形成有源层；
在有源层远离光检测单元的一侧形成控制极、第一极和第二极。
可选地，第二电极的材料为遮光材料，第二电极在衬底基板上的正投影与有源层在衬底基板上的正投影至少部分重叠。
可选地，第二电极在衬底基板上的正投影覆盖有源层在衬底基板上的正投 影。
可选地，在光检测单元背离该光检测单元的感光侧的一侧形成开关单元之前，该方法还包括：
在光检测单元背离该光检测单元的感光侧的一侧形成绝缘层；
相应地，在光检测单元背离该光检测单元的感光侧的一侧形成开关单元，包括：
在绝缘层远离该光检测单元的一侧形成开关单元。
可选地，在开关单元远离光检测单元的一侧形成发光单元之前，该方法还包括：
在开关单元远离光检测单元的一侧形成平坦层；
相应地，在开关单元远离光检测单元的一侧形成发光单元，包括：
在平坦层远离光检测单元的一侧形成发光单元；
该方法还包括：在平坦层远离开关单元的一侧的像素界定层，发光单元位于所述像素界定层限定的像素开口中。
可选地，该方法还包括：在发光单元远离平坦层的一侧形成封装层。
上述所有可选技术方案，可以采用任意结合形成本申请的可选实施例，在此不再一一赘述。
请参考图11，其示出了本申请实施例提供的另一种阵列基板的制造方法的方法流程图，该阵列基板的制造方法可以用于制造图1或图3所示的阵列基板，本申请实施例以制造图3所示的阵列基板为例进行说明。参见图11，该方法可以包括如下步骤：
在步骤201中、提供衬底基板，衬底基板具有像素区。
其中，衬底基板可以为透明基板，例如，衬底基板可以为采用玻璃、石英或者透明树脂等具有一定坚固性的导光且非金属材料制成的刚性基板；或者，衬底基板为采用聚酰亚胺(英文：Polyimide；简称：PI)等柔性材料制成的柔性基板。
在步骤202中、在像素区中形成光检测单元。
请参考图12，其示出了本申请实施例提供的一种在衬底基板11上形成光检测单元12后的示意图，光检测单元12包括沿远离衬底基板11的方向依次叠加的第一电极121、感光层122和第二电极123，感光层122可以为PIN层，包括 依次叠加的P型半导体层、本征半导体层和N型半导体层，P型半导体层相对于N型半导体层可以靠近第一电极121，也可以远离第一电极121。其中，P型半导体层可以为P型掺杂的a-Si膜层，P型半导体层的厚度的取值范围可以为10nm～20nm，本征半导体层可以为a-Si膜层，本征半导体层的厚度的取值范围可以为500nm～1000nm，N型半导体层可以为N型掺杂的a-Si膜层，N型半导体层的厚度的取值范围可以为10nm～20nm；第一电极121的材料可以为ITO、IZO或ZnO:Al等透明导电材料，第一电极121的厚度的取值范围可以为50nm～130nm，第二电极123的材料为遮光材料，例如第二电极123的材料为金属Mo、金属Cu、金属Al、金属Au及其合金材料，第二电极123的厚度的取值范围可以为200nm～400nm。
示例地，以P型半导体层相对于N型半导体层可以靠近第一电极121为例，在像素区中形成光检测单元12可以包括如下三个步骤：
步骤(1)、通过磁控溅射、热蒸发或者等离子体增强化学气相沉积法(英文：Plasma Enhanced Chemical Vapor Deposition；简称：PECVD)等工艺中的任一种在衬底基板11上形成厚度在50nm～130nm之间的ITO材质层，通过一次构图工艺对ITO材质层进行处理得到第一电极121，第一电极121位于衬底基板11的像素区中。
步骤(2)、在第一电极121远离衬底基板11的一侧依次形成厚度在10nm～20nm之间的P型半导体材质层、厚度在500nm～1000nm之间的本征半导体材质层和厚度为10nm～50nm之间的N型半导体材质层，通过一次构图工艺对该P型半导体材质层、该本征半导体材质层和该N型半导体材质层进行处理得到与第一电极121依次叠加的P型半导体层、本征半导体层和N型半导体层，从而得到感光层122(也即是PIN层122)。其中，形成P型半导体材质层可以包括：首先通过PECVD工艺沉积本征半导体材料形成本征半导体材质层，然后对本征半导体材质层进行P型掺杂得到P型半导体材质层；或者，首先对本征半导体材料进行P型掺杂得到P型半导体材料，然后通过PECVD工艺沉积P型半导体材料得到P型半导体材质层。N型半导体材质层的形成过程与此类似，在此不再赘述。本领域技术人员容易理解，本申请实施例是以同时形成P型半导体层、本征半导体层和N型半导体层为例说明的，实际应用中，可以在每形成一半导体材质层(例如P型半导体材质层)后，就对该半导体材质层进行处理得到相应的半导体层(例如P型半导体层)，本申请实施例对此不作限定。
步骤(3)、通过磁控溅射、热蒸发或者PECVD等工艺中的任一种在感光层122远离衬底基板11的一侧形成厚度在200nm～400nm之间的金属Mo材质层，通过一次构图工艺对金属Mo材质层进行处理得到与感光层122叠加的第二电极123。
在步骤203中、在光检测单元背离该光检测单元的感光侧的一侧形成绝缘层。
请参考图13，其示出了本申请实施例提供的一种在光检测单元12背离该光检测单元12的感光侧的一侧形成绝缘层15后的示意图，绝缘层15覆盖光检测单元12，绝缘层15远离光检测单元12的一面为平面。如图13所示，光检测单元12背离该光检测单元12的感光侧的一侧也即是该光检测单元12远离衬底基板11的一侧。其中，绝缘层15可以包括叠加的有机绝缘层和无机绝缘层，有机绝缘层的材料可以为树脂，有机绝缘层的厚度与光检测单元12的厚度差可以为1.2μm～3μm，无机绝缘层可以为单层或多层结构，例如无机绝缘层可以为SiO 2单层结构或SiN/SiO 2多层结构。
示例地，在光检测单元12背离该光检测单元12的感光侧的一侧形成绝缘层15可以包括如下两个步骤：
步骤(1)、通过磁控溅射、热蒸发或者PECVD等工艺中的任一种在光检测单元12背离该光检测单元12的感光侧的一侧沉积一层树脂作为有机绝缘层，有机绝缘层覆盖光检测单元12。
步骤(2)、首先通过磁控溅射、热蒸发或者PECVD等工艺中的任一种在有机绝缘层远离光检测单元12的一侧形成SiN层，然后通过磁控溅射、热蒸发或者PECVD等工艺中的任一种在SiN层远离SiN层的一侧形成SiO 2层，SiN层与SiO 2层叠加构成无机绝缘层。
经过该步骤(1)和(2)，可以得到叠加的有机绝缘层和无机绝缘层，该叠加的有机绝缘层和无机绝缘层构成绝缘层15。
在步骤204中、在绝缘层远离光检测单元的一侧形成开关单元，开关单元在衬底基板上的正投影与光检测单元在衬底基板上的正投影至少部分重叠。
请参考图14，其示出了本申请实施例提供的一种在绝缘层15远离光检测单元12的一侧形成开关单元13后的示意图，开关单元13在衬底基板11上的正投影与光检测单元12在衬底基板11上的正投影至少部分重叠，可选地，开关单元13在衬底基板11上的正投影覆盖光检测单元12在衬底基板11上的正投 影。如图14所示，开关单元13包括有源层131、以及位于有源层131远离光检测单元12的一侧的控制极132、第一极133和第二极134，第一极133和第二极134同层分布，第一极133和第二极134可以通过同一次构图工艺制备，第一极133和第二极134分别与有源层131电连接。其中，该开关单元13可以为TFT，则如图14所示，该开关单元13还包括位于有源层131与控制极132之间的栅绝缘层135，以及，位于控制极132与第一极133和第二极134之间的层间介质层136，栅绝缘层135和层间介质层136上具有连通的第一连接孔和连通的第二连接孔，第一极133(例如漏极)依次通过层间介质层136上的第一连接孔和栅绝缘层135上的第一连接孔与有源层131电连接，第二极134(例如源极)依次通过层间介质层136上的第二连接孔和栅绝缘层135上的第二连接孔与有源层131电连接，第二电极123在衬底基板11上的正投影覆盖有源层131在衬底基板11上的正投影。其中，有源层131可以为Oxide有源层、a-Si有源层或p-Si有源层，Oxide有源层例如IGZO有源层或ITZO有源层，有源层131上与第一极133和第二极134连接的部位均进行了导体化处理；栅绝缘层135的材料可以为SiO 2、SiOx、SiNx、Al 2O 3或SiOxNx等透明绝缘材料，栅绝缘层135可以为单层或多层结构，栅绝缘层135的厚度的取值范围可以为80nm～150nm；控制极132的材料可以为金属Mo、金属Cu、金属Al、金属Au及其合金材料，控制极132的厚度的取值范围可以为200nm～400nm；层间介质层136的材料可以为SiO 2、SiOx、SiNx、Al 2O 3或SiOxNx等透明绝缘材料，层间介质层136可以为单层或多层结构，层间介质层136的厚度的取值范围可以为80nm～150nm；第一极133的材料和第二极134的材料均可以为金属Mg、金属Ag、属Mo、金属Cu、金属Al、金属Au及其合金材料，第一极133的厚度和第二极134的厚度的取值范围可以为200nm～400nm。
示例地，在绝缘层15远离光检测单元12的一侧形成开关单元13可以包括如下六个步骤：
步骤(1)、通过磁控溅射、热蒸发或者PECVD等工艺中的任一种在绝缘层15远离光检测单元12的一侧形成IGZO材质层，通过一次构图工艺对IGZO材质层进行处理得到有源层131，通过掺杂(英文：doping)、等离子体(英文：plasma)处理或气氛退火等工艺中的任一种对有源层131上用于与第一极和第二极连接的部位进行导体化处理，以增加该部位的载流子浓度，保证该部位和相应电极(例如第一极或第二极)实现欧姆接触。
步骤(2)、通过磁控溅射、热蒸发或者PECVD等工艺中的任一种在有源层131远离光检测单元12的一侧形成厚度在80nm～150nm之间的SiO 2层作为栅绝缘层135。
步骤(3)、通过磁控溅射、热蒸发或者PECVD等工艺中的任一种在栅绝缘层135远离光检测单元12的一侧形成厚度在200nm～400nm之间的金属Mo材质层，通过一次构图工艺对金属Mo材质层进行处理得到控制极132。
步骤(4)、在控制极132远离光检测单元12的一侧形成层间介质层136，层间介质层136的形成过程可以参考栅绝缘层135的形成过程。
步骤(5)、通过一次构图工艺对层间介质层136和栅绝缘层135进行处理，以在层间介质层136和栅绝缘层135上形成连通的第一连接孔和连通的第二连接孔，有源层131上用于与第一极(例如漏极)连接的部位通过第一连接孔露出，用于与第二极(例如源极)连接的部位通过第二连接孔露出。
步骤(6)、通过磁控溅射、热蒸发或者PECVD等工艺中的任一种在层间介质层136远离光检测单元12的一侧形成厚度在200nm～400nm之间的金属Mo材质层，通过一次构图工艺对金属Mo材质层进行处理得到第一极133和第二极134，第一极133依次通过层间介质层136上的第一连接孔和栅绝缘层135上的第一连接孔与有源层131电连接，第二极134依次通过层间介质层136上的第二连接孔和栅绝缘层135上的第二连接孔与有源层131电连接。
在步骤205中、在开关单元远离绝缘层的一侧形成平坦层。
请参考图15，其示出了本申请实施例提供的一种在开关单元13远离绝缘层15的一侧形成平坦层16后的示意图，平坦层16远离开关单元13的一面为平面，平坦层16具有阳极过孔G，开关单元13的第一极133通过该阳极过孔G露出，平坦层16的材料可以为树脂。
示例地，通过磁控溅射、热蒸发或者PECVD等工艺中的任一种在开关单元13远离绝缘层15的一侧形成厚度在2μm～3μm之间的树脂层作为平坦层16。
在步骤206中、在平坦层远离开关单元的一侧形成发光单元和像素界定层，发光单元位于像素界定层限定的像素开口中，发光单元与开关单元电连接，发光单元与光检测单元共用开关单元。
请参考图16，其示出了本申请实施例提供的一种在平坦层16远离开关单元13的一侧形成发光单元14和像素界定层17后的示意图，发光单元14位于像素界定层17限定的像素开口K中，发光单元14包括沿远离衬底基板11的方向依 次叠加的阳极141、电致发光层142和阴极143，阳极141通过平坦层16上的阳极过孔G与第一极133电连接。其中，阳极141的材料可以为金属Mg、金属Ag、金属Mo、金属Cu、金属Al、金属Au及其合金材料，电致发光层142的材料可以为电致发光材料，阴极143的材料可以为ITO、IZO、金属Ag等导电材料，例如，阴极143为ITO/Ag/ITO的多层结构，其中ITO膜层的厚度为8nm，Ag膜层的厚度为100nm，像素界定层17的材料可以为疏液性较强的树脂。
示例地，在平坦层16远离开关单元13的一侧形成发光单元14和像素界定层17可以包括如下四个步骤：
步骤(1)、通过磁控溅射、热蒸发或者PECVD等工艺中的任一种在平坦层16远离开关单元13的一侧沉积一层镁银合金得到合金材质层，通过一次构图工艺对该合金材质层进行处理得到阳极141，阳极141通过阳极过孔G与第一极133电连接。
步骤(2)、通过磁控溅射、热蒸发或者PECVD等工艺中的任一种在阳极141远离第一极133的一侧沉积一层树脂得到树脂材质层，通过一次构图工艺对该树脂材质层进行处理得到像素界定层17，阳极141的侧面位于像素界定层17内，阳极141的上表面通过像素开口K部分露出。
步骤(3)、通过喷墨打印工艺在像素开口K中形成打印一层电致发光材料，并对打印的电致发光材料进行干燥处理得到电致发光层142。
步骤(4)、通过磁控溅射、热蒸发或者PECVD等工艺中的任一种在电致发光层142远离阳极141的一侧形成依次叠加的ITO材质层、Ag材质层和ITO材质层，ITO材质层的厚度可以为8nm，Ag材质层的厚度可以为100nm，通过一次构图工艺对ITO材质层、Ag材质层和ITO材质层进行处理得到阴极143。
在步骤207中、在发光单元远离平坦层的一侧形成封装层。
在发光单元14远离平坦层16的一侧形成封装层18后的示意图可以参考图4，封装层18覆盖发光单元14以及像素界定层17。封装层18可以为TFE层或封装盖板，TFE层包括交替叠加的无机层和有机层，无机层的材料可以为SiO 2、SiOx、SiNx、Al 2O 3或SiOxNx等透明绝缘材料，有机层的材料可以为有机树脂，封装盖板可以是采用玻璃等材料制备的盖板。
示例地，以封装层18是TFE层为例，在发光单元14远离平坦层16的一侧形成封装层18可以包括：通过磁控溅射、热蒸发或者PECVD等工艺中的任一种在发光单元14远离平坦层16的一侧形成沉积一层SiOx得到SiOx材质层， 通过一次构图工艺对SiOx材质层进行处理得到无机层；通过喷墨打印工艺在无机层远离平坦层16的一侧打印一层有机树脂，并对打印的有机树脂进行干燥处理得到有机层，从而得到封装层。
本申请实施例所涉及的一次构图工艺包括光刻胶涂覆、曝光、显影、刻蚀和光刻胶剥离，通过一次构图工艺对材质层(例如ITO材质层)进行处理包括：在材质层(例如ITO材质层)上涂覆一层光刻胶形成光刻胶层，采用掩膜版对光刻胶层进行曝光，使得光刻胶层形成完全曝光区和非曝光区，之后采用显影工艺处理，使完全曝光区的光刻胶被完全去除，非曝光区的光刻胶全部保留，采用刻蚀工艺对材质层(例如ITO材质层)上完全曝光区对应的区域进行刻蚀，最后剥离非曝光区的光刻胶得到相应的结构(例如第一电极121)。这里是以光刻胶为正性光刻胶为例进行说明的，当光刻胶为负性光刻胶时，一次构图工艺的过程可以参考本段的描述，本申请实施例在此不再赘述。
本申请实施例提供的阵列基板的制造方法步骤的先后顺序可以进行适当调整，步骤也可以根据情况进行相应增减，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化的方法，都应涵盖在本申请的保护范围之内，因此不再赘述。
综上所述，本申请实施例提供的阵列基板的制造方法，由于在像素区中，发光单元与光检测单元共用一个开关单元，因此有助于减少阵列基板上的开关单元的数量，简化阵列基板的结构。本申请实施例提供的阵列基板的制造方法，由于先制作光检测单元而后制作开关单元，因此可以避免制备光检测单元的过程对开关单元的有源层的影响。
下述为本申请的光检测方法的实施例，本申请中光检测方法和原理可以参见下文各实施例中的描述。
请参考图17，其示出了本申请实施例提供的一种光检测方法的方法流程图，该光检测方法可以用于上述实施例提供的阵列基板，该阵列基板的每个像素区中设置有光检测单元、开关单元和发光单元，每个像素区中的光检测单元与该像素区中的发光单元共用该像素区中的开关单元。其中，该光检测单元包括第一电极、感光层和第二电极，该光检测方法可以由光检测组件来执行。参见图17，该方法可以包括如下步骤：
在步骤301中、控制开关单元工作在开启过渡区，开启过渡区为开关单元 的开启区与关闭区之间的区域。
在步骤302中、向光检测单元的第一电极施加电压，使光检测单元的第二电极具有电势，其中，在照射至第一电极的光线的作用下，第二电极的电势变化，引起开关单元的输出电流变化。
在步骤303中、确定开关单元的输出电流的变化量。
在步骤304中、根据开关单元的输出电流的变化量，确定照射至第一电极的光照强度。
可选地，照射至第一电极的光线是经过指纹反射后的光线，在步骤303之后，该方法还包括：根据多个开关单元的输出电流的变化量，进行指纹检测。
综上所述，本申请实施例提供的光检测方法，由于在阵列基板的每个像素区中，发光单元与光检测单元共用一个开关单元，因此有助于减少阵列基板上的开关单元的数量，简化阵列基板的结构。
请参考图18，其示出了本申请实施例提供的另一种光检测方法的方法流程图，该光检测方法可以用于上述实施例提供的阵列基板，该阵列基板的每个像素区中设置有光检测单元、开关单元和发光单元，每个像素区中的光检测单元与该像素区中的发光单元共用该像素区中的开关单元。其中，该光检测单元包括第一电极、感光层和第二电极，该光检测方法可以由光检测组件来执行。参见图18，该方法可以包括如下步骤：
在步骤401中、控制开关单元工作在开启过渡区，开启过渡区为开关单元的开启区与关闭区之间的区域。
可选地，光检测组件可以与开关单元的控制极(例如栅极)电连接，光检测组件可以向开关单元施加控制电压(例如栅电压)，使开关单元工作在开启过渡区。当开关单元工作在开启过渡区时，通过开关单元传输至发光单元的电流不足以使发光单元开启，因此发光单元处于关闭状态，发光单元不发光。其中，开启过渡区为开关单元的开启区与关闭区之间的区域，当开关单元为TFT时，该开启过渡区也即是亚阈值摆幅区。
在步骤402中、向光检测单元的第一电极施加电压，使光检测单元的第二电极具有电势，其中，在照射至第一电极的光线的作用下，第二电极的电势变化，引起开关单元的输出电流变化。
可选地，光检测组件可以与光检测单元的第一电极电连接，光检测组件可 以向光检测单元的第一电极施加电压，向第一电极施加电压后，光检测组件的感光层(例如PIN层)可以累积电荷，使光检测组件的第二电极具有电势。
本申请实施例中，当光线照射到第一电极上时，光检测单元会产生光生偏压，该光生偏压可以使得第二电极的电势变化，第二电极的电势变化会引起开关单元的输出电流变化，具体的原理可以参考图5至图9的相关描述。
可选地，在步骤402之前，可以向光检测单元的第一电极施加正电压使感光层正偏，以去除感光层中的残余电荷，接着再执行该步骤402，以避免感光层中的残余电荷对光检测过程的影响。
在步骤403中、确定开关单元的输出电流的变化量。
可选地，当开关单元为TFT时，开关单元的输出电流也即是开关单元的漏电流。光检测组件可以与开关单元的第一极(也即是漏极)电连接，开关单元的输出电流会通过开关单元的第一极传输至光检测组件，光检测组件可以根据光照之前开关单元的输出电流的大小和光照之后开关单元的输出电流的大小，确定开关单元的输出电流的变化量。
在步骤404中、根据开关单元的输出电流的变化量，确定照射至第一电极的光照强度。
其中，照射至第一电极的光照强度也即是照射至第一电极的光线的强度。
可选地，光检测单元可以维护电流变化量与光照强度的关联关系，光检测单元可以根据开关单元的输出电流的变化量和电流变化量与光照强度的关联关系，确定照射至第一电极的光照强度。
在步骤405中、根据多个开关单元的输出电流的变化量，进行指纹检测。
当手指按压在阵列基板的出光面(例如衬底基板)上时，手指的指纹可以对阵列基板发射出的光线进行反射产生反射光线，反射光线可以射入至少一个像素区的光检测单元，且经过指纹的“脊”和“沟”反射形成的反射光线不同，经过指纹的“脊”和“沟”反射形成的反射光线可以射入不同像素区的光检测单元，引起该不同的像素区的开关单元的输出电流发生变化，该不同的像素区的开关单元的输出电流的变化量不同，因此可以根据不同像素区的开关单元的输出电流的变化量，成像出指纹的“脊”和“沟”的轮廓，从而实现指纹检测。
在本申请实施例中，光检测单元还可以对阵列基板所处环境光进行检测，光检测单元可以将检测到的环境光强度传输至光检测组件，当该阵列基板应用于手机等智能终端时，光检测组件可以根据光检测单元检测到的环境光强度， 调节智能终端的屏幕亮度，实现智能终端对屏幕亮度的自动调节，本申请实施例在此不再赘述。
综上所述，本申请实施例提供的光检测方法，由于在阵列基板的每个像素区中，发光单元与光检测单元共用一个开关单元，因此有助于减少阵列基板上的开关单元的数量，简化阵列基板的结构。
下述为本申请的光检测组件实施例，可以用于执行本申请的光检测方法。对于本申请的光检测组件实施例中未披露的细节，请参照本申请的光检测方法实施例。
请参考图19，其示出了本申请实施例提供的一种光检测组件500的框图，该光检测组件500可以用于执行图17或图18所示实施例提供的光检测方法。参见图19，该光检测组件500可以包括但不限于：
控制模块510，用于控制开关单元工作在开启过渡区，开启过渡区为开关单元的开启区与关闭区之间的区域；
加压模块520，用于向光检测单元的第一电极施加电压，使光检测单元的第二电极具有电势，其中，在照射至第一电极的光线的作用下，第二电极的电势变化，引起开关单元的输出电流变化；
第一确定模块530，用于确定开关单元的输出电流的变化量；
第二确定模块540，用于根据开关单元的输出电流的变化量，确定照射至第一电极的光照强度。
可选地，照射至第一电极的光线是经过指纹反射后的光线，请参考图20，在图19的基础上，该光检测组件500还包括：检测模块550，用于根据多个开关单元的输出电流的变化量，进行指纹检测。
综上所述，本申请实施例提供的光检测组件，由于在阵列基板的每个像素区中，发光单元与光检测单元共用一个开关单元，因此有助于减少阵列基板上的开关单元的数量，简化阵列基板的结构。
基于同样的发明构思，本申请实施例还提供了一种显示装置，该显示装置包括图1至图4所示的阵列基板。可选地，该显示装置还包括图19或图20所示的光检测组件。该显示装置可以为电致发光显示装置，例如，OLED显示装置或QLED显示装置。
其中，该显示装置可以为电子纸、显示基板、显示面板、手表、手环、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。
在本申请中，术语“电连接”指的是连接且能够传输电荷，但不必然有电荷传输，例如，A与B电连接表示A与B连接且A与B之间能够传输电荷，但是A与B之间并不必然有电荷传输。术语“至少一个”表示一个或多个，多个表示两个或两个以上，除非另有明确的限定。术语“第一”、“第二”和“第三”等仅用于描述目的，而不能理解为指示或暗示相对重要性。
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以通过硬件来完成，也可以通过程序来指令相关的硬件完成，所述的程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存储器，磁盘或光盘等。
以上所述仅为本申请的示例性实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (21)

  1. 一种阵列基板，包括：
    衬底基板，所述衬底基板具有像素区；
    位于所述像素区中的光检测单元、开关单元和发光单元，所述光检测单元与所述发光单元共用所述开关单元。
  2. 根据权利要求1所述的阵列基板，其中，
    所述开关单元位于背离所述光检测单元的感光侧的一侧，所述开关单元与所述光检测单元绝缘，所述光检测单元在所述衬底基板上的正投影与所述开关单元在所述衬底基板上的正投影至少部分重叠；
    所述开关单元与所述发光单元电连接。
  3. 根据权利要求2所述的阵列基板，其中，
    所述开关单元在所述衬底基板上的正投影覆盖所述光检测单元在所述衬底基板上的正投影。
  4. 根据权利要求2或3所述的阵列基板，其中，
    所述光检测单元包括沿靠近所述开关单元的方向依次叠加的第一电极、感光层和第二电极；
    所述开关单元包括有源层，以及位于所述有源层远离所述光检测单元的一侧的控制极、第一极和第二极，所述第一极和所述第二极中的一个为源极，另一个为漏极。
  5. 根据权利要求4所述的阵列基板，其中，
    所述第二电极的材料为遮光材料，所述第二电极在所述衬底基板上的正投影与所述有源层在所述衬底基板上的正投影至少部分重叠。
  6. 根据权利要求5所述的阵列基板，其中，
    所述第二电极在所述衬底基板上的正投影覆盖所述有源层在所述衬底基板上的正投影。
  7. 根据权利要求4至6任一项所述的阵列基板，其中，
    所述发光单元为电致发光单元，所述开关单元的所述第一极与所述发光单元的阳极电连接。
  8. 根据权利要求2至7任一项所述的阵列基板，其中，所述阵列基板还包括：
    位于所述光检测单元与所述开关单元之间的绝缘层；
    位于所述开关单元与所述发光单元之间的平坦层；以及，
    位于所述平坦层远离所述开关单元的一侧的像素界定层，所述发光单元位于所述像素界定层限定的像素开口中。
  9. 根据权利要求1至8任一项所述的阵列基板，其中，
    所述光检测单元、所述开关单元和所述发光单元沿远离所述衬底基板的方向依次分布，所述阵列基板还包括：
    位于所述发光单元远离所述衬底基板的一侧的封装层。
  10. 一种光检测方法，用于权利要求1至9任一项所述的阵列基板，所述阵列基板的光检测单元包括第一电极、感光层和第二电极，所述方法包括：
    控制所述开关单元工作在开启过渡区，所述开启过渡区为所述开关单元的开启区与关闭区之间的区域；
    向所述光检测单元的所述第一电极施加电压，使所述光检测单元的所述第二电极具有电势，其中，在照射至所述第一电极的光线的作用下，所述第二电极的电势变化，引起所述开关单元的输出电流变化；
    确定所述开关单元的输出电流的变化量；
    根据所述开关单元的输出电流的变化量，确定照射至所述第一电极的光照强度。
  11. 根据权利要求10所述的方法，其中，
    照射至所述第一电极的光线是经过指纹反射后的光线，在确定所述开关单 元的输出电流的变化量之后，所述方法还包括：
    根据多个所述开关单元的输出电流的变化量，进行指纹检测。
  12. 一种光检测组件，用于权利要求1至9任一项所述的阵列基板，所述阵列基板的光检测单元包括第一电极、感光层和第二电极，所述光检测组件包括：
    控制模块，用于控制所述开关单元工作在开启过渡区，所述开启过渡区为所述开关单元的开启区与关闭区之间的区域；
    加压模块，用于向所述光检测单元的所述第一电极施加电压，使所述光检测单元的所述第二电极具有电势，其中，在照射至所述第一电极的光线的作用下，所述第二电极的电势变化，引起所述开关单元的输出电流变化；
    第一确定模块，用于确定所述开关单元的输出电流的变化量；
    第二确定模块，用于根据所述开关单元的输出电流的变化量，确定照射至所述第一电极的光照强度。
  13. 根据权利要求12所述的光检测组件，其中，照射至所述第一电极的光线是经过指纹反射后的光线，所述光检测组件还包括：
    检测模块，用于根据多个所述开关单元的输出电流的变化量，进行指纹检测。
  14. 一种阵列基板的制造方法，包括：
    提供衬底基板，所述衬底基板具有像素区；
    在所述像素区中形成光检测单元、开关单元和发光单元，所述光检测单元与所述发光单元共用所述开关单元。
  15. 根据权利要求14所述的方法，其中，
    在所述像素区中形成光检测单元、开关单元和发光单元，所述光检测单元与所述发光单元共用所述开关单元，包括：
    在所述像素区中形成光检测单元；
    在所述光检测单元背离所述光检测单元的感光侧的一侧形成开关单元，所 述开关单元与所述光检测单元绝缘，所述光检测单元在所述衬底基板上的正投影与所述开关单元在所述衬底基板上的正投影至少部分重叠；
    在所述开关单元远离所述光检测单元的一侧形成发光单元，所述发光单元与所述开关单元电连接。
  16. 根据权利要求15所述的方法，其中，
    在所述像素区中形成光检测单元，包括：
    在所述像素区中形成沿远离所述衬底基板的方向依次叠加的第一电极、感光层和第二电极；
    在所述光检测单元背离所述光检测单元的感光侧的一侧形成开关单元，包括：
    在所述光检测单元背离所述光检测单元的感光侧的一侧形成有源层；
    在所述有源层远离所述光检测单元的一侧形成控制极、第一极和第二极，所述第一极和所述第二极中的一个为源极，另一个为漏极。
  17. 根据权利要求15或16所述的方法，其中，
    在所述光检测单元背离所述光检测单元的感光侧的一侧形成开关单元之前，所述方法还包括：
    在所述光检测单元背离所述光检测单元的感光侧的一侧形成绝缘层；
    在所述光检测单元背离所述光检测单元的感光侧的一侧形成开关单元，包括：
    在所述绝缘层远离所述光检测单元的一侧形成开关单元。
  18. 根据权利要求15至17任一所述的方法，其中，
    在所述开关单元远离所述光检测单元的一侧形成发光单元之前，所述方法还包括：
    在所述开关单元远离所述光检测单元的一侧形成平坦层；
    在所述开关单元远离所述光检测单元的一侧形成发光单元，包括：
    在所述平坦层远离所述光检测单元的一侧形成发光单元；
    所述方法还包括：
    在所述平坦层远离所述开关单元的一侧形成像素界定层，所述发光单元位于所述像素界定层限定的像素开口中。
  19. 根据权利要求14至18任一项所述的方法，其中，所述方法还包括：
    在所述发光单元远离所述衬底基板的形成封装层。
  20. 一种显示装置，包括：权利要求1至9任一项所述的阵列基板。
  21. 根据权利要求20所述的显示装置，其中，所述显示装置还包括：
    权利要求12或13所述的光检测组件。
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CN109285870A (zh) * 2018-09-28 2019-01-29 京东方科技集团股份有限公司 显示基板及其制备方法、显示面板
CN109801569A (zh) * 2019-03-28 2019-05-24 京东方科技集团股份有限公司 一种阵列基板、其制作方法及显示装置
CN109962114A (zh) * 2019-04-17 2019-07-02 京东方科技集团股份有限公司 双栅tft、像素电路及其控制方法
CN110071164A (zh) * 2019-05-07 2019-07-30 京东方科技集团股份有限公司 一种显示基板及其亮度调节方法、显示装置
CN110164847A (zh) * 2019-05-28 2019-08-23 京东方科技集团股份有限公司 阵列基板、光检测方法及组件、显示装置

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