Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/005—Processes
  • H01L33/0093—Wafer bonding; Removal of the growth substrate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
  • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
  • H01L21/02293—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
  • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/005—Processes
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
  • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
  • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
  • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
  • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
  • H01L2933/0008—Processes
  • H01L2933/0025—Processes relating to coatings

Definitions

• the present invention relates to a method for manufacturing an optoelectronic semiconductor chip, in particular to a bonded wafer suitable for epitaxy.
• Single crystal sapphire, silicon carbide, and gallium arsenide crystals are relatively typical epitaxial materials, have excellent photoelectric effects, and are widely used in LEDs and power devices. Crystals such as sapphire, silicon carbide, and gallium arsenide all consume a lot of electricity when growing. And the larger the wafer size, the lower the yield of the crystal material. The semiconductor substrate wafer gradually transitions from 4 inches to 6 inches or 8 inches, and the cost is relatively high.
• the crystal needs to go through multiple processes such as cutting, grinding, polishing, and cleaning to become a wafer; after epitaxial growth, the entire chip thickness needs to be reduced in the manufacturing process of the chip to reduce the chip size.
• the thickness of the chip is usually less than 1/3 of the wafer, that is to say, more than half of the crystals have to be grinded with a thinner at the end, and the crystal material is wasted greatly.
• the thickness of the wafer is one of the key factors affecting the uniformity of the epitaxial wavelength.
• the thicker the thickness the more it can reduce the warpage caused by the stress of the epitaxial layer, thereby improving the wavelength uniformity; in order to reduce the chip size and reduce the waste of packaging materials
• a thinner wafer substrate thickness is required.
• the thicker the wafer the more cost to thin the chip manufacturing process, which has a lot of waste of crystal materials.
• the present invention provides a solution to the technical problem in the background art.
• the present invention discloses a method for manufacturing an optoelectronic semiconductor chip.
• the original growth substrate is divided into a mother wafer and a daughter wafer.
• the round and sub-wafers include sapphire, silicon carbide or gallium arsenide.
• Choose the appropriate bonding medium in the mother wafer, daughter wafer A layer of bonding medium film is grown on the circle or both, preferably a layer of bonding medium is grown on the surface of one of them, and it is especially recommended to grow the bonding medium on the mother wafer as an intermediate layer.
• the intermediate layer includes one or any combination of silicon dioxide, aluminum nitride, and gallium nitride.
• the bonding design performs the bonding of the mother and daughter wafers in a vacuum high temperature environment of 300°C to 1000°C, and the bonding medium is located on the bonding surface.
• the thinner daughter wafer can be non-destructively debonded after the semiconductor epitaxy process is processed, the bonding medium can be destroyed and separated, and the daughter wafer separated from the mother wafer and the semiconductor epitaxial layer on the daughter wafer continue to be processed Chip manufacturing process; the thicker mother wafer below can be annealed at a high temperature after cleaning to release the stress accumulated by epitaxial growth, and the annealed mother wafer can be recycled.
• the thickness of the daughter wafer can be designed according to the final chip thickness, and the thickness of the daughter wafer can be slightly later than or equal to the thickness of the final chip substrate.
• the original wafer thickness specification minus the daughter wafer thickness is the minimum mother wafer thickness.
• the surface of the mother wafer should be a wafer with rough surfaces on both sides. High-hardness micropowders such as silicon carbide, boron carbide, silicon carbide, etc.
• the reagents for activation treatment include hydrogen peroxide, ammonia or a mixture of both.
• the activation treatment can also be a dry treatment, such as activation by plasma.
• the bonding medium can be a thin film of silicon dioxide (SiO2), aluminum nitride (AlN), etc., and the intermediate layer composed of the bonding medium needs to have a certain thickness to be uniformly bonded, for example, 3 to 5 pm, It can resist the bending caused by the high temperature of 1000°C and the stress of the epitaxial layer during epitaxial growth.
• the aforementioned bonding conditions need to be performed on high-temperature, vacuum bonding equipment.
• the non-destructive debonding method is an acid corrosion method, which corrodes the bonding medium and does not damage the wafer.
• the recycling of the mother wafer requires cleaning, annealing and other processes to eliminate the stress of the epitaxy, and the mother wafer is relatively flat, which is conducive to reuse.
• the thickness of the daughter wafer is 50-40 ⁇ m thicker than the final chip, and some space for thinning adjustment is reserved.
• the side of the daughter wafer away from the epitaxial layer can be reduced.
• the thickness of the mother wafer can be slightly thicker than the minimum mother wafer thickness by 100 ⁇ 1000— to reserve a processing window.
• the thickness of the daughter wafer is 100 ⁇ 45(Vm )
• the thickness of the mother wafer is 300 ⁇ 150(Vm
• the polished roughness of the front side of the daughter wafer is 0.08 ⁇ 0.2nm; the roughness of the back side of the daughter wafer and the mother wafer is 0.1 ⁇ 1.2 [xm
• the thickness of the intermediate layer composed of the bonding medium is 3 ⁇ 5um
• the bonding conditions are 300 to 400° C. in a vacuum environment, and the mother wafer and the daughter wafer are bonded at a pressure of 100 to 250 kg/cm 2 for 10 to 40 minutes.
• the debonding method is normal temperature hydrofluoric acid (HF) corrosion of the silicon oxide bonding medium.
• HF normal temperature hydrofluoric acid
• the method for reusing the mother wafer is cleaning with ultrasonic clean water, spin-drying, and then placing it in a high temperature annealing furnace at 1350 to 1400°C for annealing to release residual stress in epitaxial production.
• the mother wafer may include a first mother wafer and a second mother wafer, or consist of two or more separable wafers.
• the present invention divides the traditional wafer into a mother wafer and a daughter wafer, and after the mother wafer and the daughter wafer are bonded by an appropriate bonding technology, they can withstand the high temperature and stress generated by an external delay of about 1000°C. Warpage changes; use non-physical destruction methods to release the bond after epitaxy.
• the mother wafer can be recycled.
• the daughter wafer and the epitaxial layer are directly used in the chip manufacturing process. There is no need to thin or a small amount of thinning, which solves the problem of the raw material and chip processing cost of large-size epitaxial wafers, and obtains better wavelength uniformity Of epitaxial wafers.
• the thickness of the mother wafer can be appropriately increased to maintain the stability of mass production, such as reducing the warpage problem during epitaxial growth, thereby improving the uniformity of epitaxial growth, and will not significantly increase production costs.
• the mass production and manufacturing of large-size wafers has far-reaching significance.
• FIG. 1 is a manufacturing process flow of a bonded wafer
• FIGS. 2-7 are schematic diagrams of the manufacturing process of optoelectronic semiconductor products and corresponding bonded wafer photos.
• the present invention provides a method for manufacturing optoelectronic semiconductor chips for manufacturing low-cost, high-performance, and environmentally friendly wafers.
• the method for large-size sapphire, carbonization Silicon or gallium arsenide wafers are extremely cost-effective.
• the method includes the steps of: providing a mother wafer 100 and a daughter wafer 200 of the same material or different materials, evaporating a dielectric layer on one side of the mother wafer 100 and the daughter wafer 200, the dielectric layer has bonding characteristics, and the dielectric layer is used as an intermediate layer 300. After the dielectric layer is polished and cleaned, the intermediate layer 300 is activated with ammonia and hydrogen peroxide.
• the purpose of the activation treatment is to promote the formation of hydroxyl groups (-OH) on the surface of the intermediate layer 300.
• the hydroxyl groups form a coulomb for A1 or 0 of the wafer material. Pulling force, favorable
• the mother wafer and the daughter wafer are connected in the intermediate layer, the mother wafer 100 and the daughter wafer 200 are pre-aligned, aligned with each other, and the thermocompression bonding process is performed to obtain the bonded wafer, and the bonded wafer is inspected and cleaned .
• a mother wafer 100 and a daughter wafer 200 are provided, and the material selection of the two includes but not limited to: sapphire, silicon carbide or gallium arsenide, in order to perform subsequent high temperature bonding
• the high-temperature environment temperature that the wafer material can withstand should not be less than 1000°C.
• the intermediate layer 300 is provided between the two.
• the non-smooth surface 110 of the mother wafer 100 and the daughter wafer 200 is relatively non-smooth surface 100 by vapor deposition bonding dielectric material 310 2 to make an intermediate layer 300 (not shown in the intermediate layer diagram), and CMP (mechanical chemical polishing) is performed on the intermediate layer 300, because SiO 2 is deposited by vapor deposition
• CMP mechanical chemical polishing
• polishing needs to be used to improve the flatness of the intermediate layer, and then after the two results are activated, the side with the intermediate layer 300 is faced to undergo a bonding process.
• the thickness of the mother wafer 100 is 30 (Vm to 50 (Vm).
• the thickness of the mother wafer 100 has a tendency to increase with the increase of the wafer area.
• the thickness of the mother wafer 100 may reach 150 ⁇ m
• the thickness of the daughter wafer 200 may be 10 ⁇ m to 450 mm.
• the daughter wafer 200 under the concept of the present invention can reach at least 100 ⁇ m.
• a suitable bonding medium needs to have a high lattice match with the wafer material, such as one or any combination of silicon dioxide (SiO 2 ), aluminum nitride (AlN), gallium nitride (GaN) and other thin films.
• Mother wafer or film may be grown on the mother wafer 100 and wafer 200 are sub-film growth, do bonded at a suitable temperature and pressure.
• the roughness of the surface of the mother wafer 100 and the daughter wafer 200 opposite to each other will also affect the bonding effect.
• the coarser the surface of the wafer the denser the bonding medium grows; however, the roughness is too large, and holes are prone to appear, which affects the bonding effect.
• the roughness is controlled at 0.1-1.2 pm.
• the size of the mother wafer 100 and the daughter wafer 200 need to be the same, and the diameter should be within ⁇ 0.1 mm to facilitate the alignment of the mother wafer 100 and the daughter wafer 200 during bonding.
• Sapphire wafers for LEDs need to be exposed, developed, and etched to produce patterns (Patterned Sapphire Substrate, PSS) on the sub-wafer 200
• PSS Powerned Sapphire Substrate
• the patterned substrate can effectively improve the light-emitting efficiency of the light-emitting semiconductor device in terms of reflection and epitaxial lattice matching. In the process of wafer bonding, it is recommended to avoid damage to the pattern by the pressure during bonding before making the above-mentioned patterns.
• the bonding is debonded by acid etching the bonding medium.
• hydrofluoric acid is used to corrode the bonding medium silicon oxide. After 40 minutes of soaking in hydrofluoric acid at room temperature, it can be easily separated without affecting the semiconductor.
• the epitaxial layer of the device and the wafer body is formed by a tool in a low temperature environment. This type of damage will produce many chipping corners, and the reuse rate of the mother wafer 100 will decrease.
• the bonding is debonded by acid etching the bonding medium. Taking the sapphire wafer as an example, hydrofluoric acid is used to corrode the bonding medium silicon oxide. After 40 minutes of soaking in hydrofluoric acid at room temperature, it can be easily separated without affecting the semiconductor. The epitaxial layer of the device and the wafer body.
• the sub-wafer 200 is used for making an epitaxial layer, and a smooth surface is provided on the side of the sub-wafer 200 away from the bonding surface for making an epitaxial layer 210.
• the epitaxial layer includes an N-side layer and a P-side layer.
• the active layer located between the two, for example, a semiconductor material by MOCVD metal organic chemical vapor deposition.
• the intermediate layer 300 is unwound, and the mother wafer 100 and the daughter wafer 200 are separated.
• the sub-wafer 200 continues the chip manufacturing process, for example, using photoresist etching to make a chip pattern on the side of the epitaxial layer 210 away from the sub-wafer 200, remove part of the P-side layer until the N-side layer is exposed, and then add the P-side layer and /Or an insulating protective layer or a transparent conductive diffusion layer is fabricated on the surface of the exposed N-side layer, and finally chip electrodes connected to the P-side layer and the exposed N-side layer are fabricated to form a light-emitting semiconductor chip structure.
• the separated mother wafer 100 can be annealed at a high temperature and then recycled again to make a bonded wafer again.
• the sub-wafer 200 is thinned to meet the chip process requirements.
• the thinning thickness of the sub-wafer 200 of the present invention can be significantly lower than the thinning thickness of the substrate in the prior art. Taking a 75 ⁇ m thickness wafer substrate as an example, the present invention only needs to remove about 200 [ xm wafers Materials can be used to obtain a 100 [ xm chip substrate wafer, and as a comparison, 5 see the technology needs to remove 65 (Vm, the amount of removal is more than 3 times that of the present invention.
• the cost The invention saves production costs, shortens the thinning time, and also reduces the industrial waste generated, and plays a positive role in promoting the industrialization of large wafers with sizes of six inches and above, for example.
• the mother wafer 100 may be further designed to include a bonding composition of a first mother wafer and a second mother wafer according to actual needs of thickness, so that it can be removed one by one to control the wafer The thickness of the substrate is controlled.

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• 2019
  • 2019-04-19 WO PCT/CN2019/083521 patent/WO2020211089A1/zh active Application Filing
  • 2019-04-19 KR KR1020217027188A patent/KR20210120058A/ko not_active IP Right Cessation
  • 2019-04-19 CN CN201980004714.0A patent/CN111183513A/zh active Pending
• 2020
  • 2020-01-22 TW TW109102559A patent/TWI734359B/zh active

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