CN111183513A - 一种用于制作光电半导体芯片的方法及其所使用的键合晶圆 - Google Patents

一种用于制作光电半导体芯片的方法及其所使用的键合晶圆 Download PDF

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Publication number
CN111183513A
CN111183513A CN201980004714.0A CN201980004714A CN111183513A CN 111183513 A CN111183513 A CN 111183513A CN 201980004714 A CN201980004714 A CN 201980004714A CN 111183513 A CN111183513 A CN 111183513A
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CN
China
Prior art keywords
wafer
sub
mother
optoelectronic semiconductor
recited
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Pending
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CN201980004714.0A
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English (en)
Chinese (zh)
Inventor
谢斌晖
陈铭欣
萧尊贺
郑贤良
宋志棠
刘卫丽
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Fujian Jingan Optoelectronics Co Ltd
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Fujian Jingan Optoelectronics Co Ltd
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Publication date
Application filed by Fujian Jingan Optoelectronics Co Ltd filed Critical Fujian Jingan Optoelectronics Co Ltd
Publication of CN111183513A publication Critical patent/CN111183513A/zh
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0093Wafer bonding; Removal of the growth substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02293Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008Processes
    • H01L2933/0025Processes relating to coatings

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Recrystallisation Techniques (AREA)
  • Led Devices (AREA)
CN201980004714.0A 2019-04-19 2019-04-19 一种用于制作光电半导体芯片的方法及其所使用的键合晶圆 Pending CN111183513A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2019/083521 WO2020211089A1 (zh) 2019-04-19 2019-04-19 一种用于制作光电半导体芯片的方法及其所使用的键合晶圆

Publications (1)

Publication Number Publication Date
CN111183513A true CN111183513A (zh) 2020-05-19

Family

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Family Applications (1)

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CN201980004714.0A Pending CN111183513A (zh) 2019-04-19 2019-04-19 一种用于制作光电半导体芯片的方法及其所使用的键合晶圆

Country Status (4)

Country Link
KR (1) KR20210120058A (ko)
CN (1) CN111183513A (ko)
TW (1) TWI734359B (ko)
WO (1) WO2020211089A1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111952151A (zh) * 2020-07-28 2020-11-17 苏州赛万玉山智能科技有限公司 半导体复合晶圆及制造方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102601702B1 (ko) * 2022-10-31 2023-11-13 웨이브로드 주식회사 반도체 성장용 템플릿을 이용한 반도체 발광 소자 제조 방법
KR102649711B1 (ko) * 2022-12-02 2024-03-20 웨이브로드 주식회사 초박형 반도체 다이의 제조 방법

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6281032B1 (en) * 1998-04-22 2001-08-28 Sony Corporation Manufacturing method for nitride III-V compound semiconductor device using bonding
US20040029358A1 (en) * 2002-08-10 2004-02-12 Park Jea-Gun Method of fabricating nano SOI wafer and nano SOI wafer fabricated by the same
TW200849337A (en) * 2007-06-06 2008-12-16 Soitec Silicon On Insulator Process for fabricating a structure for epitaxy without an exclusion zone
KR20100033641A (ko) * 2008-09-22 2010-03-31 주식회사 동부하이텍 반도체 소자의 웨이퍼 재활용 방법
CN102956762A (zh) * 2011-08-26 2013-03-06 郑朝元 Ⅲ-ⅴ族晶圆可重复进行磊晶制程的方法与构造
CN103165625A (zh) * 2011-12-15 2013-06-19 电力集成公司 用于制造半导体器件的复合晶圆
US9761493B2 (en) * 2014-01-24 2017-09-12 Rutgers, The State University Of New Jersey Thin epitaxial silicon carbide wafer fabrication

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6689669B2 (en) * 2001-11-03 2004-02-10 Kulite Semiconductor Products, Inc. High temperature sensors utilizing doping controlled, dielectrically isolated beta silicon carbide (SiC) sensing elements on a specifically selected high temperature force collecting membrane
CN102486992A (zh) * 2010-12-01 2012-06-06 比亚迪股份有限公司 一种半导体器件的制造方法
CN102184882A (zh) * 2011-04-07 2011-09-14 中国科学院微电子研究所 一种形成复合功能材料结构的方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6281032B1 (en) * 1998-04-22 2001-08-28 Sony Corporation Manufacturing method for nitride III-V compound semiconductor device using bonding
US20040029358A1 (en) * 2002-08-10 2004-02-12 Park Jea-Gun Method of fabricating nano SOI wafer and nano SOI wafer fabricated by the same
TW200849337A (en) * 2007-06-06 2008-12-16 Soitec Silicon On Insulator Process for fabricating a structure for epitaxy without an exclusion zone
KR20100033641A (ko) * 2008-09-22 2010-03-31 주식회사 동부하이텍 반도체 소자의 웨이퍼 재활용 방법
CN102956762A (zh) * 2011-08-26 2013-03-06 郑朝元 Ⅲ-ⅴ族晶圆可重复进行磊晶制程的方法与构造
CN103165625A (zh) * 2011-12-15 2013-06-19 电力集成公司 用于制造半导体器件的复合晶圆
US20130157440A1 (en) * 2011-12-15 2013-06-20 Power Integrations, Inc. Composite wafer for fabrication of semiconductor devices
US9761493B2 (en) * 2014-01-24 2017-09-12 Rutgers, The State University Of New Jersey Thin epitaxial silicon carbide wafer fabrication

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111952151A (zh) * 2020-07-28 2020-11-17 苏州赛万玉山智能科技有限公司 半导体复合晶圆及制造方法

Also Published As

Publication number Publication date
TW202039945A (zh) 2020-11-01
KR20210120058A (ko) 2021-10-06
WO2020211089A1 (zh) 2020-10-22
TWI734359B (zh) 2021-07-21

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Application publication date: 20200519