WO2020211089A1 - Method for preparing optoelectronic semiconductor chip and bonding wafer used therein - Google Patents

Method for preparing optoelectronic semiconductor chip and bonding wafer used therein Download PDF

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Publication number
WO2020211089A1
WO2020211089A1 PCT/CN2019/083521 CN2019083521W WO2020211089A1 WO 2020211089 A1 WO2020211089 A1 WO 2020211089A1 CN 2019083521 W CN2019083521 W CN 2019083521W WO 2020211089 A1 WO2020211089 A1 WO 2020211089A1
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WIPO (PCT)
Prior art keywords
wafer
optoelectronic semiconductor
mother
semiconductor chips
daughter
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PCT/CN2019/083521
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French (fr)
Chinese (zh)
Inventor
谢斌晖
陈铭欣
萧尊贺
郑贤良
宋志棠
刘卫丽
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福建晶安光电有限公司
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Application filed by 福建晶安光电有限公司 filed Critical 福建晶安光电有限公司
Priority to KR1020217027188A priority Critical patent/KR20210120058A/en
Priority to CN201980004714.0A priority patent/CN111183513A/en
Priority to PCT/CN2019/083521 priority patent/WO2020211089A1/en
Priority to TW109102559A priority patent/TWI734359B/en
Publication of WO2020211089A1 publication Critical patent/WO2020211089A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02293—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0025—Processes relating to coatings

Definitions

  • the present invention relates to a method for manufacturing an optoelectronic semiconductor chip, in particular to a bonded wafer suitable for epitaxy.
  • Single crystal sapphire, silicon carbide, and gallium arsenide crystals are relatively typical epitaxial materials, have excellent photoelectric effects, and are widely used in LEDs and power devices. Crystals such as sapphire, silicon carbide, and gallium arsenide all consume a lot of electricity when growing. And the larger the wafer size, the lower the yield of the crystal material. The semiconductor substrate wafer gradually transitions from 4 inches to 6 inches or 8 inches, and the cost is relatively high.
  • the crystal needs to go through multiple processes such as cutting, grinding, polishing, and cleaning to become a wafer; after epitaxial growth, the entire chip thickness needs to be reduced in the manufacturing process of the chip to reduce the chip size.
  • the thickness of the chip is usually less than 1/3 of the wafer, that is to say, more than half of the crystals have to be grinded with a thinner at the end, and the crystal material is wasted greatly.
  • the thickness of the wafer is one of the key factors affecting the uniformity of the epitaxial wavelength.
  • the thicker the thickness the more it can reduce the warpage caused by the stress of the epitaxial layer, thereby improving the wavelength uniformity; in order to reduce the chip size and reduce the waste of packaging materials
  • a thinner wafer substrate thickness is required.
  • the thicker the wafer the more cost to thin the chip manufacturing process, which has a lot of waste of crystal materials.
  • the present invention provides a solution to the technical problem in the background art.
  • the present invention discloses a method for manufacturing an optoelectronic semiconductor chip.
  • the original growth substrate is divided into a mother wafer and a daughter wafer.
  • the round and sub-wafers include sapphire, silicon carbide or gallium arsenide.
  • Choose the appropriate bonding medium in the mother wafer, daughter wafer A layer of bonding medium film is grown on the circle or both, preferably a layer of bonding medium is grown on the surface of one of them, and it is especially recommended to grow the bonding medium on the mother wafer as an intermediate layer.
  • the intermediate layer includes one or any combination of silicon dioxide, aluminum nitride, and gallium nitride.
  • the bonding design performs the bonding of the mother and daughter wafers in a vacuum high temperature environment of 300°C to 1000°C, and the bonding medium is located on the bonding surface.
  • the thinner daughter wafer can be non-destructively debonded after the semiconductor epitaxy process is processed, the bonding medium can be destroyed and separated, and the daughter wafer separated from the mother wafer and the semiconductor epitaxial layer on the daughter wafer continue to be processed Chip manufacturing process; the thicker mother wafer below can be annealed at a high temperature after cleaning to release the stress accumulated by epitaxial growth, and the annealed mother wafer can be recycled.
  • the thickness of the daughter wafer can be designed according to the final chip thickness, and the thickness of the daughter wafer can be slightly later than or equal to the thickness of the final chip substrate.
  • the original wafer thickness specification minus the daughter wafer thickness is the minimum mother wafer thickness.
  • the surface of the mother wafer should be a wafer with rough surfaces on both sides. High-hardness micropowders such as silicon carbide, boron carbide, silicon carbide, etc.
  • the reagents for activation treatment include hydrogen peroxide, ammonia or a mixture of both.
  • the activation treatment can also be a dry treatment, such as activation by plasma.
  • the bonding medium can be a thin film of silicon dioxide (SiO2), aluminum nitride (AlN), etc., and the intermediate layer composed of the bonding medium needs to have a certain thickness to be uniformly bonded, for example, 3 to 5 pm, It can resist the bending caused by the high temperature of 1000°C and the stress of the epitaxial layer during epitaxial growth.
  • the aforementioned bonding conditions need to be performed on high-temperature, vacuum bonding equipment.
  • the non-destructive debonding method is an acid corrosion method, which corrodes the bonding medium and does not damage the wafer.
  • the recycling of the mother wafer requires cleaning, annealing and other processes to eliminate the stress of the epitaxy, and the mother wafer is relatively flat, which is conducive to reuse.
  • the thickness of the daughter wafer is 50-40 ⁇ m thicker than the final chip, and some space for thinning adjustment is reserved.
  • the side of the daughter wafer away from the epitaxial layer can be reduced.
  • the thickness of the mother wafer can be slightly thicker than the minimum mother wafer thickness by 100 ⁇ 1000— to reserve a processing window.
  • the thickness of the daughter wafer is 100 ⁇ 45(Vm )
  • the thickness of the mother wafer is 300 ⁇ 150(Vm
  • the polished roughness of the front side of the daughter wafer is 0.08 ⁇ 0.2nm; the roughness of the back side of the daughter wafer and the mother wafer is 0.1 ⁇ 1.2 [xm
  • the thickness of the intermediate layer composed of the bonding medium is 3 ⁇ 5um
  • the bonding conditions are 300 to 400° C. in a vacuum environment, and the mother wafer and the daughter wafer are bonded at a pressure of 100 to 250 kg/cm 2 for 10 to 40 minutes.
  • the debonding method is normal temperature hydrofluoric acid (HF) corrosion of the silicon oxide bonding medium.
  • HF normal temperature hydrofluoric acid
  • the method for reusing the mother wafer is cleaning with ultrasonic clean water, spin-drying, and then placing it in a high temperature annealing furnace at 1350 to 1400°C for annealing to release residual stress in epitaxial production.
  • the mother wafer may include a first mother wafer and a second mother wafer, or consist of two or more separable wafers.
  • the present invention divides the traditional wafer into a mother wafer and a daughter wafer, and after the mother wafer and the daughter wafer are bonded by an appropriate bonding technology, they can withstand the high temperature and stress generated by an external delay of about 1000°C. Warpage changes; use non-physical destruction methods to release the bond after epitaxy.
  • the mother wafer can be recycled.
  • the daughter wafer and the epitaxial layer are directly used in the chip manufacturing process. There is no need to thin or a small amount of thinning, which solves the problem of the raw material and chip processing cost of large-size epitaxial wafers, and obtains better wavelength uniformity Of epitaxial wafers.
  • the thickness of the mother wafer can be appropriately increased to maintain the stability of mass production, such as reducing the warpage problem during epitaxial growth, thereby improving the uniformity of epitaxial growth, and will not significantly increase production costs.
  • the mass production and manufacturing of large-size wafers has far-reaching significance.
  • FIG. 1 is a manufacturing process flow of a bonded wafer
  • FIGS. 2-7 are schematic diagrams of the manufacturing process of optoelectronic semiconductor products and corresponding bonded wafer photos.
  • the present invention provides a method for manufacturing optoelectronic semiconductor chips for manufacturing low-cost, high-performance, and environmentally friendly wafers.
  • the method for large-size sapphire, carbonization Silicon or gallium arsenide wafers are extremely cost-effective.
  • the method includes the steps of: providing a mother wafer 100 and a daughter wafer 200 of the same material or different materials, evaporating a dielectric layer on one side of the mother wafer 100 and the daughter wafer 200, the dielectric layer has bonding characteristics, and the dielectric layer is used as an intermediate layer 300. After the dielectric layer is polished and cleaned, the intermediate layer 300 is activated with ammonia and hydrogen peroxide.
  • the purpose of the activation treatment is to promote the formation of hydroxyl groups (-OH) on the surface of the intermediate layer 300.
  • the hydroxyl groups form a coulomb for A1 or 0 of the wafer material. Pulling force, favorable
  • the mother wafer and the daughter wafer are connected in the intermediate layer, the mother wafer 100 and the daughter wafer 200 are pre-aligned, aligned with each other, and the thermocompression bonding process is performed to obtain the bonded wafer, and the bonded wafer is inspected and cleaned .
  • a mother wafer 100 and a daughter wafer 200 are provided, and the material selection of the two includes but not limited to: sapphire, silicon carbide or gallium arsenide, in order to perform subsequent high temperature bonding
  • the high-temperature environment temperature that the wafer material can withstand should not be less than 1000°C.
  • the intermediate layer 300 is provided between the two.
  • the non-smooth surface 110 of the mother wafer 100 and the daughter wafer 200 is relatively non-smooth surface 100 by vapor deposition bonding dielectric material 310 2 to make an intermediate layer 300 (not shown in the intermediate layer diagram), and CMP (mechanical chemical polishing) is performed on the intermediate layer 300, because SiO 2 is deposited by vapor deposition
  • CMP mechanical chemical polishing
  • polishing needs to be used to improve the flatness of the intermediate layer, and then after the two results are activated, the side with the intermediate layer 300 is faced to undergo a bonding process.
  • the thickness of the mother wafer 100 is 30 (Vm to 50 (Vm).
  • the thickness of the mother wafer 100 has a tendency to increase with the increase of the wafer area.
  • the thickness of the mother wafer 100 may reach 150 ⁇ m
  • the thickness of the daughter wafer 200 may be 10 ⁇ m to 450 mm.
  • the daughter wafer 200 under the concept of the present invention can reach at least 100 ⁇ m.
  • a suitable bonding medium needs to have a high lattice match with the wafer material, such as one or any combination of silicon dioxide (SiO 2 ), aluminum nitride (AlN), gallium nitride (GaN) and other thin films.
  • Mother wafer or film may be grown on the mother wafer 100 and wafer 200 are sub-film growth, do bonded at a suitable temperature and pressure.
  • the roughness of the surface of the mother wafer 100 and the daughter wafer 200 opposite to each other will also affect the bonding effect.
  • the coarser the surface of the wafer the denser the bonding medium grows; however, the roughness is too large, and holes are prone to appear, which affects the bonding effect.
  • the roughness is controlled at 0.1-1.2 pm.
  • the size of the mother wafer 100 and the daughter wafer 200 need to be the same, and the diameter should be within ⁇ 0.1 mm to facilitate the alignment of the mother wafer 100 and the daughter wafer 200 during bonding.
  • Sapphire wafers for LEDs need to be exposed, developed, and etched to produce patterns (Patterned Sapphire Substrate, PSS) on the sub-wafer 200
  • PSS Powerned Sapphire Substrate
  • the patterned substrate can effectively improve the light-emitting efficiency of the light-emitting semiconductor device in terms of reflection and epitaxial lattice matching. In the process of wafer bonding, it is recommended to avoid damage to the pattern by the pressure during bonding before making the above-mentioned patterns.
  • the bonding is debonded by acid etching the bonding medium.
  • hydrofluoric acid is used to corrode the bonding medium silicon oxide. After 40 minutes of soaking in hydrofluoric acid at room temperature, it can be easily separated without affecting the semiconductor.
  • the epitaxial layer of the device and the wafer body is formed by a tool in a low temperature environment. This type of damage will produce many chipping corners, and the reuse rate of the mother wafer 100 will decrease.
  • the bonding is debonded by acid etching the bonding medium. Taking the sapphire wafer as an example, hydrofluoric acid is used to corrode the bonding medium silicon oxide. After 40 minutes of soaking in hydrofluoric acid at room temperature, it can be easily separated without affecting the semiconductor. The epitaxial layer of the device and the wafer body.
  • the sub-wafer 200 is used for making an epitaxial layer, and a smooth surface is provided on the side of the sub-wafer 200 away from the bonding surface for making an epitaxial layer 210.
  • the epitaxial layer includes an N-side layer and a P-side layer.
  • the active layer located between the two, for example, a semiconductor material by MOCVD metal organic chemical vapor deposition.
  • the intermediate layer 300 is unwound, and the mother wafer 100 and the daughter wafer 200 are separated.
  • the sub-wafer 200 continues the chip manufacturing process, for example, using photoresist etching to make a chip pattern on the side of the epitaxial layer 210 away from the sub-wafer 200, remove part of the P-side layer until the N-side layer is exposed, and then add the P-side layer and /Or an insulating protective layer or a transparent conductive diffusion layer is fabricated on the surface of the exposed N-side layer, and finally chip electrodes connected to the P-side layer and the exposed N-side layer are fabricated to form a light-emitting semiconductor chip structure.
  • the separated mother wafer 100 can be annealed at a high temperature and then recycled again to make a bonded wafer again.
  • the sub-wafer 200 is thinned to meet the chip process requirements.
  • the thinning thickness of the sub-wafer 200 of the present invention can be significantly lower than the thinning thickness of the substrate in the prior art. Taking a 75 ⁇ m thickness wafer substrate as an example, the present invention only needs to remove about 200 [ xm wafers Materials can be used to obtain a 100 [ xm chip substrate wafer, and as a comparison, 5 see the technology needs to remove 65 (Vm, the amount of removal is more than 3 times that of the present invention.
  • the cost The invention saves production costs, shortens the thinning time, and also reduces the industrial waste generated, and plays a positive role in promoting the industrialization of large wafers with sizes of six inches and above, for example.
  • the mother wafer 100 may be further designed to include a bonding composition of a first mother wafer and a second mother wafer according to actual needs of thickness, so that it can be removed one by one to control the wafer The thickness of the substrate is controlled.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
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Abstract

The present invention provides a method for preparing an optoelectronic semiconductor chip and a bonding wafer used therein. A wafer material comprises wafers for epitaxy such as sapphire, silicon carbide, and gallium arsenide. According to the method, the conventional wafer is divided into a parent wafer and a child wafer, the application of a proper bonding technology to bond the parent wafer with the child wafer can withstand a change in warpage generated by a high temperature of 1,000ºC during epitaxy and the stress, and a non-physical destruction mode is used to unbond after epitaxy. The parent wafer can be recycled. The child wafer and an epitaxial layer are directly used for a chip manufacturing process without thinning or thinning partially, which solves the problems of a raw material of a large-size epitaxial wafer and chip processing costs. Moreover, an epitaxial wafer having a better wavelength uniformity is obtained.

Description

一种用于制作光电半导体芯片的方法及其所使用的键合 晶圆 A method for manufacturing optoelectronic semiconductor chips and its bonded wafer
技术领域 Technical field
[0001] 本发明涉及一种光电半导体芯片的制作方法， 具体涉及适用于外延的键合晶圆 背景技术 [0001] The present invention relates to a method for manufacturing an optoelectronic semiconductor chip, in particular to a bonded wafer suitable for epitaxy. BACKGROUND
[0002] 单晶蓝宝石、 碳化硅、 砷化镓晶体是比较典型的外延材料， 具有优良的光电效 应， 并被广泛地用于 LED、 功率器件上。 蓝宝石、 碳化硅、 砷化镓等晶体在生长 时都需要耗费大量的电能。 且晶圆尺寸越大， 晶体材料的良率越低， 半导体衬 底晶圆逐步从 4寸过渡到 6寸或者 8寸， 成本也相对较高。 [0002] Single crystal sapphire, silicon carbide, and gallium arsenide crystals are relatively typical epitaxial materials, have excellent photoelectric effects, and are widely used in LEDs and power devices. Crystals such as sapphire, silicon carbide, and gallium arsenide all consume a lot of electricity when growing. And the larger the wafer size, the lower the yield of the crystal material. The semiconductor substrate wafer gradually transitions from 4 inches to 6 inches or 8 inches, and the cost is relatively high.
[0003] 晶体需经过切割、 研磨、 抛光、 清洗等多段工序后成为晶圆； 经过外延生长后 ， 芯片的制程均需要将整个芯片厚度减薄， 以缩小芯片尺寸。 芯片的厚度通常 只有晶圆的 1/3以下， 也就是说， 有一半以上的晶体在最后得用减薄机磨掉， 晶 体材料浪费甚大。 [0003] The crystal needs to go through multiple processes such as cutting, grinding, polishing, and cleaning to become a wafer; after epitaxial growth, the entire chip thickness needs to be reduced in the manufacturing process of the chip to reduce the chip size. The thickness of the chip is usually less than 1/3 of the wafer, that is to say, more than half of the crystals have to be grinded with a thinner at the end, and the crystal material is wasted greatly.
[0004] 晶圆厚度是影响外延波长均匀性的关键要素之一， 厚度越厚越能减少外延层应 力所产生的翘曲度， 进而提高波长均匀性； 为了缩小芯片尺寸， 减少封装材料 的浪费， 芯片厚度越来越薄， 因此要求具有更薄的晶圆衬底厚度。 晶圆越厚在 芯片制程也须花更多成本来减薄， 这对于晶体材料存在大量浪费。 [0004] The thickness of the wafer is one of the key factors affecting the uniformity of the epitaxial wavelength. The thicker the thickness, the more it can reduce the warpage caused by the stress of the epitaxial layer, thereby improving the wavelength uniformity; in order to reduce the chip size and reduce the waste of packaging materials As the chip thickness is getting thinner and thinner, a thinner wafer substrate thickness is required. The thicker the wafer, the more cost to thin the chip manufacturing process, which has a lot of waste of crystal materials.
发明概述 Summary of the invention
技术问题 technical problem
问题的解决方案 The solution to the problem
技术解决方案 Technical solutions
[0005] 本发明提供了背景技术中的技术问题的解决方法， 本发明公开了一种用于制作 光电半导体芯片的方法， 将原本生长衬底分成母晶圆与子晶圆， 所述母晶圆和 子晶圆包括蓝宝石、 碳化硅或者砷化镓。 选择适当的键合介质在母晶圆、 子晶 圆或两者上都生长一层键合介质薄膜， 优选在其中之一的表面生长一层键合介 质， 尤其推荐在母晶圆上生长键合介质作为中间层。 中间层包括二氧化硅、 氮 化铝、 氮化镓中的一种或者任意种任意组合。 [0005] The present invention provides a solution to the technical problem in the background art. The present invention discloses a method for manufacturing an optoelectronic semiconductor chip. The original growth substrate is divided into a mother wafer and a daughter wafer. The round and sub-wafers include sapphire, silicon carbide or gallium arsenide. Choose the appropriate bonding medium in the mother wafer, daughter wafer A layer of bonding medium film is grown on the circle or both, preferably a layer of bonding medium is grown on the surface of one of them, and it is especially recommended to grow the bonding medium on the mother wafer as an intermediate layer. The intermediate layer includes one or any combination of silicon dioxide, aluminum nitride, and gallium nitride.
[0006] 键合设计在 300°C至 1000°C真空高温环境下进行母、 子晶圆的键合， 键合介质 位于键合面上。 其中较薄的子晶圆在半导体外延工艺制程后， 可以非破坏性的 解键合方式将键合介质破坏后分离， 与母晶圆分离后的子晶圆以及子晶圆上的 半导体外延层继续进行芯片制程； 下方较厚的母晶圆则可以在清洗后进行高温 退火释放外延生长累积的应力， 退火后的母晶圆可实现循环使用。 [0006] The bonding design performs the bonding of the mother and daughter wafers in a vacuum high temperature environment of 300°C to 1000°C, and the bonding medium is located on the bonding surface. Among them, the thinner daughter wafer can be non-destructively debonded after the semiconductor epitaxy process is processed, the bonding medium can be destroyed and separated, and the daughter wafer separated from the mother wafer and the semiconductor epitaxial layer on the daughter wafer continue to be processed Chip manufacturing process; the thicker mother wafer below can be annealed at a high temperature after cleaning to release the stress accumulated by epitaxial growth, and the annealed mother wafer can be recycled.
[0007] 所述的母晶圆与所述子晶圆的厚度设计， 可依据最终芯片厚度来设计子晶圆厚 度， 子晶圆厚度可比最终芯片衬底厚度略后或者相等。 为了提高良品率， 建议 订较厚母晶圆厚度； 原本晶圆厚度规格减去子晶圆厚度则为最低母晶圆厚度。 所述的母晶圆表面应为双面都是粗糙面的晶圆， 可以金刚砂、 碳化硼、 碳化硅 等高硬度微粉进行双面研磨制作稳定的粗糙表面， 并将线切割产生的翘曲 (WA RP) 修平； 或采用有关黄光、 显影、 蚀刻等技术制作的粗糙面。 定义子晶圆待 外延生长的表面为正面， 相对正面的另一面为背面， 背面与母晶圆相向键合， 子晶圆正面应为可外延等级的抛光面， 背面与母晶圆同为粗糙面或抛光面。 键 合前应以 03、 N2进行等离子清洁或化学方式清洗、 活化键合介质生长表面， 活 化处理的试剂包括双氧水、 氨水或者两者的混合物。 活化处理也可以为干法处 理， 例如利用电浆进行活化。 [0007] In the thickness design of the mother wafer and the daughter wafer, the thickness of the daughter wafer can be designed according to the final chip thickness, and the thickness of the daughter wafer can be slightly later than or equal to the thickness of the final chip substrate. In order to improve the yield rate, it is recommended to order a thicker mother wafer thickness; the original wafer thickness specification minus the daughter wafer thickness is the minimum mother wafer thickness. The surface of the mother wafer should be a wafer with rough surfaces on both sides. High-hardness micropowders such as silicon carbide, boron carbide, silicon carbide, etc. can be polished on both sides to produce a stable rough surface, and the warpage caused by wire cutting ( WA RP) Smoothing; or the rough surface produced by techniques related to yellow light, development, and etching. Define the surface of the daughter wafer to be epitaxially grown as the front side, and the opposite side to the front side as the back side. The back side is bonded to the mother wafer. The front side of the daughter wafer should be an epitaxially polished surface, and the back side should be rough as the mother wafer. Surface or polished surface. Before bonding, plasma cleaning or chemical cleaning with 03 or N2 should be used to clean and activate the growth surface of the bonding medium. The reagents for activation treatment include hydrogen peroxide, ammonia or a mixture of both. The activation treatment can also be a dry treatment, such as activation by plasma.
[0008] 所述的键合介质可以为二氧化硅 (Si02)、 氮化铝 (A1N)等薄膜， 键合介质组成的 中间层需有一定的厚度才能均匀键合， 例如采用 3~5pm， 才能抵抗在外延生长时 的 1000°C高温与外延层应力导致的弯曲。 所述的键合条件需在高温、 真空的键合 设备上进行。 所述的非破坏式的解键合方法为酸液腐蚀法， 将键合介质腐蚀破 坏， 不会伤到晶圆。 所述的母晶圆循环使用需经过清洗、 退火等制程， 将外延 的应力消除， 母晶圆也比较平坦， 有利于再次使用。 [0008] The bonding medium can be a thin film of silicon dioxide (SiO2), aluminum nitride (AlN), etc., and the intermediate layer composed of the bonding medium needs to have a certain thickness to be uniformly bonded, for example, 3 to 5 pm, It can resist the bending caused by the high temperature of 1000°C and the stress of the epitaxial layer during epitaxial growth. The aforementioned bonding conditions need to be performed on high-temperature, vacuum bonding equipment. The non-destructive debonding method is an acid corrosion method, which corrodes the bonding medium and does not damage the wafer. The recycling of the mother wafer requires cleaning, annealing and other processes to eliminate the stress of the epitaxy, and the mother wafer is relatively flat, which is conducive to reuse.
[0009] 优选的， 子晶圆厚度比最终芯片厚 50~40(Vm， 预留一些减薄调整的空间， 在 与母晶圆分离后， 可对子晶圆远离外延层的一侧进行减薄， 母晶圆厚度可比最 低母晶圆厚度稍厚 100~1000—， 以预留加工窗口。 子晶圆的厚度为 100~45(Vm ， 母晶圆的厚度为 300~150(Vm [0009] Preferably, the thickness of the daughter wafer is 50-40 μm thicker than the final chip, and some space for thinning adjustment is reserved. After being separated from the mother wafer, the side of the daughter wafer away from the epitaxial layer can be reduced. Thin, the thickness of the mother wafer can be slightly thicker than the minimum mother wafer thickness by 100~1000— to reserve a processing window. The thickness of the daughter wafer is 100~45(Vm , The thickness of the mother wafer is 300~150(Vm
[0010] 优选的， 子晶圆正面抛光粗糙度为 0.08~0.2nm; 子晶圆背面与母晶圆双面粗糙 度为 0.1 ~ 1.2[xm [0010] Preferably, the polished roughness of the front side of the daughter wafer is 0.08~0.2nm; the roughness of the back side of the daughter wafer and the mother wafer is 0.1~1.2 [xm
[0011] 优选的， 键合介质组成的中间层厚度为 3~5um [0011] Preferably, the thickness of the intermediate layer composed of the bonding medium is 3~5um
[0012] 优选的， 键合条件为 300~400°C真空环境下， 以 100~250 kg/cm 2的压力将母晶 圆与子晶圆键合 10~40分钟。 [0012] Preferably, the bonding conditions are 300 to 400° C. in a vacuum environment, and the mother wafer and the daughter wafer are bonded at a pressure of 100 to 250 kg/cm 2 for 10 to 40 minutes.
[0013] 优选的， 解键合方法为常温氢氟酸 (HF)腐蚀氧化硅键合介质。 [0013] Preferably, the debonding method is normal temperature hydrofluoric acid (HF) corrosion of the silicon oxide bonding medium.
[0014] 优选的， 母晶圆再利用的方法为超声波洁净水清洗、 旋干后， 放入 1350~1400 °C的高温退火炉中进行退火， 释放外延生产残余应力。 [0014] Preferably, the method for reusing the mother wafer is cleaning with ultrasonic clean water, spin-drying, and then placing it in a high temperature annealing furnace at 1350 to 1400°C for annealing to release residual stress in epitaxial production.
[0015] 优选的， 在一些情况下， 母晶圆可以包括第一母晶圆和第二母晶圆， 或者由两 个以上可分离的晶圆构成。 [0015] Preferably, in some cases, the mother wafer may include a first mother wafer and a second mother wafer, or consist of two or more separable wafers.
发明的有益效果 The beneficial effects of the invention
有益效果 Beneficial effect
[0016] 本发明的有益效果包括： [0016] The beneficial effects of the present invention include:
[0017] 本发明将传统晶圆分成母晶圆、 子晶圆， 运用适当的键合技术将母晶圆与子晶 圆键合后， 能耐外延时约 1000°C的高温与应力产生的翘曲变化； 外延后使用非物 理破坏方式解开键合。 母晶圆可以循环使用， 子晶圆与外延层直接用于芯片制 程， 不需要减薄或少量减薄， 解决了大尺寸外延晶圆的原材料与芯片加工成本 问题， 并得到波长均匀性更好的外延片。 [0017] The present invention divides the traditional wafer into a mother wafer and a daughter wafer, and after the mother wafer and the daughter wafer are bonded by an appropriate bonding technology, they can withstand the high temperature and stress generated by an external delay of about 1000°C. Warpage changes; use non-physical destruction methods to release the bond after epitaxy. The mother wafer can be recycled. The daughter wafer and the epitaxial layer are directly used in the chip manufacturing process. There is no need to thin or a small amount of thinning, which solves the problem of the raw material and chip processing cost of large-size epitaxial wafers, and obtains better wavelength uniformity Of epitaxial wafers.
[0018] 出于降低半导体器件生产制造成本和提升量产效率的考量， 越加聚焦于大尺寸 晶圆的研究， 大尺寸晶圆需要更佳抵抗制程应力的能力， 由于本案的母晶圆可 回收利用的特性， 因此可通过适当增加母晶圆厚度以保持量产的稳定性， 例如 降低外延生长时的翘曲问题， 从而提高外延生长的均匀性， 并不会明显增加生 产成本， 在大尺寸晶圆的量产制造上意义深远。 [0018] In order to reduce the manufacturing cost of semiconductor devices and improve the efficiency of mass production, the more focused the research on large-size wafers, the larger the wafers need better resistance to process stress, because the mother wafer in this case can Due to the characteristics of recycling, the thickness of the mother wafer can be appropriately increased to maintain the stability of mass production, such as reducing the warpage problem during epitaxial growth, thereby improving the uniformity of epitaxial growth, and will not significantly increase production costs. The mass production and manufacturing of large-size wafers has far-reaching significance.
[0019] 本发明的其它特征和优点将在随后的说明书中阐述， 并且， 部分地从说明书中 变得显而易见， 或者通过实施本发明而了解。 本发明的目的和其他优点可通过 在说明书、 权利要求书以及附图中所特别指出的结构来实现和获得。 [0019] Other features and advantages of the present invention will be described in the following description, and partly become obvious from the description, or understood by implementing the present invention. The objects and other advantages of the present invention can be realized and obtained through the structures specifically pointed out in the specification, claims and drawings.
对附图的简要说明 附图说明 Brief description of the drawings Description of the drawings
[0020] 附图用来提供对本发明的进一步理解， 并且构成说明书的一部分， 与本发明的 实施例一起用于解释本发明， 并不构成对本发明的限制。 此外， 附图数据是描 述概要， 不是按比例绘制。 [0020] The accompanying drawings are used to provide a further understanding of the present invention, and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation to the present invention. In addition, the figure data is a descriptive summary, not drawn to scale.
[0021] 图 1为键合晶圆的制作工艺流程； [0021] FIG. 1 is a manufacturing process flow of a bonded wafer;
[0022] 图 2~图7为光电半导体产品的制作过程示意图及相应的键合晶圆照片。 [0022] FIGS. 2-7 are schematic diagrams of the manufacturing process of optoelectronic semiconductor products and corresponding bonded wafer photos.
[0023] 图中标示： 100、 母晶圆； 110、 非光滑面； 200、 子晶圆； 300、 中间层； 310 、 外延层。 [0023] Indicated in the figure: 100, mother wafer; 110, non-smooth surface; 200, daughter wafer; 300, intermediate layer; 310, epitaxial layer.
发明实施例 Invention embodiment
本发明的实施方式 Embodiments of the invention
[0024] 下面便结合附图对本发明若干具体实施例作进一步的详细说明。 但以下关于实 施例的描述及说明对本发明保护范围不构成任何限制。 [0024] Several specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. However, the following description and explanation of the embodiments do not constitute any limitation to the protection scope of the present invention.
[0025] 应当理解， 本发明所使用的术语仅出于描述具体实施方式的目的， 而不是旨在 限制本发明。 进一步理解， 当在本发明中使用术语“包含”、 ”包括’’时， 用于表明 陈述的特征、 整体、 步骤、 组件存在， 而不排除一个或多个其他特征、 整体、 步骤、 组件和 /或它们的组合的存在或增加。 [0025] It should be understood that the terms used in the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. It is further understood that when the terms "including" and "including" are used in the present invention, they are used to indicate that the stated features, wholes, steps, and components are present, but do not exclude one or more other features, wholes, steps, components, and / Or the presence or increase of their combination.
[0026] 除另有定义之外， 本发明所使用的所有术语 （包括技术术语和科学术语） 具有 与本发明所属领域的普通技术人员通常所理解的含义相同的含义。 应进一步理 解， 本发明所使用的术语应被理解为具有与这些术语在本说明书的上下文和相 关领域中的含义一致的含义， 并且不应以理想化或过于正式的意义来理解， 除 本发明中明确如此定义之外。 [0026] Unless otherwise defined, all terms (including technical and scientific terms) used in the present invention have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention belongs. It should be further understood that the terms used in the present invention should be understood as having meanings consistent with the meanings of these terms in the context of this specification and related fields, and should not be understood in an idealized or overly formal sense, except for the present invention. Clearly defined as such.
[0027] 参看图 1， 本发明提供了一种用于制作光电半导体芯片的方法， 用以制作低成 本、 高性能、 环保的晶圆， 利用本发明的键合方法， 对大尺寸蓝宝石、 碳化硅 或砷化镓晶圆具有极大的成本效益。 方法包括步骤： 提供相同材料或者不同材 料的母晶圆 100和子晶圆 200， 对母晶圆 100和子晶圆 200的其中一面蒸镀介质层 ， 介质层具有键合特性， 利用介质层作为中间层 300, 在对介质层进行抛光后清 洗， 利用氨水和双氧水对中间层 300进行活化处理， 活化处理目的在于促使中间 层 300表面形成羟基 （-OH） ， 羟基对晶圆材料的 A1或者 0形成库伦拉力， 有利 于中间层与母晶圆和子晶圆相连接， 母晶圆 100和子晶圆 200预对位， 相互对齐 ， 进行热压键合工艺， 得到键合晶圆， 对键合晶圆进行检测后清洗。 [0027] Referring to FIG. 1, the present invention provides a method for manufacturing optoelectronic semiconductor chips for manufacturing low-cost, high-performance, and environmentally friendly wafers. Using the bonding method of the present invention, the method for large-size sapphire, carbonization Silicon or gallium arsenide wafers are extremely cost-effective. The method includes the steps of: providing a mother wafer 100 and a daughter wafer 200 of the same material or different materials, evaporating a dielectric layer on one side of the mother wafer 100 and the daughter wafer 200, the dielectric layer has bonding characteristics, and the dielectric layer is used as an intermediate layer 300. After the dielectric layer is polished and cleaned, the intermediate layer 300 is activated with ammonia and hydrogen peroxide. The purpose of the activation treatment is to promote the formation of hydroxyl groups (-OH) on the surface of the intermediate layer 300. The hydroxyl groups form a coulomb for A1 or 0 of the wafer material. Pulling force, favorable The mother wafer and the daughter wafer are connected in the intermediate layer, the mother wafer 100 and the daughter wafer 200 are pre-aligned, aligned with each other, and the thermocompression bonding process is performed to obtain the bonded wafer, and the bonded wafer is inspected and cleaned .
[0028] 再参看图 2到图 4， 详细来说， 提供母晶圆 100和子晶圆 200， 二者的材料选择包 括但不限于： 蓝宝石、 碳化硅或者砷化镓， 为了进行后续的高温键合工艺， 晶 圆材料所能承受的高温环境温度应不小于 1000°c 通过在两者之间分别设置中间 层 300, 本实施例中， 在母晶圆 100的非光滑面 110以及子晶圆 200相对非光滑面 1 00的一面蒸镀键合介质材料 310 2制作中间层 300 （中间层图中未标出） ， 对中间 层 300进行 CMP （机械化学抛光） ， 由于 Si02采用蒸镀沉积的模式制作， 需利用 抛光提升中间层的平坦度， 而后将两者结果活化处理后， 将具有中间层 300的一 面相向进行键合工艺。 实施例中例如采用母晶圆 100的厚度为 30（Vm至 50（Vm， 为防止晶圆破碎， 母晶圆 100的厚度具有随着晶圆面积的增大而增厚的趋势， 因 此在大尺寸晶圆中例如八寸片， 母晶圆 100的厚度可能达到 150（Vm， 子晶圆 200 的厚度为 10（Vm至 450—， 本发明构思下的子晶圆 200至少可以达到 lOOpm级的厚 度， 需要明确的是， 随着晶圆制作技术的提升， 采用本发明的技术方案可能得 到更薄的子晶圆 200。 [0028] Referring again to FIGS. 2 to 4, in detail, a mother wafer 100 and a daughter wafer 200 are provided, and the material selection of the two includes but not limited to: sapphire, silicon carbide or gallium arsenide, in order to perform subsequent high temperature bonding The high-temperature environment temperature that the wafer material can withstand should not be less than 1000°C. The intermediate layer 300 is provided between the two. In this embodiment, the non-smooth surface 110 of the mother wafer 100 and the daughter wafer 200 is relatively non-smooth surface 100 by vapor deposition bonding dielectric material 310 2 to make an intermediate layer 300 (not shown in the intermediate layer diagram), and CMP (mechanical chemical polishing) is performed on the intermediate layer 300, because SiO 2 is deposited by vapor deposition For pattern production, polishing needs to be used to improve the flatness of the intermediate layer, and then after the two results are activated, the side with the intermediate layer 300 is faced to undergo a bonding process. In the embodiment, for example, the thickness of the mother wafer 100 is 30 (Vm to 50 (Vm). In order to prevent the wafer from breaking, the thickness of the mother wafer 100 has a tendency to increase with the increase of the wafer area. For example, for 8-inch wafers, the thickness of the mother wafer 100 may reach 150 μm, and the thickness of the daughter wafer 200 may be 10 μm to 450 mm. The daughter wafer 200 under the concept of the present invention can reach at least 100 μm. For the thickness, it should be clear that with the improvement of wafer fabrication technology, it is possible to obtain a thinner sub-wafer 200 by using the technical solution of the present invention.
[0029] 在一些实施例中， 晶圆表面洁净度越好， 所生长的键合介质的品质也越好， 键 合的效果越佳， 抛光后对键合晶圆进行清洗。 晶圆的翘曲度 （WARP） 、 平坦度 （TTV） 等越小， 键合的效果也越好， 甚至可以减少键合介质的厚度。 适合的键 合介质需与晶圆材料晶格匹配高， 如二氧化硅 （Si0 2） 、 氮化铝 （A1N） 、 氮化 镓 （GaN） 等薄膜中的一种或者多种任意组合。 可在母晶圆上生长薄膜或母晶圆 100与子晶圆 200均生长薄膜， 在适合的温度与压力下做键合。 [0029] In some embodiments, the better the cleanliness of the wafer surface, the better the quality of the grown bonding medium, the better the bonding effect, and the bonded wafer is cleaned after polishing. The smaller the wafer warpage (WARP), flatness (TTV), etc., the better the bonding effect, and even the thickness of the bonding medium can be reduced. A suitable bonding medium needs to have a high lattice match with the wafer material, such as one or any combination of silicon dioxide (SiO 2 ), aluminum nitride (AlN), gallium nitride (GaN) and other thin films. Mother wafer or film may be grown on the mother wafer 100 and wafer 200 are sub-film growth, do bonded at a suitable temperature and pressure.
[0030] 本发明提供的实施例中， 该实施例在上述方案的基础上， 在母晶圆 100与子晶 圆 200相对的表面粗糖度也会影响键合的效果。 晶圆表面越粗糖， 键合介质长得 越密； 但是粗糙度太大， 反而容易出现孔洞， 影响键合效果， 在本实施例中， 粗糙度控制在 0.1 ~ 1.2pm。 [0030] In the embodiment provided by the present invention, on the basis of the above solution, the roughness of the surface of the mother wafer 100 and the daughter wafer 200 opposite to each other will also affect the bonding effect. The coarser the surface of the wafer, the denser the bonding medium grows; however, the roughness is too large, and holes are prone to appear, which affects the bonding effect. In this embodiment, the roughness is controlled at 0.1-1.2 pm.
[0031] 在该实施例中， 母晶圆 100与子晶圆 200的尺寸需一致， 直径需在 ±0.1mm范围 内， 以利于键合时， 母晶圆 100和子晶圆 200的对位。 LED用蓝宝石晶圆需以曝光 显影、 蚀刻等制程制作图形 （Patterned Sapphire Substrate, PSS） 在子晶圆 200的 表面上， 以增加在发光半导体器件中的出光效果， 在实施中， 图形化衬底能从 反射和外延晶格匹配两方面， 有效提高发光半导体器件的出光效率。 晶圆的键 合的过程建议在制作上述图形之前， 避免键合时的压力对于图形的破坏。 [0031] In this embodiment, the size of the mother wafer 100 and the daughter wafer 200 need to be the same, and the diameter should be within ±0.1 mm to facilitate the alignment of the mother wafer 100 and the daughter wafer 200 during bonding. Sapphire wafers for LEDs need to be exposed, developed, and etched to produce patterns (Patterned Sapphire Substrate, PSS) on the sub-wafer 200 On the surface, in order to increase the light-emitting effect in the light-emitting semiconductor device, in implementation, the patterned substrate can effectively improve the light-emitting efficiency of the light-emitting semiconductor device in terms of reflection and epitaxial lattice matching. In the process of wafer bonding, it is recommended to avoid damage to the pattern by the pressure during bonding before making the above-mentioned patterns.
[0032] 在另一些实施例中， 有别于其它物理破坏方式， 如以激光分离法， 在晶圆侧面 周围划一道深沟后， 在低温环境下再用刀具将晶圆分离的方式， 该类破坏会产 生许多崩角， 对于母晶圆 100的再利用率降低。 而本实施例以酸蚀刻键合介质的 方式解键合， 以蓝宝石晶圆为例， 使用氢氟酸来腐蚀键合介质氧化硅， 常温氢 氟酸浸泡 40分钟后即可轻易分离， 不会影响半导体器件的外延层与晶圆本体。 [0032] In other embodiments, different from other physical destruction methods, such as the laser separation method, after a deep groove is drawn around the side of the wafer, the wafer is separated by a tool in a low temperature environment. This type of damage will produce many chipping corners, and the reuse rate of the mother wafer 100 will decrease. In this embodiment, the bonding is debonded by acid etching the bonding medium. Taking the sapphire wafer as an example, hydrofluoric acid is used to corrode the bonding medium silicon oxide. After 40 minutes of soaking in hydrofluoric acid at room temperature, it can be easily separated without affecting the semiconductor. The epitaxial layer of the device and the wafer body.
[0033] 参看图 5， 子晶圆 200用于制作外延， 在子晶圆 200远离键合面的一侧设置为光 滑面， 用于制作外延层 210， 外延层依次包括 N侧层、 P侧层和位于二者之间的有 源层， 例如通过 MOCVD金属有机物化学气相沉积半导体材料。 [0033] Referring to FIG. 5, the sub-wafer 200 is used for making an epitaxial layer, and a smooth surface is provided on the side of the sub-wafer 200 away from the bonding surface for making an epitaxial layer 210. The epitaxial layer includes an N-side layer and a P-side layer. And the active layer located between the two, for example, a semiconductor material by MOCVD metal organic chemical vapor deposition.
[0034] 参看图 6和图 7， 制作好外延层 210后， 解开中间层 300， 将母晶圆 100和子晶圆 2 00分离。 子晶圆 200继续制作芯片工艺， 例如利用光阻蚀刻在外延层 210远离子 晶圆 200的一侧上制作芯片图形， 去除部分 P侧层， 至露出 N侧层， 再接着在 P侧 层和 /或露出的 N侧层表面制作绝缘保护层或者透明导电扩散层， 最后制作与 P侧 层和露出的 N侧层连接的芯片电极， 形成发光半导体芯片结构。 [0034] Referring to FIGS. 6 and 7, after the epitaxial layer 210 is fabricated, the intermediate layer 300 is unwound, and the mother wafer 100 and the daughter wafer 200 are separated. The sub-wafer 200 continues the chip manufacturing process, for example, using photoresist etching to make a chip pattern on the side of the epitaxial layer 210 away from the sub-wafer 200, remove part of the P-side layer until the N-side layer is exposed, and then add the P-side layer and /Or an insulating protective layer or a transparent conductive diffusion layer is fabricated on the surface of the exposed N-side layer, and finally chip electrodes connected to the P-side layer and the exposed N-side layer are fabricated to form a light-emitting semiconductor chip structure.
[0035] 同时可对分离后的母晶圆 100进行高温退火后再次回收利用， 用以再次制作键 合晶圆。 减薄子晶圆 200以适应芯片工艺要求。 本发明对子晶圆 200的减薄厚度 可大幅低于现有工艺对衬底的减薄厚度， 以 75(Vm厚度晶圆衬底为例， 本发明只 需移除大约 200[xm晶圆材料即可得到 100[xm的芯片衬底晶圆， 而作为对比， 5见有 技术则需移除 65(Vm， 移除量为本发明的 3倍以上。 工业生产中通常采用研磨移 除的方式去除多余衬底材料， 而研磨工艺去除衬底材料效率较低， 也会消耗研 磨砂轮， 即导致制程时间较长， 又加剧类似砂轮等生产备件的损耗， 因此相较 于现有技术， 本发明节省了生产成本， 缩短了减薄时间， 也降低了产生的工业 废料， 对例如六英寸及以上尺寸大晶圆工业化起到积极推动作用。 [0035] At the same time, the separated mother wafer 100 can be annealed at a high temperature and then recycled again to make a bonded wafer again. The sub-wafer 200 is thinned to meet the chip process requirements. The thinning thickness of the sub-wafer 200 of the present invention can be significantly lower than the thinning thickness of the substrate in the prior art. Taking a 75 μm thickness wafer substrate as an example, the present invention only needs to remove about 200 [ xm wafers Materials can be used to obtain a 100 [ xm chip substrate wafer, and as a comparison, 5 see the technology needs to remove 65 (Vm, the amount of removal is more than 3 times that of the present invention. In industrial production, grinding removal is usually used Method to remove excess substrate material, and the polishing process is less efficient in removing the substrate material, and will also consume the grinding wheel, which leads to a longer process time and aggravates the loss of production spare parts such as the grinding wheel. Therefore, compared with the prior art, the cost The invention saves production costs, shortens the thinning time, and also reduces the industrial waste generated, and plays a positive role in promoting the industrialization of large wafers with sizes of six inches and above, for example.
[0036] 在一些实施例中， 母晶圆 100可根据实际需要厚度需要， 进一步设计成包括第 一母晶圆和第二母晶圆键合组成， 可实现逐个晶圆去除， 以控制晶圆衬底的厚 度控制。 [0037] 以上所述仅是本发明的优选实施方式， 应当指出， 对于本技术领域的技术人员 ， 在不脱离本发明原理的前提下， 还可以做出若干改进和润饰， 这些改进和润 饰也应视为本发明的保护范围。 [0036] In some embodiments, the mother wafer 100 may be further designed to include a bonding composition of a first mother wafer and a second mother wafer according to actual needs of thickness, so that it can be removed one by one to control the wafer The thickness of the substrate is controlled. [0037] The above are only the preferred embodiments of the present invention. It should be pointed out that for those skilled in the art, without departing from the principle of the present invention, several improvements and modifications can be made, and these improvements and modifications are also It should be regarded as the protection scope of the present invention.

Claims

权利要求书 Claims
[权利要求 1] 一种用于制作光电半导体芯片的方法， 包括工艺步骤： [Claim 1] A method for manufacturing an optoelectronic semiconductor chip, including the process steps:
步骤 1， 提供母晶圆和子晶圆， 通过设置在二者之间的中间层键合成 为键合晶圆； Step 1. Provide a mother wafer and a daughter wafer, and synthesize them into a bonded wafer through an intermediate layer bond set between the two;
步骤 2, 在键合晶圆靠近子晶圆一侧表面制作外延层； Step 2, Fabricate an epitaxial layer on the surface of the bonded wafer near the sub-wafer side;
步骤 3， 解开中间层， 分离母晶圆和子晶圆。 Step 3. Untie the intermediate layer, and separate the mother wafer and the daughter wafer.
[权利要求 2] 根据权利要求 1所述的一种用于制作光电半导体芯片的方法， 其特征 在于： 解开后的子晶圆与外延层继续做芯片制程， 母晶圆则循环使用 [Claim 2] A method for manufacturing optoelectronic semiconductor chips according to claim 1, characterized in that: the unwrapped daughter wafer and epitaxial layer continue the chip manufacturing process, and the mother wafer is recycled
[权利要求 3] 根据权利要求 2所述的一种用于制作光电半导体芯片的方法， 其特征 在于： 解开后的母晶圆经过高温退火后循环使用。 [Claim 3] A method for manufacturing optoelectronic semiconductor chips according to claim 2, characterized in that: the unwound mother wafer is annealed at a high temperature and then recycled.
[权利要求 4] 根据权利要求 1所述的一种用于制作光电半导体芯片的方法， 其特征 在于： 解开后的子晶圆从远离外延层的一侧进行减薄。 [Claim 4] The method for manufacturing optoelectronic semiconductor chips according to claim 1, characterized in that: the unwrapped sub-wafer is thinned from the side away from the epitaxial layer.
[权利要求 5] 根据权利要求 1所述的一种用于制作光电半导体芯片的方法， 其特征 在于： 步骤 1键合前在母晶圆和子晶圆相对的一面分别制作中间层或 者仅在其中之一制作中间层。 [Claim 5] A method for manufacturing optoelectronic semiconductor chips according to claim 1, characterized in that: before bonding in step 1, an intermediate layer is formed on the opposite side of the mother wafer and the daughter wafer, or only in it. One makes the middle layer.
[权利要求 6] 根据权利要求 1所述的一种用于制作光电半导体芯片的方法， 其特征 在于： 所述母晶圆和子晶圆包括蓝宝石、 碳化桂或者砷化镓。 [Claim 6] The method for manufacturing optoelectronic semiconductor chips according to claim 1, characterized in that: the mother wafer and the daughter wafer comprise sapphire, cinnamon carbide or gallium arsenide.
[权利要求 7] 根据权利要求 1所述的一种用于制作光电半导体芯片的方法， 其特征 在于： 所述子晶圆的厚度为 10(Vm至 450—。 [Claim 7] The method for manufacturing optoelectronic semiconductor chips according to claim 1, wherein the thickness of the sub-wafer is 10 (Vm to 450 mm).
[权利要求 8] 根据权利要求 1所述的一种用于制作光电半导体芯片的方法， 其特征 在于： 所述母晶圆的厚度为 30(Vm至 150(Vm。 [Claim 8] A method for manufacturing optoelectronic semiconductor chips according to claim 1, characterized in that: the thickness of the mother wafer is 30 (Vm to 150 (Vm).
[权利要求 9] 根据权利要求 1所述的一种用于制作光电半导体芯片的方法， 其特征 在于： 所述母晶圆和 /或子晶圆所能承受的高温环境温度不小于 1000 oc [Claim 9] A method for manufacturing optoelectronic semiconductor chips according to claim 1, characterized in that: the high-temperature environmental temperature that the mother wafer and/or daughter wafer can withstand is not less than 1000 oc
[权利要求 10] 根据权利要求 1所述的一种用于制作光电半导体芯片的方法， 其特征 在于： 所述中间层包括二氧化硅、 氮化铝、 氮化镓中的一种或者任意 种任意组合。 [Claim 10] A method for manufacturing optoelectronic semiconductor chips according to claim 1, characterized in that: the intermediate layer comprises one or any of silicon dioxide, aluminum nitride, and gallium nitride random combination.
[权利要求 11] 根据权利要求 1所述的一种用于制作光电半导体芯片的方法， 其特征 在于： 所述中间层可通过腐蚀工艺移除。 [Claim 11] The method for manufacturing optoelectronic semiconductor chips according to claim 1, wherein the intermediate layer can be removed by an etching process.
[权利要求 12] 根据权利要求 1所述的一种用于制作光电半导体芯片的方法， 其特征 在于： 所述母晶圆至少由第一母晶圆和第二母晶圆组成。 [Claim 12] The method for manufacturing optoelectronic semiconductor chips according to claim 1, wherein the mother wafer is at least composed of a first mother wafer and a second mother wafer.
[权利要求 13] 根据权利要求 1所述的一种用于制作光电半导体芯片的方法， 其特征 在于： 对中间层进行活化处理。 [Claim 13] A method for manufacturing optoelectronic semiconductor chips according to claim 1, characterized in that: the intermediate layer is activated.
[权利要求 14] 根据权利要求 13所述的一种用于制作光电半导体芯片的方法， 其特征 在于： 活化处理的试剂包括双氧水、 氨水或者两者的混合物。 [Claim 14] A method for manufacturing optoelectronic semiconductor chips according to claim 13, characterized in that: the reagent for activation treatment includes hydrogen peroxide, ammonia or a mixture of the two.
[权利要求 15] 根据权利要求 13所述的一种用于制作光电半导体芯片的方法， 其特征 在于： 活化处理为干法处理， 利用电浆进行活化。 [Claim 15] A method for manufacturing optoelectronic semiconductor chips according to claim 13, characterized in that: the activation treatment is a dry treatment, and activation is performed by plasma.
[权利要求 16] 一种键合晶圆， 作为制作光电半导体芯片的生长衬底， 其特征在于： 键合晶圆包括母晶圆、 子晶圆及位于两者之间的中间层。 [Claim 16] A bonded wafer, used as a growth substrate for manufacturing optoelectronic semiconductor chips, is characterized in that the bonded wafer includes a mother wafer, a daughter wafer, and an intermediate layer between the two.
[权利要求 17] 根据权利要求 16所述的一种键合晶圆， 其特征在于： 所述子晶圆的厚 度为 100[xm至 450[xm [Claim 17] A bonded wafer according to claim 16, wherein the thickness of the sub-wafer is 100 [ xm to 450 [ xm
[权利要求 18] 根据权利要求 16所述的一种键合晶圆， 其特征在于： 所述母晶圆为 30 [Claim 18] A bonded wafer according to claim 16, characterized in that: the mother wafer is 30
0[xm至 1500[xm 0 [ xm to 1500 [ xm
[权利要求 19] 根据权利要求 16所述的一种键合晶圆， 其特征在于： 所述中间层的厚 度为 3[xm至 5[xm [Claim 19] A bonded wafer according to claim 16, characterized in that: the thickness of the intermediate layer is 3 [ xm to 5 [ xm
[权利要求 20] 根据权利要求 16所述的一种键合晶圆， 其特征在于： 所述子晶圆远离 所述母晶圆的一侧表面为光滑面。 [Claim 20] The bonded wafer according to claim 16, wherein the surface of the daughter wafer on the side away from the mother wafer is a smooth surface.
[权利要求 21] 根据权利要求 16所述的一种键合晶圆， 其特征在于： 所述母晶圆至少 由第一母晶圆和第二母晶圆组成。 [Claim 21] The bonded wafer according to claim 16, wherein the mother wafer is composed of at least a first mother wafer and a second mother wafer.
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