WO2018036169A1 - 像素电路、显示面板、显示设备及驱动方法 - Google Patents

像素电路、显示面板、显示设备及驱动方法 Download PDF

Info

Publication number
WO2018036169A1
WO2018036169A1 PCT/CN2017/079713 CN2017079713W WO2018036169A1 WO 2018036169 A1 WO2018036169 A1 WO 2018036169A1 CN 2017079713 W CN2017079713 W CN 2017079713W WO 2018036169 A1 WO2018036169 A1 WO 2018036169A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
voltage
electrically connected
node
reset
Prior art date
Application number
PCT/CN2017/079713
Other languages
English (en)
French (fr)
Inventor
张毅
张锴
玄明花
高永益
皇甫鲁江
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/569,243 priority Critical patent/US10692434B2/en
Publication of WO2018036169A1 publication Critical patent/WO2018036169A1/zh
Priority to US17/649,809 priority patent/US11574595B2/en
Priority to US18/150,873 priority patent/US11881176B2/en

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0204—Compensation of DC component across the pixels in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0693—Calibration of display systems
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • Embodiments of the present disclosure relate to a pixel circuit, a display panel, a display device, and a driving method.
  • organic light-emitting diode (OLED) display panels have the characteristics of self-luminous, high contrast, low power consumption, wide viewing angle, fast response, flexible panel, wide temperature range, and simple manufacturing. Prospects.
  • the organic light emitting diode (OLED) display panel can be applied to a device having a display function such as a mobile phone, a display, a notebook computer, a digital camera, an instrument meter, and the like.
  • Embodiments of the present disclosure provide a pixel circuit including: a storage capacitor including a first end connected to a first node and a second end connected to a second node; and an organic light emitting diode including a first connected to the third node a driving transistor including a gate connected to the first node, wherein the driving transistor is configured to control illumination of the organic light emitting diode according to a voltage of the first node; and an illumination control circuit configured to receive Illuminating the control signal and controlling the organic light emitting diode to emit or turn off according to the lighting control signal; the reset circuit is configured to receive a reset control signal and write a reset voltage to the first node according to the reset control signal; a threshold a compensation circuit configured to receive the first scan signal and write a compensation voltage to the first node according to the first scan signal, wherein the compensation voltage is a first power voltage and a threshold voltage of the driving transistor And a first data writing circuit configured to receive the first scan signal and the data signal and according to the first scan letter Writing the
  • the initialization voltage is equal to the complex Bit voltage.
  • the organic light emitting diode further includes a second pole, and the second pole of the organic light emitting diode is electrically connected to the second power line to receive the second power voltage, the organic a first anode of the light emitting diode, a second cathode of the organic light emitting diode, and a difference between the initialization voltage and the second power voltage is less than a lightening voltage of the organic light emitting diode.
  • the initialization voltage is less than or equal to the second power voltage.
  • the reset circuit includes a first transistor
  • the threshold compensation circuit includes a second transistor
  • the first data write circuit includes a third transistor
  • the reference voltage is written.
  • the input circuit includes a fourth transistor
  • the illumination control circuit includes a fifth transistor
  • the initialization circuit includes a sixth transistor.
  • the gate of the driving transistor is electrically connected to the first node, and the first pole of the driving transistor is electrically connected to the first power line to receive the first power voltage.
  • the second pole of the driving transistor is electrically connected to the fourth node; the first pole of the organic light emitting diode is electrically connected to the third node, and the second pole of the organic light emitting diode is electrically connected to the second power line Receiving a second power voltage; the first end of the storage capacitor is electrically connected to the first node, the second end of the storage capacitor is electrically connected to the second node; and the gate of the first transistor is a reset control signal line electrically connected to receive the reset control signal, a first pole of the first transistor being electrically coupled to the reset voltage line to receive the reset voltage, a second pole of the first transistor and the first The node is electrically connected; the gate of the second transistor is electrically connected to the first scan signal line to receive the first scan signal, and the first pole of the
  • the driving transistor, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the The sixth transistor is a P-type transistor.
  • the driving transistor, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the The sixth transistor is a thin film transistor.
  • the pixel circuit provided by the embodiment of the present disclosure further includes a second data writing circuit configured to receive the reset control signal and the data signal and write to the second node according to the reset control signal The data signal.
  • the reset circuit includes a first transistor
  • the threshold compensation circuit includes a second transistor
  • the first data write circuit includes a third transistor
  • the reference voltage is written.
  • the input circuit includes a fourth transistor
  • the illumination control circuit includes a fifth transistor
  • the initialization circuit includes a sixth transistor
  • the second data write circuit includes a seventh transistor.
  • the gate of the driving transistor is electrically connected to the first node, and the first pole of the driving transistor is electrically connected to the first power line to receive the first power voltage.
  • the second pole of the driving transistor is electrically connected to the fourth node; the first pole of the organic light emitting diode is electrically connected to the third node, and the second pole of the organic light emitting diode is electrically connected to the second power line Receiving a second power voltage; the first end of the storage capacitor is electrically connected to the first node, the second end of the storage capacitor is electrically connected to the second node; and the gate of the first transistor is a reset control signal line electrically connected to receive the reset control signal, a first pole of the first transistor being electrically coupled to the reset voltage line to receive the reset voltage, a second pole of the first transistor and the first The node is electrically connected; the gate of the second transistor is electrically connected to the first scan signal line to receive the first scan signal, and the first pole of the
  • the driving transistor, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the The sixth transistor and the seventh transistor are both P-type transistors.
  • the driving transistor, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the The sixth transistor and the seventh transistor are both thin film transistors.
  • An embodiment of the present disclosure further provides a display panel including the pixel circuit provided by any of the embodiments of the present disclosure.
  • the display panel provided by the embodiment of the present disclosure further includes: a data driver configured to provide the data signal to the pixel circuit; and a scan driver configured to provide the illumination control signal to the pixel circuit
  • a data driver configured to provide the data signal to the pixel circuit
  • a scan driver configured to provide the illumination control signal to the pixel circuit
  • An embodiment of the present disclosure further provides a display device including the display panel provided by any embodiment of the present disclosure.
  • An embodiment of the present disclosure further provides a driving method of a pixel circuit according to an embodiment of the present disclosure, including a reset phase, a data writing and threshold compensation phase, a voltage drop compensation phase, and an illumination phase in a frame display period, wherein In the reset phase, setting the light emission control signal to a turn-off voltage, setting the reset control signal to an on voltage, and setting the first scan signal to a turn-off voltage.
  • An embodiment of the present disclosure further provides a driving method of a pixel circuit according to an embodiment of the present disclosure, including a reset phase, a data writing and threshold compensation phase, a voltage drop compensation phase, and an illumination phase in a frame display period, wherein
  • the reset phase setting the light emission control signal to a turn-off voltage, setting the reset control signal to an on voltage, setting the first scan signal to a turn-off voltage, and setting the second scan signal to a turn-off voltage, setting The data signal is a valid data signal;
  • the lighting control signal is set to a shutdown voltage, the reset control signal is set to a shutdown voltage, and the first scan signal is set to an on voltage And setting the second scan signal to a shutdown voltage, setting the data signal to be a valid data signal;
  • the voltage drop compensation phase setting the illumination control signal to a shutdown voltage, and setting the reset control signal to a shutdown voltage, Setting the first scan signal to be a turn-off voltage, and setting the second scan signal to a turn-on voltage,
  • the ratio of the duration of the lighting phase to the display period of one frame may be adjusted.
  • the driving method provided by the embodiment of the present disclosure may further include a lighting continuation phase in a frame display period, wherein the illuminating continuation phase includes at least one closing sub-phase and at least one illuminating sub-phase, in the closing a sub-stage, setting the light-emitting control signal to a turn-off voltage, setting the reset control signal to a turn-off voltage, and setting the first scan signal to a turn-off voltage, Setting the second scan signal as an on voltage, setting the data signal as an invalid data signal; in the illuminating sub-stage, setting the illuminating control signal to an on voltage, setting the reset control signal to a shutdown voltage, setting a setting The first scan signal is a turn-off voltage, the second scan signal is set to an on voltage, and the data signal is set to be an invalid data signal.
  • the illuminating continuation phase includes at least one closing sub-phase and at least one illuminating sub-phase, in the closing a sub-stage, setting the light-emitting control signal to a turn-
  • the ratio of the duration of the illuminating phase and the total duration of all the illuminating sub-stages to the one-frame display period can be adjusted.
  • the duration of each of the shutdown sub-phases is equal to the duration of the reset phase, the duration of the data writing and threshold compensation phase, and the duration of the voltage drop compensation phase.
  • the duration of each of the illuminating sub-phases is equal to the length of the illuminating phase.
  • FIG. 1 is a schematic diagram of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 2 is a second schematic diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 3 is a third schematic diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 4 is a fourth schematic diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 5 is a fifth schematic diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • FIG. 8 and FIG. 9 are exemplary driving timing diagrams of the pixel circuit shown in FIG. 3 according to an embodiment of the present disclosure
  • FIG. 10 and 11 are exemplary driving timing diagrams of the pixel circuit shown in FIG. 5 provided by an embodiment of the present disclosure.
  • OLED organic light-emitting diode
  • the threshold voltages of the driving transistors in the respective pixel units may differ from each other due to the fabrication process, and the threshold voltage of the driving transistor may also drift due to, for example, the influence of temperature changes. Therefore, the difference in threshold voltages of the respective driving transistors may also cause the display panel to be unevenly displayed. Therefore, this also leads to the need to compensate for the threshold voltage.
  • the gray scale of the OLED display device is controlled by the data voltage of the driving circuit.
  • the driving circuit is difficult to accurately control under the condition of outputting low gray scale data voltage. .
  • Embodiments of the present disclosure provide a pixel circuit, a display panel, a display device, and a driving method, which can perform resistance voltage drop and threshold voltage compensation on a display panel, thereby improving uniformity of driving current, thereby improving display panel uniformity.
  • the leakage current is reduced to ensure high contrast in the black state, and the ratio of the illumination time to the display period of one frame is adjusted to ensure the fineness in the low gray level condition. Indeed displayed.
  • the pixel circuit 100 includes a storage capacitor C, an organic light emitting diode OLED, a driving transistor DT, an illumination control circuit 110, a reset circuit 120, and a threshold compensation circuit 130.
  • the storage capacitor C includes a first end connected to the first node N1 and a second end connected to the second node N2.
  • the organic light emitting diode OLED includes a first pole connected to the third node N3.
  • the driving transistor DT includes a gate connected to the first node N1; the driving transistor DT is configured to control the organic light emitting diode OLED to emit light according to the voltage of the first node N1.
  • the light emission control circuit 110 is configured to receive the light emission control signal EM and control the organic light emitting diode OLED to emit light or turn off according to the light emission control signal EM.
  • the reset circuit 120 is configured to receive the reset control signal Reset and write a reset voltage Vint to the first node N1 according to the reset control signal Reset.
  • the threshold compensation circuit 130 is configured to receive the first scan signal Gate and write a compensation voltage to the first node N1 according to the first scan signal Gate, the compensation voltage being the first power voltage ELVDD and the threshold voltage Vth of the driving transistor And ELVDD+Vth.
  • the first data write circuit 140 is configured to receive the first scan signal Gate and the data signal Data and write the data signal Data to the second node N2 according to the first scan signal Gate.
  • the reference voltage writing circuit 150 is configured to receive the second scan signal Scan and write the reference voltage Vref to the second node N2 according to the second scan signal Scan.
  • the initialization circuit 160 is configured to receive the first scan signal Gate or the reset control signal Reset and write the initialization voltage Vre to the third node N3 according to the first scan signal Gate or the reset control signal Reset.
  • the initialization voltage Vre is equal to the reset voltage Vint. That is to say, the reset voltage can be used for both the reset circuit 120 and the initialization circuit 160. This arrangement can save the voltage output port, simplify the circuit, and save cost.
  • the organic light emitting diode OLED further includes a second pole, and the second pole of the organic light emitting diode OLED is electrically connected to the second power line to receive the second power source.
  • Voltage ELVSS For example, the first extreme anode of the organic light emitting diode and the second extreme cathode of the organic light emitting diode. The difference between the initialization voltage Vre and the second power supply voltage ELVSS is smaller than the light-emitting voltage of the organic light emitting diode OLED.
  • the initialization circuit 160 writes the initialization voltage Vre to the third node N3, which can be the voltage of the third node N3 (ie, the organic light emitting diode
  • the third node N3 ie, the organic light emitting diode
  • the voltage of the anode of the tube is initialized, and the difference between the initialization voltage Vre and the second power supply voltage ELVSS is smaller than the light-emitting voltage of the organic light emitting diode OLED to avoid abnormal light emission of the organic light emitting diode after initialization, thereby improving display quality.
  • the initialization voltage Vre is equal to or smaller than the second power source voltage ELVSS.
  • the initialization voltage Vre is equal to or lower than the second power supply voltage ELVSS, so that the organic light emitting diode after the initialization is in a reverse-off state, preventing abnormal light emission of the organic light emitting diode, and improving display quality.
  • the reset circuit 120 includes a first transistor T1
  • the threshold compensation circuit 130 includes a second transistor T2
  • the first data write circuit 140 includes a third transistor.
  • T3 the reference voltage writing circuit 150 includes a fourth transistor T4
  • the lighting control circuit 110 includes a fifth transistor T5
  • the initialization circuit 160 includes a sixth transistor T6.
  • the gate of the driving transistor DT is electrically connected to the first node N1; the first pole of the driving transistor DT is electrically connected to the first power line to receive The first power supply voltage ELVDD; the second pole of the driving transistor DT is electrically connected to the fourth node N4.
  • the first pole of the organic light emitting diode OLED is electrically connected to the third node N3; the second pole of the organic light emitting diode OLED is electrically connected to the second power line to receive the second power voltage ELVSS.
  • the first end of the storage capacitor C is electrically connected to the first node N1; the second end of the storage capacitor C is electrically connected to the second node N2.
  • the gate of the first transistor T1 is electrically connected to the reset control signal line to receive the reset control signal Reset; the first pole of the first transistor T1 is electrically connected to the reset voltage line to receive the reset voltage Vint; the second pole of the first transistor T1 is The first node N1 is electrically connected.
  • a gate of the second transistor T2 is electrically connected to the first scan signal line to receive the first scan signal Gate; a first pole of the second transistor T2 is electrically connected to the first node N1; and a second pole and a fourth of the second transistor T2 Node N4 is electrically connected.
  • the gate of the third transistor T3 is electrically connected to the first scan signal line to receive the first scan signal Gate; the first pole of the third transistor T3 is electrically connected to the data signal line to receive the data signal Data; the second of the third transistor T3 The pole is electrically connected to the second node N2.
  • the gate of the fourth transistor T4 is electrically connected to the second scan signal line to receive the second scan signal Scan; the first pole of the fourth transistor T4 is electrically connected to the reference voltage line to receive the reference voltage Vref; the second of the fourth transistor T4 The pole is electrically connected to the second node N2.
  • the gate of the fifth transistor T5 is electrically connected to the light emission control signal line to receive the light emission control signal EM; the first pole of the fifth transistor T5 is electrically connected to the third node N3; and the second pole and the fourth node N4 of the fifth transistor T5 Electrical connection.
  • a gate of the sixth transistor T6 and a first scan signal line or complex The bit control signal line is electrically connected to receive the first scan signal Gate or the reset control signal Reset; the first pole of the sixth transistor T6 is electrically connected to the reset voltage line to receive the reset voltage Vint; the second pole and the third of the sixth transistor T6 Node N3 is electrically connected.
  • the first pole of the sixth transistor T6 includes but is not limited to the case where the reset voltage line is electrically connected to receive the reset voltage Vint as shown in FIG. 3, and the first pole of the sixth transistor T6 can also be initialized with the voltage.
  • the line is electrically connected to receive the initialization voltage Vre.
  • the driving transistor DT, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all P. Type transistor.
  • the driving transistor DT, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all thin films.
  • a transistor such as a P-type thin film transistor.
  • the transistors used in the embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other switching devices having the same characteristics.
  • the source and drain of the transistor used here may be structurally symmetrical, so that the source and the drain may be structurally indistinguishable.
  • the first pole of the transistor of the embodiment of the present disclosure in order to distinguish the two poles of the transistor except the gate, one of the first poles and the other pole are directly described, so the first pole of all or part of the transistors in the embodiment of the present disclosure
  • the second pole is interchangeable as needed.
  • the first pole of the transistor of the embodiment of the present disclosure may be a source
  • the second pole may be a drain; or the first extreme drain of the transistor and the second source of the second.
  • the transistor can be divided into N-type and P-type transistors according to the characteristics of the transistor, and the embodiment of the present disclosure drives the transistor DT, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the The five transistors T5 and the sixth transistor T6 are both P-type transistors as an example. Based on the description and teachings of the implementation of the present disclosure, those skilled in the art can easily realize the implementation of the N-type transistor or the combination of the N-type and P-type transistors in the embodiments of the present disclosure without making creative efforts. These implementations are also within the scope of the present disclosure.
  • the pixel circuit 100 provided by the embodiment of the present disclosure further includes a second data writing circuit 170.
  • the second data write circuit 170 is configured to receive the reset control signal Reset and the data signal Data and write the data signal Data to the second node N2 according to the reset control signal Reset.
  • the reset circuit 120 includes a first transistor T1
  • the threshold compensation circuit 130 includes a second transistor T2
  • the first data write circuit 140 includes a third transistor T3
  • the reference voltage write circuit 150 includes a fourth transistor T4
  • the illumination control circuit 110 includes a fifth transistor T5
  • the initialization circuit 160 includes a sixth transistor T6
  • the second data write circuit 170 includes a seventh transistor T7.
  • the gate of the driving transistor DT is electrically connected to the first node N1; the first pole of the driving transistor DT is electrically connected to the first power line to receive The first power supply voltage ELVDD; the second pole of the driving transistor DT is electrically connected to the fourth node N4.
  • the first pole of the organic light emitting diode OLED is electrically connected to the third node N3; the second pole of the organic light emitting diode OLED is electrically connected to the second power line to receive the second power voltage ELVSS.
  • the first end of the storage capacitor C is electrically connected to the first node N1; the second end of the storage capacitor C is electrically connected to the second node N2.
  • the gate of the first transistor T1 is electrically connected to the reset control signal line to receive the reset control signal Reset; the first pole of the first transistor T1 is electrically connected to the reset voltage line to receive the reset voltage Vint; the second pole of the first transistor T1 is The first node N1 is electrically connected.
  • a gate of the second transistor T2 is electrically connected to the first scan signal line to receive the first scan signal Gate; a first pole of the second transistor T2 is electrically connected to the first node N1; and a second pole and a fourth of the second transistor T2 Node N4 is electrically connected.
  • the gate of the third transistor T3 is electrically connected to the first scan signal line to receive the first scan signal Gate; the first pole of the third transistor T3 is electrically connected to the data signal line to receive the data signal Data; the second of the third transistor T3 The pole is electrically connected to the second node N2.
  • the gate of the fourth transistor T4 is electrically connected to the second scan signal line to receive the second scan signal Scan; the first pole of the fourth transistor T4 is electrically connected to the reference voltage line to receive the reference voltage Vref; the second of the fourth transistor T4 The pole is electrically connected to the second node N2.
  • the gate of the fifth transistor T5 is electrically connected to the light emission control signal line to receive the light emission control signal EM; the first pole of the fifth transistor T5 is electrically connected to the third node N3; and the second pole and the fourth node N4 of the fifth transistor T5 Electrical connection.
  • the gate of the sixth transistor T6 is electrically connected to the first scan signal line or the reset control signal line to receive the first scan signal Gate or the reset control signal Reset; the first pole of the sixth transistor T6 is electrically connected to the reset voltage line to receive the reset The voltage Vint; the second pole of the sixth transistor T6 is electrically connected to the third node N3.
  • the gate of the seventh transistor T7 is electrically connected to the reset control signal line to receive the reset control signal Reset; the first pole of the seventh transistor T7 is electrically connected to the data signal line to receive the data signal Data; the second pole of the seventh transistor T7 is The second node N2 is electrically connected.
  • the first pole of the sixth transistor T6 includes but is not limited to the case where the reset voltage line is electrically connected to receive the reset voltage Vint as shown in FIG. 5, and the first pole of the sixth transistor T6 is also It may be electrically connected to the initialization voltage line to receive the initialization voltage Vre.
  • the driving transistor DT, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh Transistor T7 is a P-type transistor.
  • the driving transistor DT, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh Transistor T7 is a thin film transistor such as a P-type thin film transistor.
  • the embodiment of the present disclosure further provides a display panel 10, as shown in FIG. 6, the display panel 10 includes the pixel circuit 100 provided by any embodiment of the present disclosure.
  • the display panel 10 includes a plurality of pixel circuits 100 arranged in a matrix, each of the pixel circuits 100 is configured to drive at least one sub-pixel to emit light, and the at least one sub-pixel may emit red, green, and blue light. Or white light, etc.
  • the display panel 10 provided by the embodiment of the present disclosure further includes: a data driver 11 , a scan driver 12 , and a controller 13 .
  • the data driver 11 is configured to supply the data signal Data to the pixel circuit 100 in accordance with an instruction of the controller 13;
  • the scan driver 12 is configured to provide the pixel circuit 100 with the light emission control signal EM, the first scan signal Gate, according to an instruction of the controller 13.
  • the data driver 11, the scan driver 12, and the controller 13 may each be implemented by an application specific integrated circuit chip, or may be implemented by circuitry or by software, hardware (circuit), firmware, or any combination thereof.
  • the scan driver 12 can be implemented by a GOA (gate on array) gate drive circuit.
  • the data driver 11, the scan driver 12, and the controller 13 may include a processor, a memory.
  • the processor may process the data signals, and may include various computing structures, such as a Complex Instruction Set Computer (CISC) structure, a Structured Reduced Instruction Set Computer (RISC) structure, or a combination of multiple instruction sets. Structure.
  • the processor can also be a microprocessor, such as an X86 processor or an ARM processor, or can be a digital processor (DSP) or the like.
  • DSP digital processor
  • the processor can control other components to perform the desired functions.
  • the memory may hold instructions and/or data executed by the processor.
  • the memory can include one or more computer program products, which can include various forms of computer readable storage Storage medium, such as volatile memory and/or non-volatile memory.
  • the volatile memory may include, for example, a random access memory (RAM) and/or a cache or the like.
  • the nonvolatile memory may include, for example, a read only memory (ROM), a hard disk, a flash memory, or the like.
  • One or more computer program instructions can be stored on the computer readable storage medium, and the processor can execute the program instructions to implement a desired function (implemented by a processor) in an embodiment of the present disclosure.
  • Various applications and various data may also be stored in the computer readable storage medium, such as various data used and/or generated by the application, and the like.
  • the display panel 10 further includes a data signal line, an illumination control signal line, a first scan signal line, a second scan signal line, and a reset control signal line (not shown in FIG. 6).
  • the data driver 11 supplies the data signal Data to the pixel circuit 100 through the data signal line;
  • the scan driver 12 supplies illumination to each of the pixel circuits 100 through the light emission control signal line, the first scan signal line, the second scan signal line, and the reset control signal line, respectively.
  • the display panel 10 further includes a power source (a voltage source or a current source, not shown), a first power line, a second power line, a reference voltage line, and a reset voltage line (not shown in FIG. 6).
  • the power source is configured to supply the first power source voltage ELVDD, the second power source voltage ELVSS, the reference voltage Vref, the reset voltage Vint, and the like to the pixel circuit 100 through the first power line, the second power line, the reference voltage line, and the reset voltage line, respectively.
  • the embodiment of the present disclosure further provides a display device 1.
  • the display device 1 includes the display panel 10 provided by any embodiment of the present disclosure.
  • the display device may include any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the embodiment of the present disclosure also provides a driving method of the pixel circuit 100 as shown in FIG.
  • the driving method includes a reset phase t1, a data write and threshold compensation phase t2, a voltage drop compensation phase t3, and an illumination phase t4 in a frame display period.
  • the lighting control signal EM is set to the off voltage
  • the reset control signal Reset is set to the turn-on voltage
  • the first scan signal Gate is set to the off voltage
  • the second scan signal Scan is set to the turn-on voltage
  • the data signal Data is set to be invalid data. signal.
  • the lighting control signal EM is set to the off voltage
  • the reset control signal Reset is set to the off voltage
  • the first scan signal Gate is set to the turn-on voltage.
  • the second scan signal Scan is set to be a shutdown voltage
  • the data signal Data is set to be a valid data signal.
  • the illumination control signal EM is set to the off voltage
  • the reset control signal Reset is set to the off voltage
  • the first scan signal Gate is set to the off voltage
  • the second scan signal Scan is set to the on voltage
  • the data signal Data is set to Invalid data signal.
  • the lighting control signal EM is set to the turn-on voltage
  • the reset control signal Reset is set to the off voltage
  • the first scan signal Gate is set to the off voltage
  • the second scan signal Scan is set to the turn-on voltage
  • the data signal Data is set to be invalid data. signal.
  • the turn-on voltage in the embodiment of the present disclosure refers to a voltage that enables the first and second stages of the respective transistors to be turned on
  • the turn-off voltage refers to a voltage that can turn off the first and second stages of the respective transistors.
  • the turn-on voltage is a low voltage (for example, 0V)
  • the turn-off voltage is a high voltage (for example, 5V)
  • the turn-on voltage is a high voltage (for example, 5V)
  • the voltage is a low voltage (eg, 0V).
  • the turn-on voltage is a low voltage (for example, 0 V)
  • the turn-off voltage is a high voltage (for example, 5 V).
  • the invalid data signal is, for example, a low voltage signal (for example, 0 V)
  • the valid data signal is, for example, a signal including light emission data information.
  • a high voltage signal is taken as an example in FIGS. 8 to 11 .
  • the illumination control signal EM is the off voltage
  • the reset control signal Reset is the on voltage
  • the first scan signal Gate is the off voltage
  • the second scan signal Scan is the on voltage
  • Data is an invalid data signal.
  • the first transistor T1 and the fourth transistor T4 are in an on state
  • the second transistor T2, the third transistor T3, and the fifth transistor T5 are in a closed state.
  • the first transistor T1 transmits the reset voltage Vint to the first node N1
  • the fourth transistor T4 transmits the reference voltage Vref to the second node N2.
  • the reset circuit receives the reset control signal Reset and writes the reset voltage Vint to the first node N1 according to the reset control signal Reset;
  • the reference voltage write circuit receives the second scan signal Scan and writes to the second node N2 according to the second scan signal Scan
  • the reference voltage Vref is input.
  • the illumination control signal EM is the off voltage
  • the reset control signal Reset is the off voltage
  • the first scan signal Gate is the on voltage
  • the second scan signal Scan is the off voltage
  • the data signal Data is the valid data. signal.
  • the second transistor T2 and the third transistor T3 are in an on state
  • the first transistor T1, the fourth transistor T4, and the fifth transistor T5 are in a closed state.
  • the third transistor T3 transmits the voltage Vdata of the valid data signal to the first
  • the voltage of the second node N2 and the second node N2 is changed from Vref of the reset phase t1 to Vdata, that is, the first data writing circuit receives the first scan signal Gate and the data signal Data and according to the first scan signal Gate to the second node N2. Write data signal Data.
  • the second transistor T2 is turned on to connect the driving transistor DT into a diode structure, and the voltage of the first node N1 is ELVDD+Vth, wherein ELVDD is the first power voltage, and Vth is the threshold voltage of the driving transistor, that is, the threshold compensation circuit receives the first A scan signal Gate performs threshold voltage compensation on the voltage of the first node N1 according to the first scan signal Gate. At this stage, the voltage across the storage capacitor C is ELVDD+Vth-Vdata.
  • the light emission control signal EM is a turn-off voltage
  • the reset control signal Reset is a turn-off voltage
  • the first scan signal Gate is a turn-off voltage
  • the second scan signal Scan is an turn-on voltage
  • the data signal Data is an invalid data signal.
  • the fourth transistor T4 is in an on state, and the first transistor T1, the second transistor T2, the third transistor T3, and the fifth transistor T5 are in a closed state. At this time, the fourth transistor T4 transmits the reference voltage Vref to the second node N2 again. Due to the bootstrap action of the storage capacitor C (ie, the voltage across the storage capacitor does not abruptly change), the voltage of the first node N1 becomes ELVDD+Vth. -Vdata+Vref.
  • the light-emission control signal EM is the turn-on voltage
  • the reset control signal Reset is the turn-off voltage
  • the first scan signal Gate is the turn-off voltage
  • the second scan signal Scan is the turn-on voltage
  • the data signal Data is the invalid data signal.
  • the fourth transistor T4 and the fifth transistor are in an on state, and the first transistor T1, the second transistor T2, and the third transistor T3 are in a closed state.
  • the voltage of the first node N1 is maintained at ELVDD+Vth-Vdata+Vref
  • the illuminating current Ioled flows into the organic light emitting diode OLED through the driving transistor DT and the fifth transistor T5, and the organic light emitting diode OLED emits light. That is, the light emission control circuit receives the light emission control signal EM and controls the organic light emitting diode OLED to emit light according to the light emission control signal EM.
  • the illuminating current Ioled satisfies the following saturation current formula:
  • ⁇ n is the mobility of the driving transistor channel
  • Cox per unit area of the driving transistor channel capacitance W and L are the channel width and channel length of the driving transistor
  • Vgs is the gate-source voltage of the driving transistor (driving transistor The difference between the gate voltage and the source voltage).
  • the current flowing through the OLED is independent of the threshold voltage of the driving transistor DT, and is independent of the voltage of ELVDD. Therefore, the pixel circuit compensates very well for the threshold voltage of the driving transistor DT and the IR drop of the ELVDD trace.
  • the sixth transistor T6 when the gate of the sixth transistor T6 is electrically connected to the first scan signal line to receive the first scan signal Gate, in the data writing and threshold compensation phase t2, the sixth transistor T6 is in an on state, and the third node N3 is
  • the potential is the initialization voltage Vre (for example, the initialization voltage Vre is equal to the reset voltage Vint).
  • the difference between the initialization voltage Vre and the second power supply voltage ELVSS is smaller than the light-emitting voltage of the organic light-emitting diode OLED.
  • the initialization voltage Vre is equal to or less than the second power supply voltage ELVSS, which can prevent abnormal light emission of the organic light-emitting diode and improve display quality.
  • the sixth transistor T6 In the light-emitting phase t4, the sixth transistor T6 is in a closed state, and when the black screen is displayed, the voltage of the third node N3 can be discharged by the leakage current of the sixth transistor T6, thereby ensuring low brightness at the black screen and improving the display effect. .
  • the sixth transistor T6 when the gate of the sixth transistor T6 is electrically connected to the reset control signal line to receive the reset control signal Reset, in the reset phase t1, the sixth transistor T6 is in an on state, and the potential of the third node N3 is an initialization voltage Vre (for example, The initialization voltage Vre is equal to the reset voltage Vint).
  • the difference between the initialization voltage Vre and the second power supply voltage ELVSS is smaller than the light-emitting voltage of the organic light-emitting diode OLED.
  • the initialization voltage Vre is equal to or less than the second power supply voltage ELVSS, which can prevent abnormal light emission of the organic light-emitting diode and improve display quality.
  • the sixth transistor T6 In the light-emitting phase t4, the sixth transistor T6 is in a closed state, and when the black screen is displayed, the voltage of the third node N3 can be discharged by the leakage current of the sixth transistor T6, thereby ensuring low brightness at the black screen and improving the display effect. .
  • the initialization circuit receives the first scan signal Gate or the reset control signal Reset and writes the initialization voltage Vre to the third node N3 according to the first scan signal Gate or the reset control signal Reset.
  • the initialization voltage Vre is, for example, equal to the reset voltage Vint.
  • the ratio of the duration of the lighting period t4 to the one-frame display period F can be adjusted.
  • the luminance of the light can be controlled by adjusting the length of the light-emitting phase t4 to the ratio of one frame display period F.
  • the ratio of the length of the adjustment lighting period t4 to the one-frame display period F is achieved by controlling the scanning driver 12 in the display panel.
  • the driving method provided by the embodiment of the present disclosure includes a luminescence continuation phase in a frame display period F, and the luminescence continuation phase includes at least one shutdown sub-phase and at least one illuminating sub-phase.
  • the luminescence continuation phase includes n closed sub-phases (t51...t5n) and n illuminating sub-phases (t61...t6n).
  • the illumination control signal EM is set to be the off voltage
  • the reset control signal Reset is set to the off voltage
  • the first scan signal Gate is set to Turning off the voltage, setting the second scan signal Scan to be the turn-on voltage, setting the data signal Data to be the invalid data signal; in the illuminating sub-stage, setting the light-emission control signal EM to the turn-on voltage, setting the reset control signal Reset to the turn-off voltage, and setting the first scan signal
  • the gate is a turn-off voltage
  • the second scan signal Scan is set to be the turn-on voltage
  • the data signal Data is set to be an invalid data signal.
  • the arrangement can switch the organic light emitting diode between the light emitting state and the non-light emitting state multiple times in a frame display period, that is, increase the frequency of the organic light emitting diode to emit light, and reduce or avoid the result of the visual persistence effect. Blinking phenomenon.
  • the flicker phenomenon can be better improved.
  • the ratio of the duration of the lighting phase t4 and the total duration of all the lighting sub-stages to the one-frame display period F can be adjusted.
  • the duration of each shutdown sub-phase is equal to the sum of the duration of the reset phase t1, the duration of the data writing and threshold compensation phase t2, and the duration of the voltage drop compensation phase t3, each
  • the duration of the illuminating sub-phase is equal to the duration of the illuminating phase t4.
  • the embodiment of the present disclosure further provides a driving method of the pixel circuit 100 as shown in FIG. 5, including a reset phase t1, a data writing and threshold compensation phase t2, a voltage drop compensation phase t3, and a frame display period. Illumination phase t4.
  • the illumination control signal EM is set to the off voltage
  • the reset control signal Reset is set to the on voltage
  • the first scan signal Gate is set to the off voltage
  • the second scan signal Scan is set to the off voltage
  • the data signal Data is set to the valid data. signal.
  • the illumination control signal EM is set to the off voltage
  • the reset control signal Reset is set to the off voltage
  • the first scan signal Gate is set to the on voltage
  • the second scan signal Scan is set to the off voltage
  • the data is set.
  • the signal Data is a valid data signal.
  • the illumination control signal EM is set to the off voltage
  • the reset control signal Reset is set to the off voltage
  • the first scan signal Gate is set to the off voltage
  • the second scan signal Scan is set to the on voltage
  • the data signal Data is set to Invalid data signal.
  • the lighting control signal EM is set to the turn-on voltage
  • the reset control signal Reset is set to the off voltage
  • the first scan signal Gate is set to the off voltage
  • the second scan signal is set.
  • Scan is the turn-on voltage
  • the data signal Data is set to be an invalid data signal.
  • the illumination control signal EM is the off voltage
  • the reset control signal Reset is the on voltage
  • the first scan signal Gate is the off voltage
  • the second scan signal Scan is the off voltage
  • Data is a valid data signal.
  • the first transistor T1 and the seventh transistor T7 are in an on state
  • the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are in a closed state.
  • the first transistor T1 transmits the reset voltage Vint to the first node N1
  • the seventh transistor T7 transmits the voltage Vdata of the valid data signal to the second node N2.
  • the reset circuit receives the reset control signal Reset and writes the reset voltage Vint to the first node N1 according to the reset control signal Reset;
  • the second data write circuit receives the reset control signal Reset and the data signal Data and proceeds to the second according to the reset control signal Reset Node N2 writes the data signal Data.
  • the illumination control signal EM is the off voltage
  • the reset control signal Reset is the off voltage
  • the first scan signal Gate is the on voltage
  • the second scan signal Scan is the off voltage
  • the data signal Data is the valid data. signal.
  • the second transistor T2 and the third transistor T3 are in an on state
  • the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are in a closed state.
  • the third transistor T3 continues to transmit the voltage Vdata of the valid data signal to the second node N2, that is, the first data writing circuit receives the first scan signal Gate and the data signal Data and proceeds to the second according to the first scan signal Gate. Node N2 writes the data signal Data.
  • the second transistor T2 is turned on to connect the driving transistor DT into a diode structure, and the voltage of the first node N1 is ELVDD+Vth, wherein ELVDD is the first power voltage, and Vth is the threshold voltage of the driving transistor, that is, the threshold compensation circuit receives the first
  • ELVDD is the first power voltage
  • Vth is the threshold voltage of the driving transistor
  • the compensation voltage is the sum of the first power voltage ELVDD and the threshold voltage Vth of the drive transistor ELVDD+Vth.
  • the voltage difference across the storage capacitor C is ELVDD+Vth-Vdata.
  • the light emission control signal EM is a turn-off voltage
  • the reset control signal Reset is a turn-off voltage
  • the first scan signal Gate is a turn-off voltage
  • the second scan signal Scan is an turn-on voltage
  • the data signal Data is an invalid data signal.
  • the fourth transistor T4 is in an on state, and the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, and the seventh transistor T7 are in a closed state.
  • the fourth transistor T4 transmits the reference voltage Vref to the second node N2 again, due to the bootstrap action of the storage capacitor C (ie, the voltage across the storage capacitor does not change), the first The voltage of the node N1 becomes ELVDD+Vth-Vdata+Vref.
  • the light-emission control signal EM is the turn-on voltage
  • the reset control signal Reset is the turn-off voltage
  • the first scan signal Gate is the turn-off voltage
  • the second scan signal Scan is the turn-on voltage
  • the data signal Data is the invalid data signal.
  • the fourth transistor T4, the fifth transistor, and the seventh transistor T7 are in an on state, and the first transistor T1, the second transistor T2, and the third transistor T3 are in a closed state.
  • the voltage of the first node N1 is maintained at ELVDD+Vth-Vdata+Vref, and the illuminating current Ioled flows into the organic light emitting diode OLED through the driving transistor DT and the fifth transistor T5, and the organic light emitting diode OLED emits light. That is, the light emission control circuit receives the light emission control signal EM and controls the organic light emitting diode OLED to emit light according to the light emission control signal EM.
  • the illuminating current Ioled satisfies the following saturation current formula:
  • ⁇ n is the channel mobility of the driving transistor
  • Cox is the channel capacitance per unit area of the driving transistor
  • W and L are the channel width and channel length of the driving transistor, respectively
  • Vgs is the gate-source voltage of the driving transistor (driving transistor) The difference between the gate voltage and the source voltage).
  • the current flowing through the OLED is independent of the threshold voltage of the driving transistor DT, and is independent of the voltage of ELVDD. Therefore, the pixel circuit compensates very well for the threshold voltage of the driving transistor DT and the IR drop of the ELVDD trace.
  • the driving method of the driving circuit shown in FIG. 5 starts writing data signals to the second node N2 in the reset phase t1, increasing the time for writing the data signals, and simultaneously
  • the reset phase t1 is prevented from being converted to the data writing and the threshold compensation phase t2
  • the voltage of the second node N2 is excessively changed, which is beneficial to the stability of the circuit.
  • the sixth transistor T6 when the gate of the sixth transistor T6 is electrically connected to the first scan signal line to receive the first scan signal Gate, in the data writing and threshold compensation phase t2, the sixth transistor T6 is in an on state, and the third node N3 is
  • the potential is the initialization voltage Vre (for example, the initialization voltage Vre is equal to the reset voltage Vint).
  • the difference between the initialization voltage Vre and the second power supply voltage ELVSS is smaller than the light-emitting voltage of the organic light-emitting diode OLED.
  • the initialization voltage Vre is equal to or less than the second power supply voltage ELVSS, which can prevent abnormal light emission of the organic light-emitting diode and improve display quality.
  • the sixth transistor T6 In the light-emitting phase t4, the sixth transistor T6 is in a closed state, and when the black screen is displayed, the voltage of the third node N3 can be discharged by the leakage current of the sixth transistor T6, thereby ensuring low brightness at the black screen, and improving display effect.
  • the sixth transistor T6 when the gate of the sixth transistor T6 is electrically connected to the reset control signal line to receive the reset control signal Reset, in the reset phase t1, the sixth transistor T6 is in an on state, and the potential of the third node N3 is an initialization voltage Vre (for example, The initialization voltage Vre is equal to the reset voltage Vint).
  • the difference between the initialization voltage Vre and the second power supply voltage ELVSS is smaller than the light-emitting voltage of the organic light-emitting diode OLED.
  • the initialization voltage Vre is equal to or less than the second power supply voltage ELVSS, which can prevent abnormal light emission of the organic light-emitting diode and improve display quality.
  • the sixth transistor T6 In the light-emitting phase t4, the sixth transistor T6 is in a closed state, and when the black screen is displayed, the voltage of the third node N3 can be discharged by the leakage current of the sixth transistor T6, thereby ensuring low brightness at the black screen and improving the display effect. .
  • the initialization circuit receives the first scan signal Gate or the reset control signal Reset and writes the initialization voltage Vre to the third node N3 according to the first scan signal Gate or the reset control signal Reset.
  • the initialization voltage Vre is, for example, equal to the reset voltage Vint.
  • the ratio of the duration of the lighting period t4 to the one-frame display period F can be adjusted.
  • the luminance of the light can be controlled by adjusting the length of the light-emitting phase t4 to the ratio of one frame display period F.
  • the ratio of the length of the adjustment lighting period t4 to the one-frame display period F is achieved by controlling the scanning driver 12 in the display panel.
  • the driving method provided by the embodiment of the present disclosure includes a luminescence continuation phase in a frame display period F, and the luminescence continuation phase includes at least one shutdown sub-phase and at least one illuminating sub-phase.
  • the luminescence continuation phase includes n closed sub-phases (t51...t5n) and n illuminating sub-phases (t61...t6n).
  • the lighting control signal EM is set to the off voltage
  • the reset control signal Reset is set to the off voltage
  • the first scan signal Gate is set to the off voltage
  • the second scan signal Scan is set to the turn-on voltage
  • the data signal Data is set to the invalid data.
  • the illuminating control signal EM is set to the turn-on voltage
  • the reset control signal Reset is set to the off voltage
  • the first scan signal Gate is set to the off voltage
  • the second scan signal Scan is set to the turn-on voltage
  • the data signal Data is set to Invalid data signal.
  • the arrangement can switch the organic light emitting diode between the light emitting state and the non-light emitting state multiple times in a frame display period, that is, increase the frequency of the organic light emitting diode to emit light, and reduce or avoid the result of the visual persistence effect. Blinking phenomenon.
  • the ratio of the duration of the lighting phase t4 and the total duration of all the lighting sub-stages to the one-frame display period F can be adjusted.
  • the duration of each shutdown sub-phase is equal to the sum of the duration of the reset phase t1, the duration of the data writing and threshold compensation phase t2, and the duration of the voltage drop compensation phase t3, each
  • the duration of the illuminating sub-phase is equal to the duration of the illuminating phase t4.
  • Embodiments of the present disclosure provide a pixel circuit, a display panel, a display device, and a driving method, which can perform resistance voltage drop and threshold voltage compensation on a display panel, thereby improving uniformity of driving current, thereby improving display panel uniformity.
  • the leakage current is reduced to ensure high contrast in the black state, and the ratio of the illumination time to the display period of one frame is adjusted to ensure accurate display under low gray scale conditions.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of El Displays (AREA)

Abstract

一种像素电路、显示面板、显示设备及驱动方法，该像素电路(100)包括存储电容、有机发光二极管、驱动晶体管、发光控制电路(110)、复位电路(120)、阈值补偿电路(130)、第一数据写入电路(140)、参考电压写入电路(150)以及初始化电路(160)。该像素电路、显示面板、显示设备及驱动方法，可对显示面板进行电阻压降和阈值电压补偿，提高了驱动电流的均匀性，进而提高了显示面板显示的均匀性，同时减小漏电流以保证黑态时的高对比度，以及通过调整发光时间占一帧显示时间段的比例使得在低灰阶条件下保证精确显示。

Description

像素电路、显示面板、显示设备及驱动方法 技术领域
本公开的实施例涉及一种像素电路、显示面板、显示设备及驱动方法。
背景技术
在显示领域，有机发光二极管(OLED)显示面板具有自发光、对比度高、能耗低、视角广、响应速度快、可用于挠曲性面板、使用温度范围广、制造简单等特点，具有广阔的发展前景。
由于上述特点，有机发光二极管(OLED)显示面板可以适用于手机、显示器、笔记本电脑、数码相机、仪器仪表等具有显示功能的装置。
发明内容
本公开的实施例提供一种像素电路，包括：存储电容，包括与第一节点连接的第一端和与第二节点连接的第二端；有机发光二极管，包括与第三节点连接的第一极；驱动晶体管，包括与所述第一节点连接的栅极，其中，所述驱动晶体管被配置为根据所述第一节点的电压控制所述有机发光二极管发光；发光控制电路，被配置为接收发光控制信号并根据所述发光控制信号控制所述有机发光二极管发光或关断；复位电路，被配置为接收复位控制信号并根据所述复位控制信号向所述第一节点写入复位电压；阈值补偿电路，被配置为接收第一扫描信号并根据所述第一扫描信号向所述第一节点写入补偿电压，其中，所述补偿电压为第一电源电压与所述驱动晶体管的阈值电压之和；第一数据写入电路，被配置为接收第一扫描信号和数据信号并根据所述第一扫描信号向所述第二节点写入所述数据信号；参考电压写入电路，被配置为接收第二扫描信号并根据所述第二扫描信号向所述第二节点写入参考电压；以及初始化电路，被配置为接收所述第一扫描信号或所述复位控制信号并根据所述第一扫描信号或所述复位控制信号向第三节点写入所述初始化电压。
例如，在本公开实施例提供的像素电路中，所述初始化电压等于所述复 位电压。
例如，在本公开实施例提供的像素电路中，所述有机发光二极管还包括第二极，所述有机发光二极管的第二极与第二电源线电连接以接收第二电源电压，所述有机发光二极管的第一极为阳极，所述有机发光二极管的第二极为阴极，所述初始化电压与所述第二电源电压之差小于所述有机发光二极管的起亮电压。
例如，在本公开实施例提供的像素电路中，所述初始化电压小于等于所述第二电源电压。
例如，在本公开实施例提供的像素电路中，所述复位电路包括第一晶体管，所述阈值补偿电路包括第二晶体管，所述第一数据写入电路包括第三晶体管，所述参考电压写入电路包括第四晶体管，所述发光控制电路包括第五晶体管，所述初始化电路包括第六晶体管。
例如，在本公开实施例提供的像素电路中，所述驱动晶体管的栅极与所述第一节点电连接，所述驱动晶体管的第一极与第一电源线电连接以接收第一电源电压，所述驱动晶体管的第二极与第四节点电连接；所述有机发光二极管的第一极与所述第三节点电连接，所述有机发光二极管的第二极与第二电源线电连接以接收第二电源电压；所述存储电容的第一端与所述第一节点电连接，所述存储电容的第二端与所述第二节点电连接；所述第一晶体管的栅极与复位控制信号线电连接以接收所述复位控制信号，所述第一晶体管的第一极与复位电压线电连接以接收所述复位电压，所述第一晶体管的第二极与所述第一节点电连接；所述第二晶体管的栅极与第一扫描信号线电连接以接收第一扫描信号，所述第二晶体管的第一极与所述第一节点电连接，所述第二晶体管的第二极与所述第四节点电连接；所述第三晶体管的栅极与所述第一扫描信号线电连接以接收所述第一扫描信号，所述第三晶体管的第一极与数据信号线电连接以接收所述数据信号，所述第三晶体管的第二极与所述第二节点电连接；所述第四晶体管的栅极与第二扫描信号线电连接以接收所述第二扫描信号，所述第四晶体管的第一极与参考电压线电连接以接收所述参考电压，所述第四晶体管的第二极与所述第二节点电连接；所述第五晶体管的栅极与发光控制信号线电连接以接收所述发光控制信号，所述第五晶体管的第一极与所述第三节点电连接，所述第五晶体管的第二极与所述第四节 点电连接；所述第六晶体管的栅极与第一扫描信号线或复位控制信号线电连接以接收所述第一扫描信号或所述复位控制信号，所述第六晶体管的第一极与所述复位电压线电连接以接收所述复位电压，所述第六晶体管的第二极与所述第三节点电连接。
例如，在本公开实施例提供的像素电路中，所述驱动晶体管、所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管以及所述第六晶体管均为P型晶体管。
例如，在本公开实施例提供的像素电路中，所述驱动晶体管、所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管以及所述第六晶体管均为薄膜晶体管。
例如，本公开实施例提供的像素电路，还包括第二数据写入电路，被配置为接收所述复位控制信号和所述数据信号并根据所述复位控制信号向所述第二节点写入所述数据信号。
例如，在本公开实施例提供的像素电路中，所述复位电路包括第一晶体管，所述阈值补偿电路包括第二晶体管，所述第一数据写入电路包括第三晶体管，所述参考电压写入电路包括第四晶体管，所述发光控制电路包括第五晶体管，所述初始化电路包括第六晶体管，所述第二数据写入电路包括第七晶体管。
例如，在本公开实施例提供的像素电路中，所述驱动晶体管的栅极与所述第一节点电连接，所述驱动晶体管的第一极与第一电源线电连接以接收第一电源电压，所述驱动晶体管的第二极与第四节点电连接；所述有机发光二极管的第一极与所述第三节点电连接，所述有机发光二极管的第二极与第二电源线电连接以接收第二电源电压；所述存储电容的第一端与所述第一节点电连接，所述存储电容的第二端与所述第二节点电连接；所述第一晶体管的栅极与复位控制信号线电连接以接收所述复位控制信号，所述第一晶体管的第一极与复位电压线电连接以接收所述复位电压，所述第一晶体管的第二极与所述第一节点电连接；所述第二晶体管的栅极与第一扫描信号线电连接以接收第一扫描信号，所述第二晶体管的第一极与所述第一节点电连接，所述第二晶体管的第二极与所述第三节点电连接；所述第三晶体管的栅极与所述第一扫描信号线电连接以接收所述第一扫描信号，所述第三晶体管的第一极 与数据信号线电连接以接收所述数据信号，所述第三晶体管的第二极与所述第二节点电连接；所述第四晶体管的栅极与第二扫描信号线电连接以接收所述第二扫描信号，所述第四晶体管的第一极与参考电压线电连接以接收所述参考电压，所述第四晶体管的第二极与所述第二节点电连接；所述第五晶体管的栅极与发光控制信号线电连接以接收所述发光控制信号，所述第五晶体管的第一极与所述第三节点电连接，所述第五晶体管的第二极与所述第四节点电连接；所述第六晶体管的栅极与第一扫描信号线或复位控制信号线电连接以接收所述第一扫描信号或所述复位控制信号，所述第六晶体管的第一极与所述复位电压线电连接以接收所述复位电压，所述第六晶体管的第二极与所述第三节点电连接；所述第七晶体管的栅极与复位控制信号线电连接以接收所述复位控制信号，所述第七晶体管的第一极与数据信号线电连接以接收所述数据信号，所述第七晶体管的第二极与所述第二节点电连接。
例如，在本公开实施例提供的像素电路中，所述驱动晶体管、所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管以及所述第七晶体管均为P型晶体管。
例如，在本公开实施例提供的像素电路中，所述驱动晶体管、所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管以及所述第七晶体管均为薄膜晶体管。
本公开的实施例还提供一种显示面板，包括本公开任一实施例提供的像素电路。
例如，本公开实施例提供的显示面板，还包括：数据驱动器，被配置为向所述像素电路提供所述数据信号；扫描驱动器，被配置为向所述像素电路提供所述发光控制信号、所述第一扫描信号、所述第二扫描信号以及所述复位控制信号。
本公开的实施例还提供一种显示设备，包括本公开任一实施例提供的显示面板。
本公开的实施例还提供一种本公开实施例提供的像素电路的驱动方法，在一帧显示时间段内，包括复位阶段、数据写入及阈值补偿阶段、压降补偿阶段和发光阶段，其中，在所述复位阶段，设置所述发光控制信号为关闭电压，设置所述复位控制信号为开启电压，设置所述第一扫描信号为关闭电压， 设置所述第二扫描信号为开启电压，设置所述数据信号为无效数据信号；在所述数据写入及阈值补偿阶段，设置所述发光控制信号为关闭电压，设置所述复位控制信号为关闭电压，设置所述第一扫描信号为开启电压，设置所述第二扫描信号为关闭电压，设置所述数据信号为有效数据信号；在所述压降补偿阶段，设置所述发光控制信号为关闭电压，设置所述复位控制信号为关闭电压，设置所述第一扫描信号为关闭电压，设置所述第二扫描信号为开启电压，设置所述数据信号为无效数据信号；在所述发光阶段，设置所述发光控制信号为开启电压，设置所述复位控制信号为关闭电压，设置所述第一扫描信号为关闭电压，设置所述第二扫描信号为开启电压，设置所述数据信号为无效数据信号。
本公开的实施例还提供一种本公开实施例提供的像素电路的驱动方法，在一帧显示时间段内，包括复位阶段、数据写入及阈值补偿阶段、压降补偿阶段和发光阶段，其中，在所述复位阶段，设置所述发光控制信号为关闭电压，设置所述复位控制信号为开启电压，设置所述第一扫描信号为关闭电压，设置所述第二扫描信号为关闭电压，设置所述数据信号为有效数据信号；在所述数据写入及阈值补偿阶段，设置所述发光控制信号为关闭电压，设置所述复位控制信号为关闭电压，设置所述第一扫描信号为开启电压，设置所述第二扫描信号为关闭电压，设置所述数据信号为有效数据信号；在所述压降补偿阶段，设置所述发光控制信号为关闭电压，设置所述复位控制信号为关闭电压，设置所述第一扫描信号为关闭电压，设置所述第二扫描信号为开启电压，设置所述数据信号为无效数据信号；在所述发光阶段，设置所述发光控制信号为开启电压，设置所述复位控制信号为关闭电压，设置所述第一扫描信号为关闭电压，设置所述第二扫描信号为开启电压，设置所述数据信号为无效数据信号。
例如，在本公开实施例提供的驱动方法中，所述发光阶段的时长占一帧显示时间段的比例可被调节。
例如，本公开实施例提供的驱动方法，在一帧显示时间段内，还可以包括发光延续阶段，其中，所述发光延续阶段包括至少一个关闭子阶段和至少一个发光子阶段，在所述关闭子阶段，设置所述发光控制信号为关闭电压，设置所述复位控制信号为关闭电压，设置所述第一扫描信号为关闭电压，设 置所述第二扫描信号为开启电压，设置所述数据信号为无效数据信号；在所述发光子阶段，设置所述发光控制信号为开启电压，设置所述复位控制信号为关闭电压，设置所述第一扫描信号为关闭电压，设置所述第二扫描信号为开启电压，设置所述数据信号为无效数据信号。
例如，在本公开实施例提供的驱动方法中，所述发光阶段的时长和全部所述发光子阶段的总时长之和占一帧显示时间段的比例可被调节。
例如，在本公开实施例提供的驱动方法中，每个所述关闭子阶段的时长等于所述复位阶段的时长、所述数据写入及阈值补偿阶段的时长和所述压降补偿阶段的时长之和，每个所述发光子阶段的时长等于所述发光阶段的时长。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，并非对本公开的限制。
图1是本公开实施例提供的一种像素电路的示意图之一；
图2是本公开实施例提供的一种像素电路的示意图之二；
图3是本公开实施例提供的一种像素电路的示意图之三；
图4是本公开实施例提供的一种像素电路的示意图之四；
图5是本公开实施例提供的一种像素电路的示意图之五；
图6是本公开实施例提供的一种显示面板的示意图；
图7是本公开实施例提供的一种显示设备的示意图；
图8和图9是本公开实施例提供的如图3所示的像素电路的示例性的驱动时序图；以及
图10和图11是本公开实施例提供的如图5所示的像素电路的示例性的驱动时序图。
具体实施方式
下面将结合附图，对本公开实施例中的技术方案进行清楚、完整地描述参考在附图中示出并在以下描述中详述的非限制性示例实施例，更加全面地说明本公开的示例实施例和它们的多种特征及有利细节。应注意的是，图中 示出的特征不是必须按照比例绘制。本公开省略了已知材料、组件和工艺技术的描述，从而不使本公开的示例实施例模糊。所给出的示例仅旨在有利于理解本公开示例实施例的实施，以及进一步使本领域技术人员能够实施示例实施例。因而，这些示例不应被理解为对本公开的实施例的范围的限制。
除非另外特别定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。此外，在本公开各个实施例中，相同或类似的参考标号表示相同或类似的构件。
在有机发光二极管(Organic Light-Emitting Diode,OLED)显示面板中，会存在电阻压降(IR drop)现象，电阻压降是由于显示面板中导线的自身电阻分压造成的，即电流经过显示面板中的导线时，根据欧姆定律，导线上会产生一定的电压降。因此，位于不同位置的像素单元受到电阻压降影响的程度也不相同，这会导致显示面板显示不均匀。因此，需要对OLED显示面板中的电阻压降进行补偿。
而且，在OLED显示面板中，各个像素单元中的驱动晶体管的阈值电压由于制备工艺可能彼此之间存在差异，而且由于例如温度变化的影响，驱动晶体管的阈值电压也会产生漂移的现象。因此，各个驱动晶体管的阈值电压的不同也可能会导致显示面板显示不均匀。因此，这样也导致需要对阈值电压进行补偿。
而且，OLED像素补偿电路中可能存在漏电流，在黑态时仍可能有0.01～0.03尼特(nit)的亮度，导致不能得到真正的纯黑，因此无法实现高对比度。
另外，OLED显示器件的灰阶区分受驱动电路的数据电压控制，在显示低灰阶时(例如，在夜间使用时)，驱动电路在输出低灰阶数据电压的条件下很难做到精确控制。
本公开的实施例提供一种像素电路、显示面板、显示设备及驱动方法，可对显示面板进行电阻压降和阈值电压补偿，提高了驱动电流的均匀性，进而提高了显示面板显示的均匀性，同时减小漏电流以保证黑态时的高对比度，以及通过调整发光时间占一帧显示时间段的比例使得在低灰阶条件下保证精 确显示。
本公开的实施例提供一种像素电路100，如图1所示，该像素电路100包括：存储电容C、有机发光二极管OLED、驱动晶体管DT、发光控制电路110、复位电路120、阈值补偿电路130、第一数据写入电路140、参考电压写入电路150以及初始化电路160。
例如，如图1所示，存储电容C包括与第一节点N1连接的第一端和与第二节点N2连接的第二端。有机发光二极管OLED包括与第三节点N3连接的第一极。驱动晶体管DT包括与第一节点N1连接的栅极；驱动晶体管DT被配置为根据第一节点N1的电压控制有机发光二极管OLED发光。发光控制电路110被配置为接收发光控制信号EM并根据发光控制信号EM控制有机发光二极管OLED发光或关断。复位电路120被配置为接收复位控制信号Reset并根据复位控制信号Reset向第一节点N1写入复位电压Vint。阈值补偿电路130被配置为接收第一扫描信号Gate并根据第一扫描信号Gate向第一节点N1写入补偿电压，所述补偿电压为第一电源电压ELVDD与所述驱动晶体管的阈值电压Vth之和ELVDD+Vth。第一数据写入电路140被配置为接收第一扫描信号Gate和数据信号Data并根据第一扫描信号Gate向第二节点N2写入数据信号Data。参考电压写入电路150被配置为接收第二扫描信号Scan并根据第二扫描信号Scan向第二节点N2写入参考电压Vref。初始化电路160被配置为接收第一扫描信号Gate或复位控制信号Reset并根据第一扫描信号Gate或复位控制信号Reset向第三节点N3写入初始化电压Vre。
例如，如图2所示，在本公开实施例提供的像素电路100中，初始化电压Vre等于复位电压Vint。也就是说，复位电压可以同时用于复位电路120和初始化电路160，这种设置可以节省电压输出端口，简化电路，节省成本。
例如，如图2所示，在本公开实施例提供的像素电路100中，有机发光二极管OLED还包括第二极，有机发光二极管OLED的第二极与第二电源线电连接以接收第二电源电压ELVSS。例如，有机发光二极管的第一极为阳极，有机发光二极管的第二极为阴极。初始化电压Vre与第二电源电压ELVSS之差小于有机发光二极管OLED的起亮电压。这样，初始化电路160向第三节点N3写入初始化电压Vre，可以对第三节点N3的电压(即有机发光二极 管的阳极的电压)初始化，初始化电压Vre与第二电源电压ELVSS之差小于有机发光二极管OLED的起亮电压可以避免初始化后有机发光二极管的异常发光，提升显示品质。
例如，在本公开实施例提供的像素电路100中，初始化电压Vre小于等于第二电源电压ELVSS。例如，初始化电压Vre小于等于第二电源电压ELVSS可以使初始化后有机发光二极管处于反向截止的状态，防止有机发光二极管的异常发光，提升显示品质。
例如，如图3所示，在本公开实施例提供的像素电路100中，复位电路120包括第一晶体管T1，阈值补偿电路130包括第二晶体管T2，第一数据写入电路140包括第三晶体管T3，参考电压写入电路150包括第四晶体管T4，发光控制电路110包括第五晶体管T5，初始化电路160包括第六晶体管T6。
例如，如图3所示，在本公开实施例提供的像素电路100中，驱动晶体管DT的栅极与第一节点N1电连接；驱动晶体管DT的第一极与第一电源线电连接以接收第一电源电压ELVDD；驱动晶体管DT的第二极与第四节点N4电连接。有机发光二极管OLED的第一极与第三节点N3电连接；有机发光二极管OLED的第二极与第二电源线电连接以接收第二电源电压ELVSS。存储电容C的第一端与第一节点N1电连接；存储电容C的第二端与第二节点N2电连接。第一晶体管T1的栅极与复位控制信号线电连接以接收复位控制信号Reset；第一晶体管T1的第一极与复位电压线电连接以接收复位电压Vint；第一晶体管T1的第二极与第一节点N1电连接。第二晶体管T2的栅极与第一扫描信号线电连接以接收第一扫描信号Gate；第二晶体管T2的第一极与第一节点N1电连接；第二晶体管T2的第二极与第四节点N4电连接。第三晶体管T3的栅极与第一扫描信号线电连接以接收第一扫描信号Gate；第三晶体管T3的第一极与数据信号线电连接以接收数据信号Data；第三晶体管T3的第二极与第二节点N2电连接。第四晶体管T4的栅极与第二扫描信号线电连接以接收第二扫描信号Scan；第四晶体管T4的第一极与参考电压线电连接以接收参考电压Vref；第四晶体管T4的第二极与第二节点N2电连接。第五晶体管T5的栅极与发光控制信号线电连接以接收发光控制信号EM；第五晶体管T5的第一极与第三节点N3电连接；第五晶体管T5的第二极与第四节点N4电连接。第六晶体管T6的栅极与第一扫描信号线或复 位控制信号线电连接以接收第一扫描信号Gate或复位控制信号Reset；第六晶体管T6的第一极与复位电压线电连接以接收复位电压Vint；第六晶体管T6的第二极与第三节点N3电连接。
需要说明的是，第六晶体管T6的第一极包括但不局限于图3所示的与复位电压线电连接以接收复位电压Vint的情形，第六晶体管T6的第一极也可以与初始化电压线电连接以接收初始化电压Vre。
例如，在本公开实施例提供的像素电路100中，驱动晶体管DT、第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5以及第六晶体管T6均为P型晶体管。
例如，在本公开实施例提供的像素电路100中，驱动晶体管DT、第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5以及第六晶体管T6均为薄膜晶体管，例如P型薄膜晶体管。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极，所以本公开实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。例如，本公开实施例所述的晶体管的第一极可以为源极，第二极可以为漏极；或者，晶体管的第一极为漏极，第二极为源极。此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管，本公开的实施例以驱动晶体管DT、第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5以及第六晶体管T6均为P型晶体管为例进行说明。基于本公开对该实现方式的描述和教导，本领域普通技术人员在没有做出创造性劳动前提下能够容易想到本公开实施例采用N型晶体管或N型和P型晶体管组合的实现方式，因此，这些实现方式也是在本公开的保护范围内的。
例如，如图4所示，本公开实施例提供的像素电路100还包括第二数据写入电路170。第二数据写入电路170被配置为接收复位控制信号Reset和数据信号Data并根据复位控制信号Reset向第二节点N2写入数据信号Data。
例如，如图5所示，在本公开实施例提供的像素电路100中，复位电路 120包括第一晶体管T1，阈值补偿电路130包括第二晶体管T2，第一数据写入电路140包括第三晶体管T3，参考电压写入电路150包括第四晶体管T4，发光控制电路110包括第五晶体管T5，初始化电路160包括第六晶体管T6，第二数据写入电路170包括第七晶体管T7。
例如，如图5所示，在本公开实施例提供的像素电路100中，驱动晶体管DT的栅极与第一节点N1电连接；驱动晶体管DT的第一极与第一电源线电连接以接收第一电源电压ELVDD；驱动晶体管DT的第二极与第四节点N4电连接。有机发光二极管OLED的第一极与第三节点N3电连接；有机发光二极管OLED的第二极与第二电源线电连接以接收第二电源电压ELVSS。存储电容C的第一端与第一节点N1电连接；存储电容C的第二端与第二节点N2电连接。第一晶体管T1的栅极与复位控制信号线电连接以接收复位控制信号Reset；第一晶体管T1的第一极与复位电压线电连接以接收复位电压Vint；第一晶体管T1的第二极与第一节点N1电连接。第二晶体管T2的栅极与第一扫描信号线电连接以接收第一扫描信号Gate；第二晶体管T2的第一极与第一节点N1电连接；第二晶体管T2的第二极与第四节点N4电连接。第三晶体管T3的栅极与第一扫描信号线电连接以接收第一扫描信号Gate；第三晶体管T3的第一极与数据信号线电连接以接收数据信号Data；第三晶体管T3的第二极与第二节点N2电连接。第四晶体管T4的栅极与第二扫描信号线电连接以接收第二扫描信号Scan；第四晶体管T4的第一极与参考电压线电连接以接收参考电压Vref；第四晶体管T4的第二极与第二节点N2电连接。第五晶体管T5的栅极与发光控制信号线电连接以接收发光控制信号EM；第五晶体管T5的第一极与第三节点N3电连接；第五晶体管T5的第二极与第四节点N4电连接。第六晶体管T6的栅极与第一扫描信号线或复位控制信号线电连接以接收第一扫描信号Gate或复位控制信号Reset；第六晶体管T6的第一极与复位电压线电连接以接收复位电压Vint；第六晶体管T6的第二极与第三节点N3电连接。第七晶体管T7的栅极与复位控制信号线电连接以接收复位控制信号Reset；第七晶体管T7的第一极与数据信号线电连接以接收数据信号Data；第七晶体管T7的第二极与第二节点N2电连接。
需要说明的是，第六晶体管T6的第一极包括但不局限于图5所示的与复位电压线电连接以接收复位电压Vint的情形，第六晶体管T6的第一极也 可以与初始化电压线电连接以接收初始化电压Vre。
例如，在本公开实施例提供的像素电路100中，驱动晶体管DT、第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6以及第七晶体管T7均为P型晶体管。
例如，在本公开实施例提供的像素电路100中，驱动晶体管DT、第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6以及第七晶体管T7均为薄膜晶体管，例如P型薄膜晶体管。
本公开的实施例还提供一种显示面板10，如图6所示，显示面板10包括本公开任一实施例提供的像素电路100。
例如，显示面板10包括多个呈矩阵排布的像素电路100，每个像素电路100用于驱动至少一个子像素发光，该至少一个子像素所发出的可以为红光、绿光、蓝光，亦或者为白光等。
例如，如图6所示，本公开实施例提供的显示面板10还包括：数据驱动器11、扫描驱动器12和控制器13。数据驱动器11被配置为根据控制器13的指令向像素电路100提供数据信号Data；扫描驱动器12被配置为根据控制器13的指令向像素电路100提供发光控制信号EM、第一扫描信号Gate、第二扫描信号Scan以及复位控制信号Reset等。
例如，数据驱动器11、扫描驱动器12和控制器13可以分别由专用集成电路芯片实现，也可以由电路或者采用软件、硬件(电路)、固件或其任意组合方式实现。例如，扫描驱动器12可以由GOA(gate on array)栅极驱动电路实现。
又例如，数据驱动器11、扫描驱动器12和控制器13可以包括处理器、存储器。在本公开的实施例中，处理器可以处理数据信号，可以包括各种计算结构，例如复杂指令集计算机(CISC)结构、结构精简指令集计算机(RISC)结构或者一种实行多种指令集组合的结构。在一些实施例中，处理器也可以是微处理器，例如X86处理器或ARM处理器，或者可以是数字处理器(DSP)等。处理器可以控制其它组件以执行期望的功能。在本公开的实施例中，存储器可以保存处理器执行的指令和/或数据。例如，存储器可以包括一个或多个计算机程序产品，所述计算机程序产品可以包括各种形式的计算机可读存 储介质，例如易失性存储器和/或非易失性存储器。所述易失性存储器例如可以包括随机存取存储器(RAM)和/或高速缓冲存储器(cache)等。所述非易失性存储器例如可以包括只读存储器(ROM)、硬盘、闪存等。在所述计算机可读存储介质上可以存储一个或多个计算机程序指令，处理器可以运行所述程序指令，以实现本公开实施例中(由处理器实现)期望的功能。在所述计算机可读存储介质中还可以存储各种应用程序和各种数据，例如所述应用程序使用和/或产生的各种数据等。
例如，显示面板10还包括数据信号线、发光控制信号线、第一扫描信号线、第二扫描信号线和复位控制信号线(图6中未示出)。数据驱动器11通过数据信号线为向像素电路100提供数据信号Data；扫描驱动器12分别通过发光控制信号线、第一扫描信号线、第二扫描信号线和复位控制信号线向各个像素电路100提供发光控制信号EM、第一扫描信号Gate、第二扫描信号Scan以及复位控制信号Reset等。
例如，显示面板10还包括电源(电压源或电流源，图中未示出)、第一电源线、第二电源线、参考电压线以及复位电压线(图6中未示出)，所述电源被配置为分别通过第一电源线、第二电源线、参考电压线以及复位电压线向像素电路100提供第一电源电压ELVDD、第二电源电压ELVSS、参考电压Vref以及复位电压Vint等。
本公开的实施例还提供一种显示设备1，如图7所示，显示设备1包括本公开任一实施例提供的显示面板10。
例如，本公开实施例提供的显示设备可以包括手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开的实施例还提供一种如图3所示的像素电路100的驱动方法。例如，如图8所示，在一帧显示时间段内，该驱动方法包括复位阶段t1、数据写入及阈值补偿阶段t2、压降补偿阶段t3和发光阶段t4。
在复位阶段t1，设置发光控制信号EM为关闭电压，设置复位控制信号Reset为开启电压，设置第一扫描信号Gate为关闭电压，设置第二扫描信号Scan为开启电压，设置数据信号Data为无效数据信号。
在数据写入及阈值补偿阶段t2，设置发光控制信号EM为关闭电压，设置复位控制信号Reset为关闭电压，设置第一扫描信号Gate为开启电压，设 置第二扫描信号Scan为关闭电压，设置数据信号Data为有效数据信号。
在压降补偿阶段t3，设置发光控制信号EM为关闭电压，设置复位控制信号Reset为关闭电压，设置第一扫描信号Gate为关闭电压，设置第二扫描信号Scan为开启电压，设置数据信号Data为无效数据信号。
在发光阶段t4，设置发光控制信号EM为开启电压，设置复位控制信号Reset为关闭电压，设置第一扫描信号Gate为关闭电压，设置第二扫描信号Scan为开启电压，设置数据信号Data为无效数据信号。
例如，本公开实施例中的开启电压是指能使相应晶体管第一极和第二级导通的电压，关闭电压是指能使相应晶体管的第一极和第二级断开的电压。当晶体管为P型晶体管时，开启电压为低电压(例如，0V)，关闭电压为高电压(例如，5V)；当晶体管为N型晶体管时，开启电压为高电压(例如，5V)，关闭电压为低电压(例如，0V)。图8至图11所示的驱动波形均以P型晶体管为例进行说明，即开启电压为低电压(例如，0V)，关闭电压为高电压(例如，5V)。无效数据信号例如为低电压信号(例如，0V)，有效数据信号例如为包括发光数据信息的信号，在图8至图11中以高电压信号为例进行说明。
例如，参见图3和图8，在复位阶段t1，发光控制信号EM为关闭电压，复位控制信号Reset为开启电压，第一扫描信号Gate为关闭电压，第二扫描信号Scan为开启电压，数据信号Data为无效数据信号。此时，第一晶体管T1和第四晶体管T4处于导通状态，第二晶体管T2、第三晶体管T3和第五晶体管T5处于关闭状态。第一晶体管T1将复位电压Vint传输到第一节点N1，第四晶体管T4将参考电压Vref传输到第二节点N2。即，复位电路接收复位控制信号Reset并根据复位控制信号Reset向第一节点N1写入复位电压Vint；参考电压写入电路接收第二扫描信号Scan并根据第二扫描信号Scan向第二节点N2写入参考电压Vref。
在数据写入及阈值补偿阶段t2，发光控制信号EM为关闭电压，复位控制信号Reset为关闭电压，第一扫描信号Gate为开启电压，第二扫描信号Scan为关闭电压，数据信号Data为有效数据信号。此时，第二晶体管T2和第三晶体管T3处于导通状态，第一晶体管T1、第四晶体管T4和第五晶体管T5处于关闭状态。此时，第三晶体管T3将有效数据信号的电压Vdata传输到第 二节点N2，第二节点N2的电压由复位阶段t1的Vref变化为Vdata，即，第一数据写入电路接收第一扫描信号Gate和数据信号Data并根据第一扫描信号Gate向第二节点N2写入数据信号Data。第二晶体管T2导通将驱动晶体管DT连接成二极管结构，第一节点N1的电压为ELVDD+Vth，其中，ELVDD为第一电源电压，Vth为驱动晶体管的阈值电压，即，阈值补偿电路接收第一扫描信号Gate并根据第一扫描信号Gate对第一节点N1的电压进行阈值电压补偿。在此阶段，存储电容C两端的电压为ELVDD+Vth-Vdata。
在压降补偿阶段t3，发光控制信号EM为关闭电压，复位控制信号Reset为关闭电压，第一扫描信号Gate为关闭电压，第二扫描信号Scan为开启电压，数据信号Data为无效数据信号。第四晶体管T4处于导通状态，第一晶体管T1、第二晶体管T2、第三晶体管T3和第五晶体管T5处于关闭状态。此时，第四晶体管T4再次将参考电压Vref传输到第二节点N2，由于存储电容C的自举作用(即存储电容两端的电压不会突变)，第一节点N1的电压变为ELVDD+Vth-Vdata+Vref。
在发光阶段t4，发光控制信号EM为开启电压，复位控制信号Reset为关闭电压，第一扫描信号Gate为关闭电压，第二扫描信号Scan为开启电压，数据信号Data为无效数据信号。第四晶体管T4和第五晶体管处于导通状态，第一晶体管T1、第二晶体管T2和第三晶体管T3处于关闭状态。第一节点N1的电压保持在ELVDD+Vth-Vdata+Vref，发光电流Ioled通过驱动晶体管DT和第五晶体管T5流入有机发光二极管OLED，有机发光二极管OLED发光。即，发光控制电路接收发光控制信号EM并根据发光控制信号EM控制有机发光二极管OLED发光。发光电流Ioled满足如下饱和电流公式：
K(Vgs-Vth)2＝K(ELVDD+Vth-Vdata+Vref-ELVDD-Vth)2＝K(Vref-Vdata)2
其中，
Figure PCTCN2017079713-appb-000001
μn为驱动晶体管的沟道迁移率，Cox为驱动晶体管单位面积的沟道电容，W和L分别为驱动晶体管的沟道宽度和沟道长度，Vgs为驱动晶体管的栅源电压(驱动晶体管的栅极电压与源极电压之差)。
由上式中可以看到流经OLED的电流与驱动晶体管DT的阈值电压无关，与ELVDD的电压也无关。因此，本像素电路非常好的补偿了驱动晶体管DT的阈值电压与ELVDD走线上的电阻压降(IR drop)。
例如，当第六晶体管T6的栅极与第一扫描信号线电连接接收第一扫描信号Gate时，在数据写入及阈值补偿阶段t2，第六晶体管T6处于导通状态，第三节点N3的电位为初始化电压Vre(例如，初始化电压Vre等于复位电压Vint)。例如，初始化电压Vre与第二电源电压ELVSS之差小于有机发光二极管OLED的起亮电压，又例如，初始化电压Vre小于等于第二电源电压ELVSS，可以防止有机发光二极管的异常发光，提升显示品质。在在发光阶段t4，第六晶体管T6处于关闭状态，当显示黑色画面时第三节点N3点的电压可以由第六晶体管T6的漏电流流出，保证了黑画面时的低亮度，提高了显示效果。
例如，当第六晶体管T6的栅极与复位控制信号线电连接接收复位控制信号Reset时，在复位阶段t1，第六晶体管T6处于导通状态，第三节点N3的电位为初始化电压Vre(例如，初始化电压Vre等于复位电压Vint)。例如，初始化电压Vre与第二电源电压ELVSS之差小于有机发光二极管OLED的起亮电压，又例如，初始化电压Vre小于等于第二电源电压ELVSS，可以防止有机发光二极管的异常发光，提升显示品质。在在发光阶段t4，第六晶体管T6处于关闭状态，当显示黑色画面时第三节点N3点的电压可以由第六晶体管T6的漏电流流出，保证了黑画面时的低亮度，提高了显示效果。
例如，根据上文所述，初始化电路接收第一扫描信号Gate或复位控制信号Reset并根据第一扫描信号Gate或复位控制信号Reset向第三节点N3写入初始化电压Vre。初始化电压Vre例如等于复位电压Vint。
例如，在本公开实施例提供的驱动方法中，发光阶段t4的时长占一帧显示时间段F的比例可被调节。这样，可以通过调节发光阶段t4的时长占一帧显示时间段F的比例控制发光亮度。
例如，通过控制显示面板中的扫描驱动器12实现调节发光阶段t4的时长占一帧显示时间段F的比例。
例如，本公开实施例提供的驱动方法，如图9所示，在一帧显示时间段F内，还包括发光延续阶段，发光延续阶段包括至少一个关闭子阶段和至少一个发光子阶段。例如，发光延续阶段包括n个关闭子阶段(t51……t5n)和n个发光子阶段(t61……t6n)。在关闭子阶段，设置发光控制信号EM为关闭电压，设置复位控制信号Reset为关闭电压，设置第一扫描信号Gate为 关闭电压，设置第二扫描信号Scan为开启电压，设置数据信号Data为无效数据信号；在发光子阶段，设置发光控制信号EM为开启电压，设置复位控制信号Reset为关闭电压，设置第一扫描信号Gate为关闭电压，设置第二扫描信号Scan为开启电压，设置数据信号Data为无效数据信号。这种设置可以在一帧显示时间段内使有机发光二极管在发光状态和不发光状态之间多次切换，即增加了有机发光二极管发光的频率，减小或避免了因视觉暂留效果导致的闪烁现象。
例如，在一帧显示时间段内包括三个关闭子阶段和三个发光子阶段，即n＝3，即可较好地改善闪烁现象。
例如，在本公开实施例提供的驱动方法中，发光阶段t4的时长和全部发光子阶段的总时长之和占一帧显示时间段F的比例可被调节。
例如，在本公开实施例提供的驱动方法中，每个关闭子阶段的时长等于复位阶段t1的时长、数据写入及阈值补偿阶段t2的时长和压降补偿阶段t3的时长之和，每个发光子阶段的时长等于发光阶段t4的时长。这种设置可以保证有机发光二极管每次发光时长相同，并且每次发光时段之间的间隔相等，便于简化时序控制，保证电路稳定。
本公开的实施例还提供一种如图5所示的像素电路100的驱动方法，在一帧显示时间段内，包括复位阶段t1、数据写入及阈值补偿阶段t2、压降补偿阶段t3和发光阶段t4。
在复位阶段t1，设置发光控制信号EM为关闭电压，设置复位控制信号Reset为开启电压，设置第一扫描信号Gate为关闭电压，设置第二扫描信号Scan为关闭电压，设置数据信号Data为有效数据信号。
在数据写入及阈值补偿阶段t2，设置发光控制信号EM为关闭电压，设置复位控制信号Reset为关闭电压，设置第一扫描信号Gate为开启电压，设置第二扫描信号Scan为关闭电压，设置数据信号Data为有效数据信号。
在压降补偿阶段t3，设置发光控制信号EM为关闭电压，设置复位控制信号Reset为关闭电压，设置第一扫描信号Gate为关闭电压，设置第二扫描信号Scan为开启电压，设置数据信号Data为无效数据信号。
在发光阶段t4，设置发光控制信号EM为开启电压，设置复位控制信号Reset为关闭电压，设置第一扫描信号Gate为关闭电压，设置第二扫描信号 Scan为开启电压，设置数据信号Data为无效数据信号。
例如，参见图5和图10，在复位阶段t1，发光控制信号EM为关闭电压，复位控制信号Reset为开启电压，第一扫描信号Gate为关闭电压，第二扫描信号Scan为关闭电压，数据信号Data为有效数据信号。此时，第一晶体管T1和第七晶体管T7处于导通状态，第二晶体管T2、第三晶体管T3、第四晶体管T4和第五晶体管T5处于关闭状态。第一晶体管T1将复位电压Vint传输到第一节点N1，第七晶体管T7将有效数据信号的电压Vdata传输到第二节点N2。即，复位电路接收复位控制信号Reset并根据复位控制信号Reset向第一节点N1写入复位电压Vint；第二数据写入电路接收复位控制信号Reset和数据信号Data并根据复位控制信号Reset向第二节点N2写入数据信号Data。
在数据写入及阈值补偿阶段t2，发光控制信号EM为关闭电压，复位控制信号Reset为关闭电压，第一扫描信号Gate为开启电压，第二扫描信号Scan为关闭电压，数据信号Data为有效数据信号。此时，第二晶体管T2和第三晶体管T3处于导通状态，第一晶体管T1、第四晶体管T4、第五晶体管T5和第七晶体管T7处于关闭状态。此时，第三晶体管T3继续将有效数据信号的电压Vdata传输到第二节点N2，即，第一数据写入电路接收第一扫描信号Gate和数据信号Data并根据第一扫描信号Gate向第二节点N2写入数据信号Data。第二晶体管T2导通将驱动晶体管DT连接成二极管结构，第一节点N1的电压为ELVDD+Vth，其中，ELVDD为第一电源电压，Vth为驱动晶体管的阈值电压，即，阈值补偿电路接收第一扫描信号Gate并根据第一扫描信号Gate向第一节点N1写入补偿电压，所述补偿电压为第一电源电压ELVDD与所述驱动晶体管的阈值电压Vth之和ELVDD+Vth。例如，在此阶段，存储电容C两端的电压差为ELVDD+Vth-Vdata。
在压降补偿阶段t3，发光控制信号EM为关闭电压，复位控制信号Reset为关闭电压，第一扫描信号Gate为关闭电压，第二扫描信号Scan为开启电压，数据信号Data为无效数据信号。第四晶体管T4处于导通状态，第一晶体管T1、第二晶体管T2、第三晶体管T3、第五晶体管T5和第七晶体管T7处于关闭状态。此时，第四晶体管T4再次将参考电压Vref传输到第二节点N2，由于存储电容C的自举作用(即存储电容两端的电压不会突变)，第一 节点N1的电压变为ELVDD+Vth-Vdata+Vref。
在发光阶段t4，发光控制信号EM为开启电压，复位控制信号Reset为关闭电压，第一扫描信号Gate为关闭电压，第二扫描信号Scan为开启电压，数据信号Data为无效数据信号。第四晶体管T4、第五晶体管和第七晶体管T7处于导通状态，第一晶体管T1、第二晶体管T2和第三晶体管T3处于关闭状态。第一节点N1的电压保持在ELVDD+Vth-Vdata+Vref，发光电流Ioled通过驱动晶体管DT和第五晶体管T5流入有机发光二极管OLED，有机发光二极管OLED发光。即，发光控制电路接收发光控制信号EM并根据发光控制信号EM控制有机发光二极管OLED发光。发光电流Ioled满足如下饱和电流公式：
K(Vgs-Vth)2＝K(ELVDD+Vth-Vdata+Vref-ELVDD-Vth)2＝K(Vref-Vdata)2
其中，
Figure PCTCN2017079713-appb-000002
μn为驱动晶体管的沟道迁移率，Cox为驱动晶体管单位面积的沟道电容，W和L分别为驱动晶体管的沟道宽度和沟道长度，Vgs为驱动晶体管的栅源电压(驱动晶体管的栅极电压与源极电压之差)。
由上式中可以看到流经OLED的电流与驱动晶体管DT的阈值电压无关，与ELVDD的电压也无关。因此，本像素电路非常好的补偿了驱动晶体管DT的阈值电压与ELVDD走线上的电阻压降(IR drop)。
例如，相比于图3所示驱动电路的驱动方法，图5所示驱动电路的驱动方法在复位阶段t1即开始向第二节点N2写入数据信号，增加了数据信号写入的时间，同时防止复位阶段t1向数据写入及阈值补偿阶段t2转换时，第二节点N2电压变化过大对电路造成的冲击，有利于电路的稳定。
例如，当第六晶体管T6的栅极与第一扫描信号线电连接接收第一扫描信号Gate时，在数据写入及阈值补偿阶段t2，第六晶体管T6处于导通状态，第三节点N3的电位为初始化电压Vre(例如，初始化电压Vre等于复位电压Vint)。例如，初始化电压Vre与第二电源电压ELVSS之差小于有机发光二极管OLED的起亮电压，又例如，初始化电压Vre小于等于第二电源电压ELVSS，可以防止有机发光二极管的异常发光，提升显示品质。在在发光阶段t4，第六晶体管T6处于关闭状态，当显示黑色画面时第三节点N3点的电压可以由第六晶体管T6的漏电流流出，保证了黑画面时的低亮度，提高了 显示效果。
例如，当第六晶体管T6的栅极与复位控制信号线电连接接收复位控制信号Reset时，在复位阶段t1，第六晶体管T6处于导通状态，第三节点N3的电位为初始化电压Vre(例如，初始化电压Vre等于复位电压Vint)。例如，初始化电压Vre与第二电源电压ELVSS之差小于有机发光二极管OLED的起亮电压，又例如，初始化电压Vre小于等于第二电源电压ELVSS，可以防止有机发光二极管的异常发光，提升显示品质。在在发光阶段t4，第六晶体管T6处于关闭状态，当显示黑色画面时第三节点N3点的电压可以由第六晶体管T6的漏电流流出，保证了黑画面时的低亮度，提高了显示效果。
例如，根据上文所述，初始化电路接收第一扫描信号Gate或复位控制信号Reset并根据第一扫描信号Gate或复位控制信号Reset向第三节点N3写入初始化电压Vre。初始化电压Vre例如等于复位电压Vint。
例如，在本公开实施例提供的驱动方法中，发光阶段t4的时长占一帧显示时间段F的比例可被调节。这样，可以通过调节发光阶段t4的时长占一帧显示时间段F的比例控制发光亮度。
例如，通过控制显示面板中的扫描驱动器12实现调节发光阶段t4的时长占一帧显示时间段F的比例。
例如，本公开实施例提供的驱动方法，如图11所示，在一帧显示时间段F内，还包括发光延续阶段，发光延续阶段包括至少一个关闭子阶段和至少一个发光子阶段。例如，发光延续阶段包括n个关闭子阶段(t51……t5n)和n个发光子阶段(t61……t6n)。在关闭子阶段，设置发光控制信号EM为关闭电压，设置复位控制信号Reset为关闭电压，设置第一扫描信号Gate为关闭电压，设置第二扫描信号Scan为开启电压，设置数据信号Data为无效数据信号；在发光子阶段，设置发光控制信号EM为开启电压，设置复位控制信号Reset为关闭电压，设置第一扫描信号Gate为关闭电压，设置第二扫描信号Scan为开启电压，设置数据信号Data为无效数据信号。这种设置可以在一帧显示时间段内使有机发光二极管在发光状态和不发光状态之间多次切换，即增加了有机发光二极管发光的频率，减小或避免了因视觉暂留效果导致的闪烁现象。
例如，在一帧显示时间段内包括三个关闭子阶段和三个发光子阶段，即 n＝3，即可较好地改善闪烁现象。
例如，在本公开实施例提供的驱动方法中，发光阶段t4的时长和全部发光子阶段的总时长之和占一帧显示时间段F的比例可被调节。
例如，在本公开实施例提供的驱动方法中，每个关闭子阶段的时长等于复位阶段t1的时长、数据写入及阈值补偿阶段t2的时长和压降补偿阶段t3的时长之和，每个发光子阶段的时长等于发光阶段t4的时长。这种设置可以保证有机发光二极管每次发光时长相同，并且每次发光时段之间的间隔相等，便于简化时序控制，保证电路稳定。
本公开的实施例提供一种像素电路、显示面板、显示设备及驱动方法，可对显示面板进行电阻压降和阈值电压补偿，提高了驱动电流的均匀性，进而提高了显示面板显示的均匀性，同时减小漏电流以保证黑态时的高对比度，以及通过调整发光时间占一帧显示时间段的比例使得在低灰阶条件下保证精确显示。
虽然上文中已经用一般性说明及具体实施方式，对本公开作了详尽的描述，但在本公开实施例基础上，可以对之作一些修改或改进，这对本领域技术人员而言是显而易见的。因此，在不偏离本公开精神的基础上所做的这些修改或改进，均属于本公开要求保护的范围。
本专利申请要求于2016年8月22日递交的中国专利申请第201610703367.9号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (22)

  1. 一种像素电路，包括：
    存储电容，包括与第一节点连接的第一端和与第二节点连接的第二端；
    有机发光二极管，包括与第三节点连接的第一极；
    驱动晶体管，包括与所述第一节点连接的栅极，其中，所述驱动晶体管被配置为根据所述第一节点的电压控制所述有机发光二极管发光；
    发光控制电路，被配置为接收发光控制信号并根据所述发光控制信号控制所述有机发光二极管发光或关断；
    复位电路，被配置为接收复位控制信号并根据所述复位控制信号向所述第一节点写入复位电压；
    阈值补偿电路，被配置为接收第一扫描信号并根据所述第一扫描信号向所述第一节点写入补偿电压，其中，所述补偿电压为第一电源电压与所述驱动晶体管的阈值电压之和；
    第一数据写入电路，被配置为接收第一扫描信号和数据信号并根据所述第一扫描信号向所述第二节点写入所述数据信号；
    参考电压写入电路，被配置为接收第二扫描信号并根据所述第二扫描信号向所述第二节点写入参考电压；以及
    初始化电路，被配置为接收所述第一扫描信号或所述复位控制信号并根据所述第一扫描信号或所述复位控制信号向第三节点写入初始化电压。
  2. 根据权利要求1所述的像素电路，其中，所述初始化电压等于所述复位电压。
  3. 根据权利要求1所述的像素电路，其中，所述有机发光二极管还包括第二极，所述有机发光二极管的第二极与第二电源线电连接以接收第二电源电压，所述有机发光二极管的第一极为阳极，所述有机发光二极管的第二极为阴极，所述初始化电压与所述第二电源电压之差小于所述有机发光二极管的起亮电压。
  4. 根据权利要求3所述的像素电路，其中，所述初始化电压小于等于所述第二电源电压。
  5. 根据权利要求1-4任一项所述的像素电路，其中，所述复位电路包括 第一晶体管，所述阈值补偿电路包括第二晶体管，所述第一数据写入电路包括第三晶体管，所述参考电压写入电路包括第四晶体管，所述发光控制电路包括第五晶体管，所述初始化电路包括第六晶体管。
  6. 根据权利要求5所述的像素电路，其中，
    所述驱动晶体管的栅极与所述第一节点电连接，所述驱动晶体管的第一极与第一电源线电连接以接收第一电源电压，所述驱动晶体管的第二极与第四节点电连接；
    所述有机发光二极管的第一极与所述第三节点电连接，所述有机发光二极管的第二极与第二电源线电连接以接收第二电源电压；
    所述存储电容的第一端与所述第一节点电连接，所述存储电容的第二端与所述第二节点电连接；
    所述第一晶体管的栅极与复位控制信号线电连接以接收所述复位控制信号，所述第一晶体管的第一极与复位电压线电连接以接收所述复位电压，所述第一晶体管的第二极与所述第一节点电连接；
    所述第二晶体管的栅极与第一扫描信号线电连接以接收第一扫描信号，所述第二晶体管的第一极与所述第一节点电连接，所述第二晶体管的第二极与所述第四节点电连接；
    所述第三晶体管的栅极与所述第一扫描信号线电连接以接收所述第一扫描信号，所述第三晶体管的第一极与数据信号线电连接以接收所述数据信号，所述第三晶体管的第二极与所述第二节点电连接；
    所述第四晶体管的栅极与第二扫描信号线电连接以接收所述第二扫描信号，所述第四晶体管的第一极与参考电压线电连接以接收所述参考电压，所述第四晶体管的第二极与所述第二节点电连接；
    所述第五晶体管的栅极与发光控制信号线电连接以接收所述发光控制信号，所述第五晶体管的第一极与所述第三节点电连接，所述第五晶体管的第二极与所述第四节点电连接；
    所述第六晶体管的栅极与第一扫描信号线或复位控制信号线电连接以接收所述第一扫描信号或所述复位控制信号，所述第六晶体管的第一极与所述复位电压线电连接以接收所述复位电压，所述第六晶体管的第二极与所述第三节点电连接。
  7. 根据权利要求5所述的像素电路，其中，所述驱动晶体管、所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管以及所述第六晶体管均为P型晶体管。
  8. 根据权利要求5所述的像素电路，其中，所述驱动晶体管、所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管以及所述第六晶体管均为薄膜晶体管。
  9. 根据权利要求1-4任一项所述的像素电路，还包括第二数据写入电路，被配置为接收所述复位控制信号和所述数据信号并根据所述复位控制信号向所述第二节点写入所述数据信号。
  10. 根据权利要求9所述的像素电路，其中，所述复位电路包括第一晶体管，所述阈值补偿电路包括第二晶体管，所述第一数据写入电路包括第三晶体管，所述参考电压写入电路包括第四晶体管，所述发光控制电路包括第五晶体管，所述初始化电路包括第六晶体管，所述第二数据写入电路包括第七晶体管。
  11. 根据权利要求10所述的像素电路，其中，
    所述驱动晶体管的栅极与所述第一节点电连接，所述驱动晶体管的第一极与第一电源线电连接以接收第一电源电压，所述驱动晶体管的第二极与第四节点电连接；
    所述有机发光二极管的第一极与所述第三节点电连接，所述有机发光二极管的第二极与第二电源线电连接以接收第二电源电压；
    所述存储电容的第一端与所述第一节点电连接，所述存储电容的第二端与所述第二节点电连接；
    所述第一晶体管的栅极与复位控制信号线电连接以接收所述复位控制信号，所述第一晶体管的第一极与复位电压线电连接以接收所述复位电压，所述第一晶体管的第二极与所述第一节点电连接；
    所述第二晶体管的栅极与第一扫描信号线电连接以接收第一扫描信号，所述第二晶体管的第一极与所述第一节点电连接，所述第二晶体管的第二极与所述第三节点电连接；
    所述第三晶体管的栅极与所述第一扫描信号线电连接以接收所述第一扫描信号，所述第三晶体管的第一极与数据信号线电连接以接收所述数据信号， 所述第三晶体管的第二极与所述第二节点电连接；
    所述第四晶体管的栅极与第二扫描信号线电连接以接收所述第二扫描信号，所述第四晶体管的第一极与参考电压线电连接以接收所述参考电压，所述第四晶体管的第二极与所述第二节点电连接；
    所述第五晶体管的栅极与发光控制信号线电连接以接收所述发光控制信号，所述第五晶体管的第一极与所述第三节点电连接，所述第五晶体管的第二极与所述第四节点电连接；
    所述第六晶体管的栅极与第一扫描信号线或复位控制信号线电连接以接收所述第一扫描信号或所述复位控制信号，所述第六晶体管的第一极与所述复位电压线电连接以接收所述复位电压，所述第六晶体管的第二极与所述第三节点电连接；
    所述第七晶体管的栅极与复位控制信号线电连接以接收所述复位控制信号，所述第七晶体管的第一极与数据信号线电连接以接收所述数据信号，所述第七晶体管的第二极与所述第二节点电连接。
  12. 根据权利要求10所述的像素电路，其中，所述驱动晶体管、所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管以及所述第七晶体管均为P型晶体管。
  13. 根据权利要求10所述的像素电路，其中，所述驱动晶体管、所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管以及所述第七晶体管均为薄膜晶体管。
  14. 一种显示面板，包括如权利要求1-13任一项所述的像素电路。
  15. 根据权利要求14所述的显示面板，还包括：
    数据驱动器，被配置为向所述像素电路提供所述数据信号；
    扫描驱动器，被配置为向所述像素电路提供所述发光控制信号、所述第一扫描信号、所述第二扫描信号以及所述复位控制信号。
  16. 一种显示设备，包括如权利要求14或15所述的显示面板。
  17. 一种如权利要求1-8任一项所述像素电路的驱动方法，在一帧显示时间段内，包括复位阶段、数据写入及阈值补偿阶段、压降补偿阶段和发光阶段，其中，
    在所述复位阶段，设置所述发光控制信号为关闭电压，设置所述复位控 制信号为开启电压，设置所述第一扫描信号为关闭电压，设置所述第二扫描信号为开启电压，设置所述数据信号为无效数据信号；
    在所述数据写入及阈值补偿阶段，设置所述发光控制信号为关闭电压，设置所述复位控制信号为关闭电压，设置所述第一扫描信号为开启电压，设置所述第二扫描信号为关闭电压，设置所述数据信号为有效数据信号；
    在所述压降补偿阶段，设置所述发光控制信号为关闭电压，设置所述复位控制信号为关闭电压，设置所述第一扫描信号为关闭电压，设置所述第二扫描信号为开启电压，设置所述数据信号为无效数据信号；
    在所述发光阶段，设置所述发光控制信号为开启电压，设置所述复位控制信号为关闭电压，设置所述第一扫描信号为关闭电压，设置所述第二扫描信号为开启电压，设置所述数据信号为无效数据信号。
  18. 一种如权利要求9-13任一项所述像素电路的驱动方法，在一帧显示时间段内，包括复位阶段、数据写入及阈值补偿阶段、压降补偿阶段和发光阶段，其中，
    在所述复位阶段，设置所述发光控制信号为关闭电压，设置所述复位控制信号为开启电压，设置所述第一扫描信号为关闭电压，设置所述第二扫描信号为关闭电压，设置所述数据信号为有效数据信号；
    在所述数据写入及阈值补偿阶段，设置所述发光控制信号为关闭电压，设置所述复位控制信号为关闭电压，设置所述第一扫描信号为开启电压，设置所述第二扫描信号为关闭电压，设置所述数据信号为有效数据信号；
    在所述压降补偿阶段，设置所述发光控制信号为关闭电压，设置所述复位控制信号为关闭电压，设置所述第一扫描信号为关闭电压，设置所述第二扫描信号为开启电压，设置所述数据信号为无效数据信号；
    在所述发光阶段，设置所述发光控制信号为开启电压，设置所述复位控制信号为关闭电压，设置所述第一扫描信号为关闭电压，设置所述第二扫描信号为开启电压，设置所述数据信号为无效数据信号。
  19. 根据权利要求17或18所述的驱动方法，其中，所述发光阶段的时长占一帧显示时间段的比例可被调节。
  20. 根据权利要求17或18所述的驱动方法，在一帧显示时间段内，还包括发光延续阶段，其中，
    所述发光延续阶段包括至少一个关闭子阶段和至少一个发光子阶段，
    在所述关闭子阶段，设置所述发光控制信号为关闭电压，设置所述复位控制信号为关闭电压，设置所述第一扫描信号为关闭电压，设置所述第二扫描信号为开启电压，设置所述数据信号为无效数据信号；
    在所述发光子阶段，设置所述发光控制信号为开启电压，设置所述复位控制信号为关闭电压，设置所述第一扫描信号为关闭电压，设置所述第二扫描信号为开启电压，设置所述数据信号为无效数据信号。
  21. 根据权利要求20所述的驱动方法，其中，所述发光阶段的时长和全部所述发光子阶段的总时长之和占一帧显示时间段的比例可被调节。
  22. 根据权利要求20所述的驱动方法，其中，每个所述关闭子阶段的时长等于所述复位阶段的时长、所述数据写入及阈值补偿阶段的时长和所述压降补偿阶段的时长之和，每个所述发光子阶段的时长等于所述发光阶段的时长。
PCT/CN2017/079713 2016-08-22 2017-04-07 像素电路、显示面板、显示设备及驱动方法 WO2018036169A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US15/569,243 US10692434B2 (en) 2016-08-22 2017-04-07 Pixel circuit, display panel, display device and driving method
US17/649,809 US11574595B2 (en) 2016-08-22 2022-02-03 Pixel circuit, display panel, display device, and driving method
US18/150,873 US11881176B2 (en) 2016-08-22 2023-01-06 Pixel circuit, display panel, display device, and driving method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610703367.9 2016-08-22
CN201610703367.9A CN106097964B (zh) 2016-08-22 2016-08-22 像素电路、显示面板、显示设备及驱动方法

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US15/569,243 A-371-Of-International US10692434B2 (en) 2016-08-22 2017-04-07 Pixel circuit, display panel, display device and driving method
US16/882,984 Continuation-In-Part US10950179B2 (en) 2016-08-22 2020-05-26 Pixel circuit, display panel, display device, and driving method

Publications (1)

Publication Number Publication Date
WO2018036169A1 true WO2018036169A1 (zh) 2018-03-01

Family

ID=57224809

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/079713 WO2018036169A1 (zh) 2016-08-22 2017-04-07 像素电路、显示面板、显示设备及驱动方法

Country Status (3)

Country Link
US (5) US10692434B2 (zh)
CN (1) CN106097964B (zh)
WO (1) WO2018036169A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114120886A (zh) * 2021-08-25 2022-03-01 友达光电股份有限公司 像素电路
CN114792511A (zh) * 2021-01-26 2022-07-26 京东方科技集团股份有限公司 像素驱动电路、驱动控制方法和显示面板

Families Citing this family (93)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015225150A (ja) * 2014-05-27 2015-12-14 ソニー株式会社 表示装置及び電子機器
CN105654906B (zh) * 2016-01-26 2018-08-03 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板以及显示装置
CN106097964B (zh) 2016-08-22 2018-09-18 京东方科技集团股份有限公司 像素电路、显示面板、显示设备及驱动方法
CN106782329B (zh) * 2016-12-02 2019-09-10 上海天马微电子有限公司 一种有机发光显示面板及其驱动方法
CN106782304B (zh) 2016-12-29 2023-11-17 上海天马微电子有限公司 一种像素驱动电路、像素阵列、驱动方法及有机发光显示面板
CN108335672A (zh) * 2017-01-19 2018-07-27 昆山国显光电有限公司 一种像素驱动电路及其驱动方法、阵列基板和显示装置
CN108470544B (zh) * 2017-02-23 2020-09-22 昆山国显光电有限公司 一种像素驱动电路及其驱动方法、阵列基板和显示装置
JP7198206B2 (ja) 2017-02-22 2022-12-28 昆山国顕光電有限公司 画素駆動回路、その駆動方法及びアレイ基板並びに表示装置
CN107038997A (zh) * 2017-05-26 2017-08-11 京东方科技集团股份有限公司 像素电路、像素驱动方法和显示装置
CN107204173B (zh) * 2017-06-08 2019-06-28 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示面板
CN109147669B (zh) * 2017-06-15 2020-04-10 京东方科技集团股份有限公司 一种像素电路、其驱动方法及显示面板
CN107170407A (zh) * 2017-07-17 2017-09-15 京东方科技集团股份有限公司 像素单元电路、像素电路、驱动方法和显示装置
CN107342044B (zh) * 2017-08-15 2020-03-03 上海天马有机发光显示技术有限公司 像素电路、显示面板和像素电路的驱动方法
CN107274825B (zh) * 2017-08-18 2020-11-24 上海天马微电子有限公司 显示面板、显示装置、像素驱动电路及其控制方法
CN107610640A (zh) * 2017-09-28 2018-01-19 京东方科技集团股份有限公司 一种阵列基板及驱动方法、显示面板和显示设备
KR102623352B1 (ko) * 2017-09-28 2024-01-09 엘지디스플레이 주식회사 유기발광표시장치 및 그의 구동방법
KR102527793B1 (ko) * 2017-10-16 2023-05-04 삼성디스플레이 주식회사 표시 장치 및 그 구동 방법
CN109727571A (zh) * 2017-10-31 2019-05-07 昆山国显光电有限公司 一种像素电路和显示装置
CN207352944U (zh) 2017-10-31 2018-05-11 昆山国显光电有限公司 一种像素电路和显示装置
KR102523646B1 (ko) 2017-11-01 2023-04-21 삼성디스플레이 주식회사 표시 장치 및 그 구동 방법
KR102477493B1 (ko) * 2017-12-07 2022-12-14 삼성디스플레이 주식회사 화소 및 이를 포함하는 표시 장치
CN107945740B (zh) * 2018-01-05 2020-08-18 信利（惠州）智能显示有限公司 像素电路的驱动方法
CN108230974B (zh) * 2018-01-26 2021-02-02 京东方科技集团股份有限公司 一种发光器件缺陷检测电路及方法、显示驱动装置、显示装置及其检测方法
TWI652665B (zh) * 2018-02-14 2019-03-01 友達光電股份有限公司 像素驅動電路
CN108154844B (zh) * 2018-03-09 2019-07-30 京东方科技集团股份有限公司 一种像素电路、其驱动方法及显示面板
TWI662530B (zh) * 2018-06-08 2019-06-11 友達光電股份有限公司 發光二極體裝置及其控制方法
CN108777131B (zh) * 2018-06-22 2020-04-03 武汉华星光电半导体显示技术有限公司 Amoled像素驱动电路及驱动方法
CN110728946A (zh) * 2018-06-29 2020-01-24 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板
CN110021263B (zh) * 2018-07-05 2020-12-22 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板
CN109036287B (zh) * 2018-07-19 2020-05-05 武汉华星光电半导体显示技术有限公司 一种像素驱动电路、驱动方法及显示面板
CN110021264B (zh) * 2018-09-07 2022-08-19 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板
US11271181B1 (en) 2018-09-21 2022-03-08 Apple Inc. Electronic display visual artifact mitigation
KR102583403B1 (ko) * 2018-10-11 2023-09-26 엘지디스플레이 주식회사 디스플레이 장치 및 디스플레이 패널
CN109272932A (zh) * 2018-11-28 2019-01-25 昆山国显光电有限公司 像素电路及其驱动方法、显示面板、显示装置
JP7154122B2 (ja) * 2018-12-20 2022-10-17 エルジー ディスプレイ カンパニー リミテッド 発光表示装置
CN109686314B (zh) * 2019-03-01 2021-01-29 京东方科技集团股份有限公司 像素电路、显示基板和显示装置
TWI681400B (zh) 2019-03-11 2020-01-01 友達光電股份有限公司 移位暫存電路及閘極驅動器
CN110111753B (zh) * 2019-04-10 2020-10-27 深圳市华星光电半导体显示技术有限公司 显示面板的驱动方法及装置
CN111951716B (zh) * 2019-04-30 2024-03-22 上海和辉光电股份有限公司 像素电路、驱动方法及显示器
US11727868B2 (en) * 2019-06-03 2023-08-15 Boe Technology Group Co., Ltd. Pixel circuit for threshold compensation, driving method thereof and display device for providing signals
KR102612043B1 (ko) * 2019-06-05 2023-12-07 엘지디스플레이 주식회사 발광 표시 장치 및 그 구동 방법
TWI722479B (zh) * 2019-07-05 2021-03-21 友達光電股份有限公司 畫素電路與畫素驅動方法
WO2021007866A1 (zh) * 2019-07-18 2021-01-21 京东方科技集团股份有限公司 驱动电路、其驱动方法及显示装置
CN112309332B (zh) * 2019-07-31 2022-01-18 京东方科技集团股份有限公司 像素电路及其驱动方法、显示基板和显示面板
CN110491338B (zh) * 2019-08-28 2021-02-02 京东方科技集团股份有限公司 像素电路及其驱动方法、发光控制电路及方法、显示装置
KR20210027652A (ko) * 2019-08-30 2021-03-11 삼성디스플레이 주식회사 표시장치 구동 방법
CN110532987B (zh) * 2019-09-04 2022-04-22 武汉天马微电子有限公司 指纹识别电路、指纹识别方法和显示面板
CN110619851A (zh) * 2019-09-24 2019-12-27 京东方科技集团股份有限公司 像素电路、驱动方法及显示装置
CN110660359B (zh) * 2019-09-29 2022-03-29 合肥京东方卓印科技有限公司 像素驱动电路及其驱动方法、显示面板和显示装置
CN110675822A (zh) * 2019-09-30 2020-01-10 昆山国显光电有限公司 像素驱动电路及像素驱动电路的控制方法
CN112750392B (zh) * 2019-10-30 2022-04-15 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板、显示装置
CN110751928B (zh) * 2019-11-11 2022-04-08 Oppo广东移动通信有限公司 一种像素电路及其工作方法、显示装置
CN111081189B (zh) * 2019-12-20 2021-04-13 合肥视涯技术有限公司 像素驱动电路和显示装置
KR102667950B1 (ko) * 2019-12-24 2024-05-21 엘지디스플레이 주식회사 유기 전계발광 표시장치 및 그의 구동방법
CN111243479B (zh) 2020-01-16 2024-05-14 京东方科技集团股份有限公司 显示面板、像素电路及其驱动方法
WO2021196015A1 (zh) * 2020-03-31 2021-10-07 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置及其驱动方法
CN111354307B (zh) * 2020-04-09 2022-02-15 武汉天马微电子有限公司 一种像素驱动电路及驱动方法、有机发光显示面板
US11087684B1 (en) * 2020-04-16 2021-08-10 Novatek Microelectronics Corp. Pixel driver and pixel driving method
CN111477669B (zh) 2020-05-09 2023-04-18 京东方科技集团股份有限公司 一种显示面板及其制作方法、显示装置
CN111477179B (zh) * 2020-05-20 2021-10-22 京东方科技集团股份有限公司 一种像素驱动电路及其驱动方法、显示装置
CN111508426B (zh) * 2020-05-29 2022-04-15 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板
KR20210148538A (ko) * 2020-05-29 2021-12-08 삼성디스플레이 주식회사 표시 장치
TWI754478B (zh) * 2020-06-10 2022-02-01 友達光電股份有限公司 畫素電路
CN111564138B (zh) * 2020-06-10 2022-04-22 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板和显示装置
CN111599309B (zh) * 2020-06-30 2022-03-11 武汉天马微电子有限公司 一种像素驱动电路、有机发光显示面板及显示装置
US11804177B2 (en) 2020-07-24 2023-10-31 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Pixel driving circuit, driving method thereof, and display panel
CN111799318B (zh) * 2020-07-28 2022-08-19 武汉天马微电子有限公司 一种显示面板及显示装置
KR20220017549A (ko) * 2020-08-04 2022-02-14 삼성디스플레이 주식회사 유기 발광 표시 장치
KR20220025996A (ko) * 2020-08-24 2022-03-04 삼성디스플레이 주식회사 화소, 표시 장치 및 그 구동 방법
CN114616616B (zh) * 2020-08-31 2023-12-22 京东方科技集团股份有限公司 一种显示基板及其制作方法、显示装置
CN112037716B (zh) 2020-09-21 2022-01-21 京东方科技集团股份有限公司 像素电路、显示面板和显示设备
EP4214698A1 (en) * 2020-11-03 2023-07-26 Google LLC Display device with reduced rounded corner bezel size
CN114766048B (zh) * 2020-11-03 2023-08-11 京东方科技集团股份有限公司 像素电路及驱动方法、显示面板、显示装置
CN112365836B (zh) * 2020-11-09 2021-09-24 深圳市华星光电半导体显示技术有限公司 驱动tft的灰阶补偿方法、装置及其显示面板、显示装置
CN112397565B (zh) * 2020-12-09 2022-08-05 武汉华星光电半导体显示技术有限公司 显示面板及显示装置
CN114694573A (zh) * 2020-12-28 2022-07-01 上海和辉光电股份有限公司 一种像素驱动电路及显示装置
CN112599100A (zh) * 2021-01-07 2021-04-02 深圳市华星光电半导体显示技术有限公司 像素驱动电路及显示面板
CN112782895A (zh) * 2021-01-27 2021-05-11 武汉华星光电技术有限公司 显示面板及液晶显示装置
CN114967252B (zh) * 2021-02-23 2023-10-03 京东方科技集团股份有限公司 一种显示面板及其制作方法、控制方法、显示装置
TWI773313B (zh) * 2021-05-11 2022-08-01 友達光電股份有限公司 畫素電路及其驅動方法
CN113421525B (zh) * 2021-06-21 2022-12-09 福州京东方光电科技有限公司 像素驱动电路、显示面板、显示设备和驱动控制方法
CN116193913A (zh) * 2021-06-30 2023-05-30 武汉天马微电子有限公司 一种显示面板和显示装置
CN114424280B (zh) * 2021-07-30 2022-09-23 京东方科技集团股份有限公司 像素电路、驱动方法和显示装置
CN113838420B (zh) * 2021-08-05 2022-03-18 京东方科技集团股份有限公司 像素电路、显示装置和驱动方法
CN113724654B (zh) * 2021-08-31 2023-12-12 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示装置
CN113808542B (zh) * 2021-09-22 2023-01-10 北京京东方技术开发有限公司 像素电路、驱动方法和显示装置
EP4390619A1 (en) * 2021-10-01 2024-06-26 Samsung Electronics Co., Ltd. Electronic device and operation method thereof
CN114242000B (zh) * 2021-12-17 2023-03-31 武汉天马微电子有限公司 显示面板及其驱动方法、显示装置
CN114898694B (zh) * 2022-05-19 2023-04-25 惠科股份有限公司 像素驱动电路及显示设备
CN114937684A (zh) 2022-06-07 2022-08-23 上海天马微电子有限公司 一种显示面板及显示装置
CN115331634A (zh) * 2022-08-30 2022-11-11 京东方科技集团股份有限公司 像素电路、像素驱动方法、显示基板和显示装置
CN115376451A (zh) * 2022-09-21 2022-11-22 武汉天马微电子有限公司 像素电路及其驱动方法、阵列基板、显示面板和显示装置
CN117198212B (zh) * 2023-11-07 2024-04-12 惠科股份有限公司 显示面板

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101540139A (zh) * 2008-03-18 2009-09-23 索尼株式会社 半导体设备、显示面板和电子器件
US20140139503A1 (en) * 2012-11-20 2014-05-22 Samsung Display Co., Ltd. Organic light emitting diode (oled) pixel, display device including the same and driving method thereof
CN203882587U (zh) * 2014-06-13 2014-10-15 京东方科技集团股份有限公司 像素驱动电路、阵列基板及显示装置
CN104835454A (zh) * 2015-06-01 2015-08-12 京东方科技集团股份有限公司 一种有机电致发光触控面板、其驱动方法显示装置
CN105243985A (zh) * 2014-07-10 2016-01-13 乐金显示有限公司 有机发光显示器及其驱动方法
CN106097964A (zh) * 2016-08-22 2016-11-09 京东方科技集团股份有限公司 像素电路、显示面板、显示设备及驱动方法
CN205920745U (zh) * 2016-08-22 2017-02-01 京东方科技集团股份有限公司 像素电路、显示面板及显示设备

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100637433B1 (ko) * 2004-05-24 2006-10-20 삼성에스디아이 주식회사 발광 표시 장치
GB0400213D0 (en) * 2004-01-07 2004-02-11 Koninkl Philips Electronics Nv Electroluminescent display devices
KR101152119B1 (ko) 2005-02-07 2012-06-15 삼성전자주식회사 표시 장치 및 그 구동 방법
KR100732842B1 (ko) * 2005-11-09 2007-06-27 삼성에스디아이 주식회사 발광 표시장치
JP5160748B2 (ja) 2005-11-09 2013-03-13 三星ディスプレイ株式會社 発光表示装置
KR100824854B1 (ko) * 2006-12-21 2008-04-23 삼성에스디아이 주식회사 유기 전계 발광 표시 장치
KR101407302B1 (ko) 2007-12-27 2014-06-13 엘지디스플레이 주식회사 발광 표시 장치 및 그 구동 방법
KR101509113B1 (ko) * 2008-12-05 2015-04-08 삼성디스플레이 주식회사 표시 장치 및 그 구동 방법
KR101056297B1 (ko) * 2009-11-03 2011-08-11 삼성모바일디스플레이주식회사 화소 및 이를 구비한 유기전계발광 표시장치
KR101125571B1 (ko) * 2010-02-05 2012-03-22 삼성모바일디스플레이주식회사 화소, 이를 이용한 표시 장치 및 그 구동 방법
KR101082234B1 (ko) * 2010-05-13 2011-11-09 삼성모바일디스플레이주식회사 유기전계발광 표시장치 및 그의 구동방법
KR20150006145A (ko) * 2013-07-08 2015-01-16 삼성디스플레이 주식회사 화소 및 이를 이용한 유기전계발광 표시장치
CN103700342B (zh) 2013-12-12 2017-03-01 京东方科技集团股份有限公司 Oled像素电路及驱动方法、显示装置
CN203882588U (zh) 2014-06-13 2014-10-15 京东方科技集团股份有限公司 像素驱动电路、阵列基板及显示装置
CN204029330U (zh) 2014-07-22 2014-12-17 京东方科技集团股份有限公司 像素驱动电路、阵列基板及显示装置
KR102238636B1 (ko) * 2014-08-05 2021-04-12 엘지디스플레이 주식회사 표시장치
KR102334265B1 (ko) * 2014-12-02 2021-12-01 삼성디스플레이 주식회사 유기 발광 표시 장치 및 이의 구동 방법
KR20200133118A (ko) * 2019-05-17 2020-11-26 삼성디스플레이 주식회사 표시장치
KR20210013485A (ko) * 2019-07-26 2021-02-04 삼성디스플레이 주식회사 표시 장치 및 그 구동 방법

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101540139A (zh) * 2008-03-18 2009-09-23 索尼株式会社 半导体设备、显示面板和电子器件
US20140139503A1 (en) * 2012-11-20 2014-05-22 Samsung Display Co., Ltd. Organic light emitting diode (oled) pixel, display device including the same and driving method thereof
CN203882587U (zh) * 2014-06-13 2014-10-15 京东方科技集团股份有限公司 像素驱动电路、阵列基板及显示装置
CN105243985A (zh) * 2014-07-10 2016-01-13 乐金显示有限公司 有机发光显示器及其驱动方法
CN104835454A (zh) * 2015-06-01 2015-08-12 京东方科技集团股份有限公司 一种有机电致发光触控面板、其驱动方法显示装置
CN106097964A (zh) * 2016-08-22 2016-11-09 京东方科技集团股份有限公司 像素电路、显示面板、显示设备及驱动方法
CN205920745U (zh) * 2016-08-22 2017-02-01 京东方科技集团股份有限公司 像素电路、显示面板及显示设备

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114792511A (zh) * 2021-01-26 2022-07-26 京东方科技集团股份有限公司 像素驱动电路、驱动控制方法和显示面板
CN114792511B (zh) * 2021-01-26 2023-10-24 京东方科技集团股份有限公司 像素驱动电路、驱动控制方法和显示面板
CN114120886A (zh) * 2021-08-25 2022-03-01 友达光电股份有限公司 像素电路
CN114120886B (zh) * 2021-08-25 2024-02-27 友达光电股份有限公司 像素电路

Also Published As

Publication number Publication date
US10692434B2 (en) 2020-06-23
US11574595B2 (en) 2023-02-07
US20230215372A1 (en) 2023-07-06
CN106097964A (zh) 2016-11-09
US20220157248A1 (en) 2022-05-19
US11270646B2 (en) 2022-03-08
US20180315374A1 (en) 2018-11-01
US20210174746A1 (en) 2021-06-10
CN106097964B (zh) 2018-09-18
US20220375409A9 (en) 2022-11-24
US11881176B2 (en) 2024-01-23
US10950179B2 (en) 2021-03-16
US20200286432A1 (en) 2020-09-10

Similar Documents

Publication Publication Date Title
WO2018036169A1 (zh) 像素电路、显示面板、显示设备及驱动方法
KR102176454B1 (ko) Amoled 픽셀 구동 회로 및 구동 방법
WO2017215290A1 (zh) 像素电路、显示面板及驱动方法
WO2018166172A1 (zh) 像素驱动电路及其驱动方法、显示装置
WO2018214419A1 (zh) 像素电路、像素驱动方法和显示装置
WO2018188390A1 (zh) 像素电路及其驱动方法、显示装置
WO2019205898A1 (zh) 像素电路及其驱动方法、显示面板
WO2018095031A1 (zh) 像素电路及其驱动方法、以及显示面板
WO2018045749A1 (zh) 像素电路、显示面板、显示设备及驱动方法
WO2020001554A1 (zh) 像素电路及其驱动方法、显示面板
WO2017080379A1 (zh) 像素补偿电路及其驱动方法、阵列基板以及显示装置
WO2016011711A1 (zh) 像素电路、像素电路的驱动方法和显示装置
WO2018145499A1 (zh) 像素电路、显示面板、显示装置及驱动方法
WO2016150232A1 (zh) 像素电路及其驱动方法、显示装置
WO2017117932A1 (zh) 像素补偿电路及主动式有机发光二极管显示装置
WO2016070570A1 (zh) 像素电路、显示基板和显示面板
WO2015180353A1 (zh) 像素电路及其驱动方法、oled显示面板和装置
WO2019037300A1 (zh) Amoled像素驱动电路
WO2017117940A1 (zh) 像素驱动电路、像素驱动方法、显示面板和显示装置
WO2019023962A1 (en) PIXEL CIRCUIT, ACTIVE MATRIX ORGANIC LIGHT EMITTING DISPLAY PANEL, DISPLAY APPARATUS, AND ATTACK TRANSISTOR THRESHOLD VOLTAGE COMPENSATION METHOD
WO2017117938A1 (zh) 像素驱动电路、像素驱动方法和显示装置
WO2018099073A1 (zh) 显示面板、显示设备及补偿方法
US9779659B2 (en) Pixel architecture and driving method thereof
WO2017117952A1 (zh) 像素电路及其驱动方法、显示面板以及显示器
WO2018228202A1 (zh) 像素电路、像素驱动方法和显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15569243

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17842594

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205 DATED 09/07/2019)

122 Ep: pct application non-entry in european phase

Ref document number: 17842594

Country of ref document: EP

Kind code of ref document: A1