WO2021007866A1 - 驱动电路、其驱动方法及显示装置 - Google Patents

驱动电路、其驱动方法及显示装置 Download PDF

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Publication number
WO2021007866A1
WO2021007866A1 PCT/CN2019/096615 CN2019096615W WO2021007866A1 WO 2021007866 A1 WO2021007866 A1 WO 2021007866A1 CN 2019096615 W CN2019096615 W CN 2019096615W WO 2021007866 A1 WO2021007866 A1 WO 2021007866A1
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WIPO (PCT)
Prior art keywords
transistor
signal
light
terminal
sub
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PCT/CN2019/096615
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English (en)
French (fr)
Inventor
杨明
丛宁
玄明花
张粲
陈小川
王灿
岳晗
赵蛟
张盎然
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN201980001088.XA priority Critical patent/CN112585670B/zh
Priority to US16/955,171 priority patent/US11373583B2/en
Priority to PCT/CN2019/096615 priority patent/WO2021007866A1/zh
Publication of WO2021007866A1 publication Critical patent/WO2021007866A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0833—Several active elements per pixel in active matrix panels forming a linear amplifier or follower
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0259—Details of the generation of driving signals with use of an analog or digital ramp generator in the column driver or in the pixel circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/066—Waveforms comprising a gently increasing or decreasing portion, e.g. ramp
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a driving circuit, a driving method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum Dot Light Emitting Diodes
  • Micro LED Micro Light Emitting Diode
  • other electroluminescent diodes have self-luminous, low energy consumption, etc.
  • the advantages are one of the hot spots in the application research field of electroluminescent display devices.
  • a driving circuit is used in an electroluminescent display device to drive the electroluminescent diode to emit light.
  • the brightness adjustment range of the electroluminescent diode is limited.
  • the current control circuit is configured to provide a driving signal to the device to be driven according to the signal of the data signal terminal;
  • a first transistor electrically connected between the current control circuit and the device to be driven
  • the duration control circuit is electrically connected to the gate of the first transistor, and is configured to send signals to the first transistor according to the combined action of the scan signal terminal, the light emission control signal terminal, the duration control signal terminal, and the reference voltage signal terminal.
  • the gate provides a light-emitting duration modulation signal to control the conduction duration of the first transistor.
  • the duration control circuit includes: an input control sub-circuit and a comparison sub-circuit;
  • the input control sub-circuit is configured to provide the signal of the duration control signal terminal to the connection node in response to the signal of the scan signal terminal; and provide the signal of the connection node in response to the signal of the light emission control signal terminal To the comparator circuit;
  • the comparator sub-circuit is configured to output the light-emitting duration modulation signal according to the signal output by the input control sub-circuit and the signal at the reference voltage signal terminal.
  • the input control sub-circuit includes: a second transistor, a third transistor, and a first capacitor;
  • the gate of the second transistor is electrically connected to the scan signal terminal, the first electrode of the second transistor is electrically connected to the duration control signal terminal, and the second electrode of the second transistor is electrically connected to the connection node Electrical connection
  • the gate of the third transistor is electrically connected to the light-emitting control signal terminal, the first electrode of the third transistor is electrically connected to the connection node, and the second electrode of the third transistor is electrically connected to the comparison sub-circuit Electrical connection
  • the first capacitor is electrically connected between the first power terminal and the connection node.
  • the comparison sub-circuit includes: a comparator
  • the non-inverting input terminal of the comparator is electrically connected to the input control sub-circuit, the inverting input terminal of the comparator is electrically connected to the reference voltage signal terminal, and the output terminal of the comparator is electrically connected to the first transistor The grid is electrically connected.
  • the current control circuit includes: a driving transistor, a fourth transistor, and a second capacitor;
  • the gate of the fourth transistor is electrically connected to the scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the gate of the driving transistor. Electrical connection
  • the first electrode of the driving transistor is electrically connected to a first power supply terminal, and the second electrode of the driving transistor is electrically connected to the first electrode of the first transistor;
  • the second capacitor is electrically connected between the gate of the driving transistor and the first power terminal.
  • the driving circuit further includes: a fifth transistor; wherein, the first transistor is electrically connected to the device to be driven through the fifth transistor;
  • the gate of the fifth transistor is electrically connected to the light emission control signal terminal.
  • the embodiment of the present disclosure also provides a display device, including:
  • a plurality of sub-pixels located on one side of the base substrate
  • At least one of the plurality of sub-pixels includes: a light-emitting device and the above-mentioned driving circuit; wherein the light-emitting device serves as the device to be driven.
  • the display device further includes: a plurality of light emission control signal lines and a light emission control input terminal; the light emission control signal terminal of the driving circuit of a row of sub-pixels is electrically connected to a light emission control signal line correspondingly ; Each of the light-emitting control signal lines are electrically connected to the light-emitting control input terminal.
  • the display device further includes: a plurality of mutually independent light-emitting control signal lines;
  • the light emission control signal end of the driving circuit of a row of sub-pixels is correspondingly electrically connected to a light emission control signal line.
  • the device to be driven includes at least one of a micro light emitting diode, an organic electroluminescent diode, and a quantum dot light emitting diode.
  • the embodiment of the present disclosure also provides a driving method of the above-mentioned display device.
  • one frame time For each row of sub-pixels, one frame time includes:
  • the current control circuit inputs the signal of the data signal terminal in response to the signal of the scan signal terminal; and the duration control circuit inputs the signal of the duration control signal terminal in response to the signal of the scan signal terminal;
  • the current control circuit During the light-emitting phase, the current control circuit generates a driving current for driving the device to be driven to emit light according to the signal from the data signal terminal; the duration control circuit according to the light-emitting control signal terminal, the reference voltage signal terminal and the input duration control signal
  • the combined action of the signals at the terminal generates a light-emitting duration modulation signal input to the gate of the first transistor to control the turn-on duration of the first transistor; wherein the voltage at the reference voltage signal terminal changes monotonically within a preset duration ,
  • the voltage of the duration control signal terminal is a fixed voltage and the fixed voltage is within a voltage range where the reference voltage signal terminal monotonously changes.
  • FIG. 1 is a schematic structural diagram of a driving circuit provided by an embodiment of the disclosure
  • FIG. 2 is a schematic diagram of some specific structures of a driving circuit provided by an embodiment of the disclosure.
  • FIG. 3 is a schematic diagram of a specific structure of a comparator provided by an embodiment of the disclosure.
  • 4a is a timing diagram of some circuits of a driving circuit provided by an embodiment of the disclosure.
  • 4b is a timing diagram of other circuits of the driving circuit provided by the embodiments of the disclosure.
  • FIG. 4c is a timing diagram of other circuits of the driving circuit provided by the embodiments of the disclosure.
  • FIG. 5 is a schematic diagram of the relationship between the voltage of the reference voltage signal terminal and the voltage of the duration control signal terminal provided by an embodiment of the disclosure
  • FIG. 6 is a schematic diagram of further specific structures of the driving circuit provided by the embodiments of the disclosure.
  • FIG. 7 is a schematic diagram of some specific structures of a display device provided by an embodiment of the disclosure.
  • FIG. 8 is a timing diagram of some circuits of a display device provided by an embodiment of the disclosure.
  • FIG. 9 is a schematic diagram of further specific structures of the display device provided by the embodiments of the disclosure.
  • FIG. 10 is a timing diagram of other circuits of the display device provided by the embodiments of the disclosure.
  • FIG. 11 is a flowchart of a driving method of a display device provided by an embodiment of the disclosure.
  • the embodiment of the present disclosure provides a driving circuit, as shown in FIG. 1, which may include:
  • the current control circuit 10 is configured to provide a driving signal to the device to be driven DL according to the signal of the data signal terminal DT;
  • the first transistor M1 is electrically connected between the current control circuit 10 and the device to be driven DL;
  • the duration control circuit 20 is electrically connected to the gate of the first transistor M1, and is configured to act according to the combined action of the scan signal terminal SC, the light emission control signal terminal EM, the duration control signal terminal SM, and the reference voltage signal terminal VREF.
  • the gate of the first transistor M1 provides a light-emitting duration modulation signal to control the conduction duration of the first transistor M1.
  • the drive circuit provided by the embodiment of the present disclosure can generate a drive signal for driving the device to be driven by setting the current control circuit, and can generate the light-emitting time modulation signal provided to the gate of the first transistor by setting the duration control circuit to control the first transistor.
  • the turn-on time of the transistor In this way, the length of time the device to be driven receives the driving signal can be controlled.
  • the drive signal input to the device to be driven and the on-duration of the first transistor can be controlled separately, so that the on-duration of the first transistor can be controlled independently, and the drive signal of the device to be driven can be input.
  • the adjustment range of the duration is larger.
  • the device to be driven may be a light emitting device, and the driving signal may be used as a driving current for driving the light emitting device to emit light.
  • the duration of the driving current flowing into the light-emitting device can be controlled by controlling the on-time duration of the first transistor to control the light-emitting duration of the light-emitting device. Therefore, the light-emitting duration of the light-emitting device within one frame can be controlled. Since different light-emitting durations can correspond to different gray scales, the display of more gray scales can be realized by controlling the light-emitting duration, and the display effect can be improved.
  • the device to be driven can also be set to other devices, which is not limited here.
  • the device to be driven is a light-emitting device as an example.
  • the first terminal of the light emitting device is electrically connected to the second electrode of the first transistor M1, and the second terminal of the light emitting device is electrically connected to the second power terminal VSS.
  • the first end of the light emitting device is its anode, and the second end is its cathode.
  • the light-emitting device is generally an electroluminescent diode.
  • the light-emitting device may include: Micro Light Emitting Diode (Micro LED), Organic Light Emitting Diode (OLED), and Quantum Dot Light Emitting Diode ( At least one of Quantum Dot Light Emitting Diodes, QLED).
  • general light-emitting devices have a light-emitting threshold voltage, and emit light when the voltage across the light-emitting device is greater than or equal to the light-emitting threshold voltage.
  • the specific structure of the light emitting device can be designed and determined according to the actual application environment, which is not limited here.
  • the duration control circuit 20 may include: an input control sub-circuit 21 and a comparator sub-circuit 22;
  • the input control sub-circuit 21 is configured to provide the signal of the duration control signal terminal SM to the connection node N0 in response to the signal of the scan signal terminal SC; and to provide the signal of the connection node N0 to the signal of the light emission control signal terminal EM Comparator circuit 22;
  • the comparator sub-circuit 22 is configured to output a light-emitting duration modulation signal according to the signal output by the input control sub-circuit 21 and the signal at the reference voltage signal terminal VREF.
  • the input control sub-circuit 21 may include: a second transistor M2, a third transistor M3, and a first capacitor C1;
  • the gate of the second transistor M2 is electrically connected to the scan signal terminal SC, the first electrode of the second transistor M2 is electrically connected to the duration control signal terminal SM, and the second electrode of the second transistor M2 is electrically connected to the connection node N0;
  • the gate of the third transistor M3 is electrically connected to the light emission control signal terminal EM, the first electrode of the third transistor M3 is electrically connected to the connection node N0, and the second electrode of the third transistor M3 is electrically connected to the comparator circuit 22;
  • the first capacitor C1 is electrically connected between the first power terminal VDD and the connection node N0.
  • the second transistor M2 when the second transistor M2 is in the on state under the control of the scan signal terminal SC, it can provide the signal of the duration control signal terminal SM to the connection node N0.
  • the connection node N0 When the third transistor M3 is in the on state under the control of the light emission control signal terminal EM, the connection node N0 can be electrically connected to the comparison sub-circuit 22 to provide the signal of the connection node N0 to the comparison sub-circuit 22.
  • the first capacitor C1 can store the signal of the first power supply terminal VDD and the input connection node N0.
  • the comparison sub-circuit 22 may include a comparator VC; wherein, the non-inverting input terminal PA of the comparator VC is electrically connected to the input control sub-circuit 21, and the comparator
  • the inverting input terminal PB of VC is electrically connected to the reference voltage signal terminal VREF, and the output terminal of the comparator VC is electrically connected to the gate of the first transistor M1.
  • the non-inverting input terminal PA of the comparator VC is electrically connected to the second pole of the third transistor M3 in the input control sub-circuit 21.
  • the output terminal thereof when the voltage of the non-inverting input terminal PA of the comparator VC is greater than the voltage of the inverting input terminal PB, the output terminal thereof outputs a high-level signal.
  • the output terminal thereof When the voltage of the non-inverting input terminal PA of the comparator VC is less than the voltage of the inverting input terminal PB, the output terminal thereof outputs a low-level signal.
  • the comparator VC may include: a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M6.
  • the first electrode of the seventh transistor M7 is electrically connected to the first voltage signal terminal VGH, and the gate and second electrode of the seventh transistor M7 are electrically connected to the first electrode of the eleventh transistor M11.
  • the gate of the eleventh transistor M11 serves as the non-inverting input terminal PA of the comparator VC, and the second electrode of the eleventh transistor M11 is electrically connected to the first electrode of the fourteenth transistor M14.
  • the first electrode of the sixth transistor M6 is electrically connected to the first voltage signal terminal VGH, the gate of the sixth transistor M6 is electrically connected to the gate of the seventh transistor M7, and the second electrode of the sixth transistor M6 is electrically connected to the twelfth transistor M12.
  • the first pole is electrically connected.
  • the gate of the twelfth transistor M12 serves as the inverting input terminal PB of the comparator VC, and the second electrode of the twelfth transistor M12 is electrically connected to the first electrode of the fourteenth transistor M14.
  • the gate of the fourteenth transistor M14 is electrically connected to the gate of the fifteenth transistor M15 and the gate of the thirteenth transistor M13, respectively, and the second electrode of the fourteenth transistor M14 is electrically connected to the second voltage signal terminal VGL.
  • the first electrode of the eighth transistor M8 is electrically connected to the first voltage signal terminal VGH, and the gate and the second electrode of the eighth transistor M8 are electrically connected to the gate and the first electrode of the thirteenth transistor M13, respectively.
  • the second electrode of the thirteenth transistor M13 is electrically connected to the second voltage signal terminal VGL.
  • the gate of the ninth transistor M9 is electrically connected to the first electrode of the twelfth transistor M12, the first electrode of the ninth transistor M9 is electrically connected to the first voltage signal terminal VGH, and the second electrode of the ninth transistor M9 is electrically connected to the tenth transistor M9.
  • the first electrode of the fifth transistor M15, the gate of the tenth transistor M10, and the gate of the sixteenth transistor M16 are electrically connected.
  • the second electrode of the fifteenth transistor M15 is electrically connected to the second voltage signal terminal VGL.
  • the first electrode of the tenth transistor M10 is electrically connected to the first voltage signal terminal VGH, and the second electrode of the tenth transistor M10 is electrically connected to the first electrode of the sixteenth transistor M16 as the output terminal VC-OUT of the comparator VC.
  • the second electrode of the sixteenth transistor M16 is electrically connected to the second voltage signal terminal VGL.
  • the sixth to tenth transistors M6 to M10 may be configured as P-type transistors.
  • the eleventh to sixteenth transistors M11 to M16 may be configured as N-type transistors.
  • the specific types and structures of the above-mentioned transistors can be set according to the actual application environment, which is not limited here.
  • the voltage of the first voltage signal terminal VGH is greater than the voltage of the second voltage signal terminal VGL.
  • the first voltage signal terminal VGH and the first power supply terminal VDD can be the same signal terminal.
  • the voltage of the first voltage signal terminal VGH and the voltage of the second voltage signal terminal VGL can be designed and determined according to the actual application environment, which is not specifically limited here.
  • comparator VC the structure and working principle of the comparator VC can also be basically the same as other comparators in the related art, which will not be repeated here.
  • the current control circuit 10 may include: a driving transistor M0, a fourth transistor M4, and a second capacitor C2;
  • the gate of the fourth transistor M4 is electrically connected to the scan signal terminal SC, the first electrode of the fourth transistor M4 is electrically connected to the data signal terminal DA, and the second electrode of the fourth transistor M4 is electrically connected to the gate of the driving transistor M0;
  • the first electrode of the driving transistor M0 is electrically connected to the first power supply terminal VDD, and the second electrode of the driving transistor M0 is electrically connected to the first electrode of the first transistor M1;
  • the second capacitor C2 is electrically connected between the gate of the driving transistor M0 and the first power terminal VDD.
  • the signal of the data signal terminal DA can be provided to the gate of the driving transistor M0.
  • the second capacitor C2 can store the signal of the gate of the driving transistor M0 and the first power terminal VDD. In this way, the structure of the pixel circuit can be made simpler, thereby reducing the occupied space and the process complexity.
  • the driving transistor M0 can be a P-type transistor; wherein, the first electrode of the driving transistor M0 has its source, and the second electrode of the driving transistor M0 has its drain. And when the driving transistor M0 is in a saturated state, current flows from the source of the driving transistor M0 to its drain.
  • the driving transistor may also be an N-type transistor; wherein, the first electrode of the driving transistor has its drain, the second electrode of the driving transistor has its source, and the driving transistor is in In saturation, current flows from the drain of the drive transistor to its source.
  • the current control circuit may also be a pixel compensation circuit capable of compensating the threshold voltage V th of the driving transistor M0.
  • the structure and working principle of the pixel compensation circuit can be basically the same as those in the related art, and will not be repeated here.
  • the first to fourth transistors M1 to M4 may all be P-type transistors.
  • the first to fourth transistors M1 to M4 can also be N-type transistors, which can also be designed and determined according to the actual application environment, which is not limited herein.
  • the P-type transistor is turned off under the action of a high-level signal, and turned on under the action of a low-level signal.
  • the N-type transistor is turned on under the action of a high-level signal, and cut off under the action of a low-level signal.
  • the transistor mentioned in the above embodiments of the present disclosure may be a thin film transistor (TFT) or a metal oxide semiconductor field effect transistor (MOS), which is not limited here.
  • TFT thin film transistor
  • MOS metal oxide semiconductor field effect transistor
  • the first electrode of the transistor can be used as its source and the second electrode as its drain; or, conversely, the first electrode of the transistor can be used as its drain.
  • the second pole is its source, which can be designed and determined according to the actual application environment, and no specific distinction will be made here.
  • the voltage V dd at the first power supply terminal is generally positive, and the voltage V ss at the second power supply terminal is generally grounded or negative.
  • the specific values of the voltage V dd at the first power supply terminal and the voltage V ss at the second power supply terminal can be designed and determined according to the actual application environment, and are not limited here.
  • the voltage Vref of the reference voltage signal terminal VREF may change monotonously within a preset time period.
  • the voltage Vref of the reference voltage signal terminal VREF may increase from the first voltage V 01 to the second voltage V 02 within a preset time period.
  • the voltage Vref of the reference voltage signal terminal VREF may increase from the first voltage V 01 to the second voltage V 02 in the first preset time period, and in the second preset time period The internal voltage drops from the second voltage V 02 to the first voltage V 01 .
  • the first preset duration and the second preset duration appear continuously.
  • the voltage Vref of the reference voltage signal terminal VREF may increase from the first voltage V 01 to the second voltage V 02 within the first preset time period, and then jump from the second voltage V 02 To the first voltage V 01 , and increase from the first voltage V 01 to the second voltage V 02 within the second preset time period.
  • the first preset duration and the second preset duration appear continuously. It should be noted that the first preset duration and the second preset duration may be the same or different, which is not limited here.
  • the voltage V ref of the reference voltage signal terminal VREF can be reduced from the second voltage V 02 to the first voltage V 01 within a preset time period.
  • the voltage change of the reference voltage signal terminal VREF can be designed and determined according to the actual application environment, which is not limited here.
  • the voltage of the duration control signal terminal SM may be a fixed voltage and the voltage of the duration control signal terminal SM is within a voltage range where the reference voltage signal terminal VREF changes monotonically.
  • the voltage of the duration control signal terminal SM may be a fixed voltage greater than or equal to the first voltage V 01 and less than or equal to the second voltage V 02 .
  • the voltage V 03 of the duration control signal terminal SM may be greater than the first voltage V 01 and less than the second voltage V 02 .
  • the voltage of the duration control signal terminal SM may be equal to the first voltage V 01 .
  • the voltage of the duration control signal terminal SM may also be equal to the second voltage V 02 .
  • the specific values of the first voltage V 01 , the second voltage V 02, and the voltage of the duration control signal terminal SM need to be designed and determined according to the actual application environment, and are not limited here.
  • the driving circuit shown in FIG. 2 as an example, the working process of the driving circuit provided by the embodiment of the present disclosure will be described below in conjunction with the circuit timing diagram shown in FIG. 4a.
  • the signal input sub-phase T11 and the light-emitting phase T20 in the circuit timing diagram shown in FIG. 4a are mainly selected.
  • the reference voltage signal VREF is the voltage at the terminal within a preset length may be increased from a first voltage to a second voltage V 01 V 02, the length of the control signal SM terminal voltage V 03 may be greater than the first voltage V 01 and A fixed voltage less than the second voltage V 02 .
  • the working process of the driving circuit within one frame time may have: a signal input sub-phase T11 and a light-emitting phase T20.
  • the light emitting stage T20 may include: a modulation sub-stage T21 and a light-emitting sub-stage T22.
  • the scan signal terminal SC is a low-level signal, which can control the second transistor M2 and the fourth transistor M4 to be turned on.
  • the light emission control signal terminal EM is a high level signal, which can control the third transistor M3 to turn off.
  • the turned-on fourth transistor M4 can provide the signal of the data signal terminal DA to the gate of the driving transistor M0 and store it through the second capacitor C2.
  • ) 2 K(V dd -V DA -
  • the second transistor M2 may be turned on when the time control signal SM is supplied to the terminal node N0 is connected, the voltage signal at node N0 is connected to V 03, and stored by the first capacitor C1.
  • the scan signal terminal SC is a high-level signal, and the second transistor M2 and the fourth transistor M4 can be controlled to be turned off.
  • the light emission control signal terminal EM is a low-level signal, which can control the third transistor M3 to turn on.
  • the turned-on third transistor M3 can provide the signal of the input connection node N0 to the non-inverting input terminal PA of the comparator AC, so that the voltage of the non-inverting input terminal PA of the comparator AC is V 03 .
  • the voltage of the inverting input terminal PB of the comparator AC is increased from V 01 to V 03 , the voltage of the non-inverting input terminal PA is greater than the voltage of the inverting input terminal PB, so that the output terminal of the comparator AC outputs a high level signal. Since the comparator AC outputs a high-level signal, the first transistor M1 can be controlled to be turned off, so that the light-emitting device DL can stop emitting light in the modulation sub-phase T21.
  • the scan signal terminal SC is a high-level signal, and the second transistor M2 and the fourth transistor M4 can be controlled to be turned off.
  • the light emission control signal terminal EM is a low-level signal, which can control the third transistor M3 to turn on.
  • the turned-on third transistor M3 can provide the signal of the input connection node N0 to the non-inverting input terminal PA of the comparator AC, so that the voltage of the non-inverting input terminal PA of the comparator AC is V 03 .
  • the voltage of the inverting input terminal PB of the comparator AC is increased from V 03 to V 02 , the voltage of the non-inverting input terminal PA is smaller than the voltage of the inverting input terminal PB, so that the output terminal of the comparator AC outputs a low-level signal. Since the comparator AC outputs a low-level signal, the first transistor M1 can be controlled to be turned on, so that the driving current I generated by the driving transistor M0 can be provided to the light-emitting device DL to drive the light-emitting device DL to emit light in the light-emitting sub-phase T22.
  • the sustaining duration of the modulation sub-phase T21 and the sustaining duration of the light-emitting sub-phase T22 can be controlled by setting the magnitude of the voltage V 03 of the duration control signal terminal SM. For example, as shown in FIG. 5, when the voltage of the duration control signal terminal SM is set to V 03-1 , the sustain duration of the light-emitting sub-phase T22 is t22-1 and the sustain duration of the modulation sub-phase T21 is t21-1.
  • the sustain duration of the light-emitting sub-phase T22 is t22-2 and the sustain duration of the modulation sub-phase T21 is t21-2.
  • V 03-1 ⁇ V 03-2. Therefore, it can be seen that when the voltage of the duration control signal terminal SM is increased, the maintenance duration of the light-emitting sub-phase T22 can be reduced. Conversely, when the voltage of the duration control signal terminal SM is reduced, the sustain duration of the light-emitting sub-phase T22 can be increased.
  • the voltage of the signal terminal SM can be controlled by adjusting the duration to control the light-emitting duration of the light-emitting device DL, and the light-emitting duration can be controlled to achieve more grayscale display and improve the display effect.
  • the light-emitting phase T20 may include: a modulation sub-phase T21, a light-emitting sub-phase T22, and a modulation sub-phase T23.
  • the working process of the modulation sub-phase T21 can be referred to the working process in the embodiment of FIG. 4a, which is not repeated here.
  • the scan signal terminal SC is a high-level signal, and the second transistor M2 and the fourth transistor M4 can be controlled to be turned off.
  • the light emission control signal terminal EM is a low-level signal, which can control the third transistor M3 to turn on.
  • the turned-on third transistor M3 can provide the signal of the input connection node N0 to the non-inverting input terminal PA of the comparator AC, so that the voltage of the non-inverting input terminal PA of the comparator AC is V 03 .
  • the voltage of the inverting input terminal PB of the comparator AC is increased from V 03 to V 02 , the voltage of the non-inverting input terminal PA is smaller than the voltage of the inverting input terminal PB, so that the output terminal of the comparator AC outputs a low-level signal. Since the comparator AC outputs a low-level signal, the first transistor M1 can be controlled to be turned on, so that the driving current I generated by the driving transistor M0 can be provided to the light-emitting device DL to drive the light-emitting device DL to emit light.
  • the scan signal terminal SC is a high-level signal, and the second transistor M2 and the fourth transistor M4 can be controlled to be turned off.
  • the light emission control signal terminal EM is a low-level signal, which can control the third transistor M3 to turn on.
  • the turned-on third transistor M3 can provide the signal of the input connection node N0 to the non-inverting input terminal PA of the comparator AC, so that the voltage of the non-inverting input terminal PA of the comparator AC is V 03 .
  • the voltage of the inverting input terminal PB of the comparator AC is reduced from V 02 to V 02 , the voltage of the non-inverting input terminal PA is less than the voltage of the inverting input terminal PB, so that the output terminal of the comparator AC outputs a low-level signal. Since the comparator AC outputs a low-level signal, the first transistor M1 can be controlled to be turned on, so that the driving current I generated by the driving transistor M0 can be provided to the light-emitting device DL to drive the light-emitting device DL to emit light.
  • the scan signal terminal SC is a high-level signal, and the second transistor M2 and the fourth transistor M4 can be controlled to be turned off.
  • the light emission control signal terminal EM is a low-level signal, which can control the third transistor M3 to turn on.
  • the turned-on third transistor M3 can provide the signal of the input connection node N0 to the non-inverting input terminal PA of the comparator AC, so that the voltage of the non-inverting input terminal PA of the comparator AC is V 03 .
  • the voltage of the inverting input terminal PB of the comparator AC is reduced from V 03 to V 01 , the voltage of the non-inverting input terminal PA is greater than the voltage of the inverting input terminal PB, so that the output terminal of the comparator AC outputs a high level signal. Since the comparator AC outputs a high-level signal, the first transistor M1 can be controlled to be turned off, so that the light-emitting device DL can stop emitting light in the modulation sub-phase T23.
  • the light-emitting phase T20 may include: a modulation sub-phase T21, a light-emitting sub-phase T22, a modulation sub-phase T23, and a light-emitting sub-phase T22.
  • the working processes of the modulation sub-stage T21 and the light-emitting sub-stage T22 can be referred to the working processes of the modulation sub-stage T21 and the light-emitting sub-stage T22 in the embodiment of FIG. 4a.
  • the working process of the modulation sub-phase T23 may refer to the working process of the modulation sub-phase T21 in the embodiment of FIG. 4a.
  • the working process of the light-emitting sub-stage T22 can be referred to the working process of the light-emitting sub-stage T22 in the embodiment of FIG. 4a, which is not repeated here.
  • the light-emitting duration can also be adjusted by adjusting the voltage of the reference voltage signal terminal VREF.
  • FIG. 6 The schematic structural diagrams of other driving circuits provided by the embodiments of the present disclosure are shown in FIG. 6, which are modified with respect to the implementation in the foregoing embodiment. The following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities are not repeated here.
  • the driving circuit further includes: a fifth transistor M5; wherein, the first transistor M1 is electrically connected to the device to be driven DL through the fifth transistor M5; The gate of the five transistor M5 is electrically connected to the light emission control signal terminal EM.
  • the driving transistor M0 will generate a driving current. Due to the leakage current phenomenon of the transistor, the first transistor M1 may have a leakage current, resulting in the driving current generated by the driving transistor M0 passing through the first transistor M1. The leakage current flows into the light-emitting device, which in turn causes the light-emitting device to emit light, reducing the display effect.
  • the fifth transistor M5 and controlling the fifth transistor M5 to be turned off in the signal input sub-phase T11 the problem of reduced display effect due to the leakage current phenomenon can be improved.
  • the fifth transistor M5 controls the fifth transistor M5 to be turned on in the light-emitting phase T20, the first transistor M1 and the light-emitting device can be turned on, and the driving current generated by the driving transistor M0 can be input to the light-emitting device when the first transistor M1 is turned on In, the light emitting device is driven to emit light.
  • the fifth transistor M5 can also be configured as a P-type transistor or an N-type transistor, which is not limited herein.
  • circuit timing diagram corresponding to the structure of the driving circuit shown in FIG. 6 may also be as shown in FIG. 4a, and the specific working process can refer to the above-mentioned embodiment, and the details are not repeated here.
  • an embodiment of the present disclosure also provides a display device, as shown in FIG. 7, which may include: a base substrate 100; and a plurality of sub-pixels 110 located on one side of the base substrate.
  • a display device may include: a base substrate 100; and a plurality of sub-pixels 110 located on one side of the base substrate.
  • at least one of the plurality of sub-pixels may include: a light-emitting device 111 and the above-mentioned driving circuit 112; wherein, the light-emitting device 111 is used as a device DL to be driven.
  • the structure and working principle of the driving circuit 112 can be referred to the above-mentioned embodiments, which will not be repeated here.
  • the same reference voltage signal may be applied to the reference voltage signal terminal of the driving circuit in each sub-pixel.
  • the complexity of the circuit that outputs signals to the reference voltage signal terminal VREF can be reduced, control is facilitated, and the number of signal lines is reduced.
  • the display device may further include: a reference voltage input terminal 120 located on the base substrate 100; and a reference voltage input terminal 120 It may be located in the bonding area BG of the base substrate 100, and the reference voltage signal terminal VREF of each driving circuit 112 is electrically connected to the reference voltage input terminal 120.
  • a reference voltage input terminal 120 is used to input the same signal to the reference voltage signal terminals VREF of all driving circuits 112 in the display device, which can reduce the space occupied by the reference voltage input terminal 120.
  • the same light-emitting control signal may be applied to the light-emitting control signal terminal of the driving circuit in each sub-pixel.
  • the complexity of the circuit outputting signals to the emission control signal terminal EM can be reduced, the control is facilitated, and the number of signal lines can be reduced.
  • the display device may further include: a plurality of light-emitting control signal lines 130 and a bonding area BG located in the base substrate 100 A lighting control input terminal 140.
  • the light emission control signal terminal EM of the driving circuit 111 of a row of sub-pixels 110 is correspondingly electrically connected to one light emission control signal line 130; each light emission control signal line 140 is electrically connected to the light emission control input terminal 140.
  • one light emission control input terminal 140 is used to input the same signal to the light emission control signal terminals EM of all driving circuits 112 in the display device, which can reduce the space occupied by the light emission control input terminal 140.
  • the display device may further include: multiple independent gate lines, multiple independent data lines, and multiple independent time control signal lines.
  • the scan signal terminal of the drive circuit of a row of sub-pixels is electrically connected to a gate line
  • the data signal terminal of the drive circuit of a column of sub-pixels is electrically connected to a data line
  • the duration control signal terminal of the drive circuit of a column of sub-pixels is electrically connected.
  • the gate line, the data line, the duration control signal line, the light-emitting control signal line, and the signal electrically connected to the reference voltage input terminal are respectively insulated from each other.
  • each sub-pixel may be located in the display area of the base substrate to achieve a display effect.
  • a general display device includes a plurality of pixel units, and at least one of the plurality of pixel units may include a plurality of sub-pixels.
  • the pixel unit may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that display can be realized by mixing red, green and blue.
  • the pixel unit may also include red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels, so that display can be realized by mixing red, green, blue and white.
  • the base substrate is further provided with a binding area BG.
  • the binding area BG may be provided with terminals for binding.
  • the reference voltage input terminal 120 and the light emission control input terminal 140 can be arranged in the binding area BG. Moreover, since only one reference voltage input terminal 120 and one light emission control input terminal 140 are provided, this can reduce the occupied space of the binding area BG.
  • an embodiment of the present disclosure also provides a display device driving method. As shown in FIG. 11, for each row of sub-pixels, one frame time includes:
  • the current control circuit responds to the signal at the scan signal terminal and inputs the signal at the data signal terminal; and the duration control circuit responds to the signal at the scan signal terminal and inputs the signal at the duration control signal terminal;
  • the current control circuit In the light-emitting stage, the current control circuit generates a drive signal for driving the device to be driven to emit light according to the signal from the data signal terminal;
  • the gate of a transistor provides a light-emitting duration modulation signal to control the turn-on duration of the first transistor; wherein the voltage at the reference voltage signal terminal changes monotonously within a preset duration, the voltage at the duration control signal terminal is a fixed voltage and the duration controls the voltage at the signal terminal In the voltage range where the reference voltage signal terminal monotonously changes.
  • the signal input stage T10 and the light emitting stage T20 in the circuit timing diagram shown in FIG. 8 are mainly selected.
  • the voltage of the reference voltage signal terminal VREF can be increased from the first voltage V 01 to the second voltage V 02 within the preset time period, and the voltage of the duration control signal terminal SM can be greater than the first voltage V 01 and less than the first voltage V 01 .
  • the fixed voltage V 03 of the second voltage V 02 is mainly selected.
  • the working phase of the display device within one frame time may have a signal input phase T10 and a light emitting phase T20.
  • the signal input stage T10 may include multiple signal input sub-stages T11-n (1 ⁇ n ⁇ N, and both N and n are integers, and N represents the total number of rows of sub-pixels in the display device).
  • the light-emitting phase T20 may include: a modulation sub-phase T21 and a light-emitting sub-phase T22.
  • a signal is loaded row by row to the scan signal terminal of the driving circuit in each row of sub-pixels to drive each row of sub-pixels row by row.
  • the first row to the third row of sub-pixels are taken as an example for description.
  • SC-1 represents the signal received by the scan signal terminal SC of the drive circuit of the first row of sub-pixels
  • SC-2 represents the signal received by the scan signal terminal SC of the drive circuit of the second row of sub-pixels
  • SC-3 represents the third The signal received by the scan signal terminal SC of the driving circuit of the row sub-pixel.
  • da represents a signal transmitted on a data line
  • sm represents a signal transmitted on a duration control signal line.
  • the first row of sub-pixels is driven.
  • the scan signal terminal SC of the driving circuit in the first row of sub-pixels is a low-level signal, which can control the second transistor M2 and the fourth transistor M4 to be turned on.
  • the light emission control signal terminal EM is a high-level signal, which can control the third transistor M3 and the fifth transistor M5 to turn off.
  • the turned-on fourth transistor M4 can provide the signal da transmitted to the data signal terminal DA through the data line to the gate of the driving transistor M0 and store it through the second capacitor C2.
  • ) 2 K(V dd -V DA-1 -
  • V sg is the source-gate voltage of the driving transistor M0;
  • K is a structural parameter. In the same structure, this value is relatively stable and can be counted as a constant .
  • the turned-on second transistor M2 can provide the signal sm transmitted from the duration control signal line to the duration control signal terminal SM to the connection node N0, so that the voltage of the signal connected to the node N0 is V 03-1 , and is performed through the first capacitor C1 storage.
  • the second row of sub-pixels is driven.
  • the scan signal terminal SC of the driving circuit in the second row of sub-pixels is a low-level signal, which can control the second transistor M2 and the fourth transistor M4 to be turned on.
  • the light emission control signal terminal EM is a high level signal, which can control the third transistor M3 and the fifth transistor M5 to turn off.
  • the turned-on fourth transistor M4 can provide the signal da transmitted to the data signal terminal DA through the data line to the gate of the driving transistor M0 and store it through the second capacitor C2.
  • ) 2 K(V dd -V DA-2 -
  • V sg is the source-gate voltage of the driving transistor M0;
  • K is a structural parameter. In the same structure, this value is relatively stable and can be counted as a constant .
  • the turned-on second transistor M2 can provide the signal sm transmitted from the duration control signal line to the duration control signal terminal SM to the connection node N0, so that the voltage of the signal connected to the node N0 is V 03-2 , and is performed through the first capacitor C1 storage.
  • the third row of sub-pixels is driven.
  • the scan signal terminal SC of the driving circuit in the third row of sub-pixels is a low-level signal, which can control the second transistor M2 and the fourth transistor M4 to be turned on.
  • the light emission control signal terminal EM is a high-level signal, which can control the third transistor M3 and the fifth transistor M5 to turn off.
  • the turned-on fourth transistor M4 can provide the signal da transmitted to the data signal terminal DA through the data line to the gate of the driving transistor M0 and store it through the second capacitor C2.
  • ) 2 K(V dd -V DA-3 -
  • V sg is the source-gate voltage of the driving transistor M0;
  • K is a structural parameter. In the same structure, this value is relatively stable and can be counted as a constant .
  • the turned-on second transistor M2 can provide the signal sm transmitted from the duration control signal line to the duration control signal terminal SM to the connection node N0, so that the voltage of the signal connected to the node N0 is V 03-3 and is performed through the first capacitor C1 storage.
  • the scan signal terminal SC of each driving circuit in the display device is a high-level signal, and the second transistor M2 and the fourth transistor M4 can be controlled to be turned off.
  • the light emission control signal terminal EM of each driving circuit in the display device is a low-level signal, which can control the third transistor M3 and the fifth transistor M5 to be turned on.
  • the turned-on third transistor M3 can provide the signal input to the connection node N0 to the non-inverting input terminal PA of the comparator AC.
  • the light-emitting phase T20 may include a modulation sub-phase T21-1 and a light-emitting sub-phase T22-1.
  • the modulation sub-phase T21-1 since the turned-on third transistor M3 can provide the signal input to the connection node N0 to the non-inverting input terminal PA of the comparator AC, the voltage of the non-inverting input terminal PA of the comparator AC is V 03-1 .
  • the voltage of the inverting input terminal PB of the comparator AC is increased from V01 to V03-1, the voltage of the non-inverting input terminal PA is greater than the voltage of the inverting input terminal PB, so that the output terminal of the comparator AC outputs a high level signal. Since the comparator AC outputs a high-level signal, the first transistor M1 can be controlled to be turned off, so that the light-emitting device DL can stop emitting light in the modulation sub-phase T21-1.
  • the voltage of the inverting input terminal PB of the comparator AC is increased from V 03-1 to V 02 , the voltage of the non-inverting input terminal PA is less than the voltage of the inverting input terminal PB, thus making the comparison
  • the output terminal of the converter AC outputs a low-level signal. Since the comparator AC outputs a low-level signal, the first transistor M1 can be controlled to be turned on, so that the driving current I generated by the driving transistor M0 can be provided to the light-emitting device DL to drive the light-emitting device DL to emit light in the light-emitting sub-phase T22-1.
  • the light-emitting phase T20 may include a modulation sub-phase T21-2 and a light-emitting sub-phase T22-2.
  • the modulation sub-phase T21-2 since the turned-on third transistor M3 can provide the signal input to the connection node N0 to the non-inverting input terminal PA of the comparator AC, the voltage of the non-inverting input terminal PA of the comparator AC is V 03-2 .
  • the voltage of the inverting input terminal PB of the comparator AC is increased from V01 to V 03-2 , the voltage of the non-inverting input terminal PA is greater than the voltage of the inverting input terminal PB, so that the output terminal of the comparator AC outputs a high level signal . Since the comparator AC outputs a high-level signal, the first transistor M1 can be controlled to be turned off, so that the light-emitting device DL can stop emitting light in the modulation sub-phase T21-2.
  • the voltage of the inverting input terminal PB of the comparator AC is increased from V 03-2 to V 02 , the voltage of the non-inverting input terminal PA is less than the voltage of the inverting input terminal PB, so that the comparison
  • the output terminal of the converter AC outputs a low-level signal. Since the comparator AC outputs a low-level signal, the first transistor M1 can be controlled to be turned on, so that the driving current I generated by the driving transistor M0 can be provided to the light-emitting device DL to drive the light-emitting device DL to emit light in the light-emitting sub-phase T22-2.
  • the light-emitting phase T20 may include a modulation sub-phase T21-3 and a light-emitting sub-phase T22-3.
  • the modulation sub-stage T21-3 since the turned-on third transistor M3 can provide the signal input to the connection node N0 to the non-inverting input terminal PA of the comparator AC, the voltage of the non-inverting input terminal PA of the comparator AC is V 03-3 .
  • the voltage of the inverting input terminal PB of the comparator AC is increased from V01 to V 03-3 , the voltage of the non-inverting input terminal PA is greater than the voltage of the inverting input terminal PB, so that the output terminal of the comparator AC outputs a high level signal . Since the comparator AC outputs a high-level signal, the first transistor M1 can be controlled to be turned off, so that the light-emitting device DL can stop emitting light in the modulation sub-phase T21-3.
  • the voltage of the inverting input terminal PB of the comparator AC is increased from V 03-3 to V 02 , the voltage of the non-inverting input terminal PA is less than the voltage of the inverting input terminal PB, so that the comparison
  • the output terminal of the converter AC outputs a low-level signal. Since the comparator AC outputs a low-level signal, the first transistor M1 can be controlled to be turned on, so that the driving current I generated by the driving transistor M0 can be provided to the light-emitting device DL to drive the light-emitting device DL to emit light in the light-emitting sub-phase T22-3.
  • the light-emitting duration of the light-emitting device DL can be adjusted, so that more grayscale display can be achieved by controlling the light-emitting duration, and the display effect can be improved.
  • the preset duration may be set as the sustain duration of the light-emitting phase T20.
  • the preset duration can also be set to other times, which is not limited here.
  • the voltage Vref of the reference voltage signal terminal VREF can also oscillate and change within a preset time period
  • the voltage of the duration control signal terminal is a fixed voltage
  • the voltage of the duration control signal terminal is within the range of the reference voltage signal terminal. Within the voltage range provided.
  • FIG. 9 The schematic structural diagrams of other display devices provided by the embodiments of the present disclosure are shown in FIG. 9, which are modified with respect to the implementation in the foregoing embodiments. The following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities are not repeated here.
  • the display device may further include: a plurality of mutually independent light-emitting control signal lines 150; wherein, a row of sub-pixel driving circuits 112
  • the light emission control signal terminal EM is correspondingly electrically connected to a light emission control signal line 150.
  • different signals can be input to each light-emitting control signal line 150 to control the third transistor M3 and the fifth transistor M5 to be turned on row by row.
  • the same signal can also be input to each light emission control signal line 150 to control the third transistor M3 and the fifth transistor M5 to be turned on at the same time.
  • the signal input stage T10 and the light emitting stage T20 in the circuit timing diagram shown in FIG. 9 are mainly selected.
  • the voltage of the reference voltage signal terminal VREF can be increased from the first voltage V 01 to the second voltage V 02 within the preset time period, and the voltage of the duration control signal terminal SM can be greater than the first voltage V 01 and less than the first voltage V 01 .
  • the fixed voltage V 03 of the second voltage V 02 is mainly selected.
  • the working phase of the display device within one frame time may have a signal input phase T10 and a light emitting phase T20.
  • the signal input stage T10 may include multiple signal input sub-stages T11-n (1 ⁇ n ⁇ N, and both N and n are integers, and N represents the total number of rows of sub-pixels in the display device).
  • the light-emitting phase T20 may include: a modulation sub-phase T21 and a light-emitting sub-phase T22.
  • a signal is applied to the scan signal terminal of the driving circuit in each row of sub-pixels row by row to drive each row of sub-pixels row by row.
  • the first row to the third row of sub-pixels are taken as an example for description.
  • SC-1 represents the signal received by the scan signal terminal SC of the driving circuit of the first row of sub-pixels
  • EM-1 represents the signal received by the light emission control signal terminal EM of the driving circuit of the first row of sub-pixels
  • SC-2 represents the signal received by the scan signal terminal SC of the driving circuit of the second row of sub-pixels
  • EM-2 represents the signal received by the light emission control signal terminal EM of the driving circuit of the second row of sub-pixels.
  • SC-3 represents the signal received by the scan signal terminal SC of the driving circuit of the third row of sub-pixels
  • EM-3 represents the signal received by the emission control signal terminal EM of the driving circuit of the third row of sub-pixels.
  • da represents a signal transmitted on a data line
  • sm represents a signal transmitted on a duration control signal line.
  • the first row of sub-pixels is driven.
  • the scan signal terminal SC of the driving circuit in the first row of sub-pixels is a low-level signal, which can control the second transistor M2 and the fourth transistor M4 to be turned on.
  • the light emission control signal terminal EM is a high level signal, which can control the third transistor M3 and the fifth transistor M5 to turn off.
  • the turned-on fourth transistor M4 can provide the signal da transmitted to the data signal terminal DA through the data line to the gate of the driving transistor M0 and store it through the second capacitor C2.
  • ) 2 K(V dd -V DA-1 -
  • V sg is the source-gate voltage of the driving transistor M0;
  • K is a structural parameter. In the same structure, this value is relatively stable and can be counted as a constant .
  • the turned-on second transistor M2 can provide the signal sm transmitted from the duration control signal line to the duration control signal terminal SM to the connection node N0, so that the voltage of the signal connected to the node N0 is V 03-1 , and is performed through the first capacitor C1 storage.
  • the scan signal terminal SC of the driving circuit in the first row of sub-pixels is a high-level signal, and the second transistor M2 and the fourth transistor M4 can be controlled to be turned off.
  • the light emission control signal terminal EM is a low-level signal, which can control the third transistor M3 and the fifth transistor M5 to turn on.
  • the second row of sub-pixels is driven.
  • the scan signal terminal SC of the driving circuit in the second row of sub-pixels is a low-level signal, which can control the second transistor M2 and the fourth transistor M4 to be turned on.
  • the light emission control signal terminal EM is a high level signal, which can control the third transistor M3 and the fifth transistor M5 to turn off.
  • the turned-on fourth transistor M4 can provide the signal da transmitted to the data signal terminal DA through the data line to the gate of the driving transistor M0 and store it through the second capacitor C2.
  • ) 2 K(V dd -V DA-2 -
  • V sg is the source-gate voltage of the driving transistor M0;
  • K is a structural parameter. In the same structure, this value is relatively stable and can be counted as a constant .
  • the turned-on second transistor M2 can provide the signal sm transmitted from the duration control signal line to the duration control signal terminal SM to the connection node N0, so that the voltage of the signal connected to the node N0 is V 03-2 , and is performed through the first capacitor C1 storage.
  • the scan signal terminal SC of the driving circuit in the second row of sub-pixels is a high-level signal, and the second transistor M2 and the fourth transistor M4 can be controlled to be turned off.
  • the light emission control signal terminal EM is a low-level signal, which can control the third transistor M3 and the fifth transistor M5 to turn on.
  • the third row of sub-pixels is driven.
  • the scan signal terminal SC of the driving circuit in the third row of sub-pixels is a low-level signal, which can control the second transistor M2 and the fourth transistor M4 to be turned on.
  • the light emission control signal terminal EM is a high level signal, which can control the third transistor M3 and the fifth transistor M5 to turn off.
  • the turned-on fourth transistor M4 can provide the signal da transmitted to the data signal terminal DA through the data line to the gate of the driving transistor M0 and store it through the second capacitor C2.
  • ) 2 K(V dd -V DA-3 -
  • V sg is the source-gate voltage of the driving transistor M0;
  • K is a structural parameter, this value is relatively stable in the same structure and can be counted as a constant .
  • the turned-on second transistor M2 can provide the signal sm transmitted from the duration control signal line to the duration control signal terminal SM to the connection node N0, so that the voltage of the signal connected to the node N0 is V 03-3 and is performed through the first capacitor C1 storage.
  • the scan signal terminal SC of the driving circuit in the third row of sub-pixels is a high-level signal, and the second transistor M2 and the fourth transistor M4 can be controlled to be turned off.
  • the light emission control signal terminal EM is a low-level signal, which can control the third transistor M3 and the fifth transistor M5 to turn on.
  • the scan signal terminal SC of each driving circuit in the display device is a high-level signal, and the second transistor M2 and the fourth transistor M4 can be controlled to be turned off.
  • the light emission control signal terminal EM of each driving circuit in the display device is a low-level signal, which can control the third transistor M3 and the fifth transistor M5 to be turned on.
  • the turned-on third transistor M3 can provide the signal input to the connection node N0 to the non-inverting input terminal PA of the comparator AC.
  • the light-emitting phase T20 may include a modulation sub-phase T21-1 and a light-emitting sub-phase T22-1.
  • the modulation sub-phase T21-1 since the turned-on third transistor M3 can provide the signal input to the connection node N0 to the non-inverting input terminal PA of the comparator AC, the voltage of the non-inverting input terminal PA of the comparator AC is V 03-1 .
  • the voltage of the inverting input terminal PB of the comparator AC is increased from V01 to V 03-1 , the voltage of the non-inverting input terminal PA is greater than the voltage of the inverting input terminal PB, so that the output terminal of the comparator AC outputs a high level signal . Since the comparator AC outputs a high-level signal, the first transistor M1 can be controlled to be turned off, so that the light-emitting device DL can stop emitting light in the modulation sub-phase T21-1.
  • the voltage of the inverting input terminal PB of the comparator AC is increased from V 03-1 to V 02 , the voltage of the non-inverting input terminal PA is less than the voltage of the inverting input terminal PB, thus making the comparison
  • the output terminal of the converter AC outputs a low-level signal. Since the comparator AC outputs a low-level signal, the first transistor M1 can be controlled to be turned on, so that the driving current I generated by the driving transistor M0 can be provided to the light-emitting device DL to drive the light-emitting device DL to emit light in the light-emitting sub-phase T22-1.
  • the light-emitting phase T20 may include a modulation sub-phase T21-2 and a light-emitting sub-phase T22-2.
  • the modulation sub-phase T21-2 since the turned-on third transistor M3 can provide the signal input to the connection node N0 to the non-inverting input terminal PA of the comparator AC, the voltage of the non-inverting input terminal PA of the comparator AC is V 03-2 .
  • the voltage of the inverting input terminal PB of the comparator AC is increased from V 01 to V 03-2 , the voltage of the non-inverting input terminal PA is greater than the voltage of the inverting input terminal PB, so that the output terminal of the comparator AC outputs a high level signal. Since the comparator AC outputs a high-level signal, the first transistor M1 can be controlled to be turned off, so that the light-emitting device DL can stop emitting light in the modulation sub-phase T21-2.
  • the voltage of the inverting input terminal PB of the comparator AC is increased from V 03-2 to V 02 , the voltage of the non-inverting input terminal PA is less than the voltage of the inverting input terminal PB, so that the comparison
  • the output terminal of the converter AC outputs a low-level signal. Since the comparator AC outputs a low-level signal, the first transistor M1 can be controlled to be turned on, so that the driving current I generated by the driving transistor M0 can be provided to the light-emitting device DL to drive the light-emitting device DL to emit light in the light-emitting sub-phase T22-2.
  • the light-emitting phase T20 may include a modulation sub-phase T21-3 and a light-emitting sub-phase T22-3.
  • the modulation sub-stage T21-3 since the turned-on third transistor M3 can provide the signal input to the connection node N0 to the non-inverting input terminal PA of the comparator AC, the voltage of the non-inverting input terminal PA of the comparator AC is V 03-3 .
  • the voltage of the inverting input terminal PB of the comparator AC is increased from V 01 to V 03-3 , the voltage of the non-inverting input terminal PA is greater than the voltage of the inverting input terminal PB, so that the output terminal of the comparator AC outputs a high level signal. Since the comparator AC outputs a high-level signal, the first transistor M1 can be controlled to be turned off, so that the light-emitting device DL can stop emitting light in the modulation sub-phase T21-3.
  • the voltage of the inverting input terminal PB of the comparator AC is increased from V 03-3 to V 02 , the voltage of the non-inverting input terminal PA is less than the voltage of the inverting input terminal PB, so that the comparison
  • the output terminal of the converter AC outputs a low-level signal. Since the comparator AC outputs a low-level signal, the first transistor M1 can be controlled to be turned on, so that the driving current I generated by the driving transistor M0 can be provided to the light-emitting device DL to drive the light-emitting device DL to emit light in the light-emitting sub-phase T22-3.
  • the light-emitting duration of the light-emitting device DL can be adjusted, so that more grayscale display can be achieved by controlling the light-emitting duration, and the display effect can be improved.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • the other indispensable components of the display device are understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as a limitation to the present disclosure.
  • the driving current for driving the device to be driven can be generated by setting the current control circuit, and the light-emitting duration modulation input to the gate of the first transistor can be generated by setting the duration control circuit Signal to control the on-time of the first transistor.
  • the length of time the device to be driven receives the driving current can be controlled.
  • the driving current flowing into the device to be driven and the turn-on duration of the first transistor can be controlled separately, so that the turn-on duration of the first transistor can be controlled independently, and the driving current flowing into the device to be driven can be controlled independently.
  • the adjustment range of the duration is larger.

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Abstract

一种驱动电路（112）、其驱动方法及显示装置，包括：电流控制电路（10），被配置为根据数据信号端（DA）的信号（da）向待驱动器件（DL）提供驱动信号；第一晶体管（M1），电连接于电流控制电路（10）与待驱动器件（DL）之间；时长控制电路（20），与第一晶体管（M1）的栅极电连接，且被配置为根据扫描信号端（SC）的信号（SC-1，SC-2，SC-3）、发光控制信号端（EM）的信号（EM-1，EM-2，EM-3）、时长控制信号端（SM）的信号（sm）以及基准电压信号端（VREF）的信号的共同作用，向第一晶体管（M1）的栅极提供发光时长调制信号，以控制第一晶体管（M1）的导通时长。

Description

驱动电路、其驱动方法及显示装置 技术领域
本公开涉及显示技术领域，特别涉及驱动电路、其驱动方法及显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)、量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)、微型发光二极管(Micro Light Emitting Diode，Micro LED)等电致发光二极管具有自发光、低能耗等优点，是当今电致发光显示装置应用研究领域的热点之一。一般电致发光显示装置中采用驱动电路来驱动电致发光二极管发光。然而，由于制程的限制，使得电致发光二极管亮度调节范围受限。
发明内容
本公开实施例提供的驱动电路，包括：
电流控制电路，被配置为根据数据信号端的信号向待驱动器件提供驱动信号；
第一晶体管，电连接于所述电流控制电路与所述待驱动器件之间；
时长控制电路，与所述第一晶体管的栅极电连接，且被配置为根据扫描信号端、发光控制信号端、时长控制信号端以及基准电压信号端的信号的共同作用，向所述第一晶体管的栅极提供发光时长调制信号，以控制所述第一晶体管的导通时长。
可选地，在本公开实施例中，所述时长控制电路包括：输入控制子电路和比较子电路；
所述输入控制子电路被配置为响应于所述扫描信号端的信号，将所述时长控制信号端的信号提供给连接节点；以及响应于所述发光控制信号端的信号，将所述连接节点的信号提供给所述比较子电路；
所述比较子电路被配置为根据所述输入控制子电路输出的信号与所述基准电压信号端的信号，输出所述发光时长调制信号。
可选地，在本公开实施例中，所述输入控制子电路包括：第二晶体管、第三晶体管以及第一电容；
所述第二晶体管的栅极与所述扫描信号端电连接，所述第二晶体管的第一极与所述时长控制信号端电连接，所述第二晶体管的第二极与所述连接节点电连接；
所述第三晶体管的栅极与所述发光控制信号端电连接，所述第三晶体管的第一极与所述连接节点电连接，所述第三晶体管的第二极与所述比较子电路电连接；
所述第一电容电连接于第一电源端与所述连接节点之间。
可选地，在本公开实施例中，所述比较子电路包括：比较器；
所述比较器的同相输入端与所述输入控制子电路电连接，所述比较器的反相输入端与所述基准电压信号端电连接，所述比较器的输出端与所述第一晶体管的栅极电连接。
可选地，在本公开实施例中，所述电流控制电路包括：驱动晶体管、第四晶体管以及第二电容；
所述第四晶体管的栅极与所述扫描信号端电连接，所述第四晶体管的第一极与数据信号端电连接，所述第四晶体管的第二极与所述驱动晶体管的栅极电连接；
所述驱动晶体管的第一极与第一电源端电连接，所述驱动晶体管的第二极与所述第一晶体管的第一极电连接；
所述第二电容电连接于所述驱动晶体管的栅极与所述第一电源端之间。
可选地，在本公开实施例中，所述驱动电路还包括：第五晶体管；其中，所述第一晶体管通过所述第五晶体管与所述待驱动器件电连接；
所述第五晶体管的栅极与所述发光控制信号端电连接。
本公开实施例还提供了显示装置，包括：
衬底基板；
多个子像素，位于所述衬底基板一侧；
所述多个子像素中的至少一个包括：发光器件和上述驱动电路；其中，所述发光器件作为所述待驱动器件。
可选地，在本公开实施例中，所述显示装置还包括：多条发光控制信号线与一个发光控制输入端子；一行子像素的驱动电路的发光控制信号端对应电连接一条发光控制信号线；各所述发光控制信号线均电连接所述发光控制输入端子。
可选地，在本公开实施例中，所述显示装置还包括：多条相互独立的发光控制信号线；
一行子像素的驱动电路的发光控制信号端对应电连接一条发光控制信号线。
可选地，在本公开实施例中，所述待驱动器件包括；微型发光二极管、有机电致发光二极管以及量子点发光二极管中的至少一种。
本公开实施例还提供了上述显示装置的驱动方法，针对每一行子像素，一帧时间包括：
信号输入阶段，所述电流控制电路响应于所述扫描信号端的信号，输入所述数据信号端的信号；以及所述时长控制电路响应于所述扫描信号端的信号，输入时长控制信号端的信号；
发光阶段，所述电流控制电路根据数据信号端的信号产生驱动所述待驱动器件发光的驱动电流；所述时长控制电路根据所述发光控制信号端、所述基准电压信号端以及输入的时长控制信号端的信号的共同作用，产生输入所述第一晶体管的栅极的发光时长调制信号，以控制所述第一晶体管的导通时长；其中，所述基准电压信号端的电压在预设时长内单调变化，所述时长控制信号端的电压为固定电压且所述固定电压处于所述基准电压信号端单调变化的电压范围内。
附图说明
图1为本公开实施例提供的驱动电路的结构示意图；
图2为本公开实施例提供的驱动电路的一些具体结构示意图；
图3为本公开实施例提供的比较器的具体结构示意图；
图4a为本公开实施例提供的驱动电路的一些电路时序图；
图4b为本公开实施例提供的驱动电路的又一些电路时序图；
图4c为本公开实施例提供的驱动电路的又一些电路时序图；
图5为本公开实施例提供的基准电压信号端的电压与时长控制信号端的电压之间的关系示意图；
图6为本公开实施例提供的驱动电路的又一些具体结构示意图；
图7为本公开实施例提供的显示装置的一些具体结构示意图；
图8为本公开实施例提供的显示装置的一些电路时序图；
图9为本公开实施例提供的显示装置的又一些具体结构示意图；
图10为本公开实施例提供的显示装置的又一些电路时序图；
图11为本公开实施例提供的显示装置的驱动方法的流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元 件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
本公开实施例提供一种驱动电路，如图1所示，可以包括：
电流控制电路10，被配置为根据数据信号端DT的信号向待驱动器件DL提供驱动信号；
第一晶体管M1，电连接于电流控制电路10与待驱动器件DL之间；
时长控制电路20，与第一晶体管M1的栅极电连接，且被配置为根据扫描信号端SC、发光控制信号端EM、时长控制信号端SM以及基准电压信号端VREF的信号的共同作用，向第一晶体管M1的栅极提供发光时长调制信号，以控制第一晶体管M1的导通时长。
本公开实施例提供的驱动电路，通过设置电流控制电路可以产生驱动待驱动器件工作的驱动信号，通过设置时长控制电路可以产生向第一晶体管的栅极提供的发光时长调制信号，以控制第一晶体管的导通时长。从而可以对待驱动器件接收驱动信号的时长进行控制。并且，这样还可以对输入待驱动器件的驱动信号和控制第一晶体管的导通时长进行单独控制，从而可以使控制第一晶体管的导通时长进行独立控制，进而可以使输入待驱动器件驱动信号的时长的调节范围较大。
在具体实施时，待驱动器件可以为发光器件，则驱动信号可以作为驱动发光器件发光的驱动电流。这样可以通过控制第一晶体管的导通时长，控制流入发光器件的驱动电流的时长，以控制发光器件的发光时长。从而可以对发光器件在一帧时间内的发光时长进行控制，由于不同的发光时长可以对应不同的灰阶，进而可以通过对发光时长的控制实现较多灰阶的显示，提高显示效果。当然，在实际应用中，待驱动器件还可以设置为其他器件，在此不 作限定。下面均以待驱动器件为发光器件为例进行说明。
在具体实施时，在本公开实施例中，发光器件的第一端与第一晶体管M1的第二极电连接，发光器件的第二端与第二电源端VSS电连接。其中，发光器件的第一端为其正极，第二端为其负极。并且，发光器件一般为电致发光二极管，例如，发光器件可以包括：微型发光二极管(Micro Light Emitting Diode，Micro LED)、有机电致发光二极管(Organic Light Emitting Diode，OLED)以及量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)中的至少一种。另外，一般发光器件具有发光阈值电压，在发光器件两端的电压大于或等于发光阈值电压时进行发光。在实际应用中，可以根据实际应用环境来设计确定发光器件的具体结构，在此不作限定。
在具体实施时，在本公开实施例中，如图2所示，时长控制电路20可以包括：输入控制子电路21和比较子电路22；
输入控制子电路21被配置为响应于扫描信号端SC的信号，将时长控制信号端SM的信号提供给连接节点N0；以及响应于发光控制信号端EM的信号，将连接节点N0的信号提供给比较子电路22；
比较子电路22被配置为根据输入控制子电路21输出的信号与基准电压信号端VREF的信号，输出发光时长调制信号。
在具体实施时，在本公开实施例中，如图2所示，输入控制子电路21可以包括：第二晶体管M2、第三晶体管M3以及第一电容C1；
第二晶体管M2的栅极与扫描信号端SC电连接，第二晶体管M2的第一极与时长控制信号端SM电连接，第二晶体管M2的第二极与连接节点N0电连接；
第三晶体管M3的栅极与发光控制信号端EM电连接，第三晶体管M3的第一极与连接节点N0电连接，第三晶体管M3的第二极与比较子电路22电连接；
第一电容C1电连接于第一电源端VDD与连接节点N0之间。
在具体实施时，在本公开实施例中，第二晶体管M2在扫描信号端SC的 控制下处于导通状态时，可以将时长控制信号端SM的信号提供给连接节点N0。第三晶体管M3在发光控制信号端EM的控制下处于导通状态时，可以将连接节点N0与比较子电路22电连接，以将连接节点N0的信号提供给比较子电路22。第一电容C1可以存储第一电源端VDD以及输入连接节点N0的信号。
在具体实施时，在本公开实施例中，如图2所示，比较子电路22可以包括：比较器VC；其中，比较器VC的同相输入端PA与输入控制子电路21电连接，比较器VC的反相输入端PB与基准电压信号端VREF电连接，比较器VC的输出端与第一晶体管M1的栅极电连接。具体地，比较器VC的同相输入端PA与输入控制子电路21中的第三晶体管M3的第二极电连接。
在具体实施时，在本公开实施例中，在比较器VC的同相输入端PA的电压大于反相输入端PB的电压时，其输出端输出高电平信号。在比较器VC的同相输入端PA的电压小于反相输入端PB的电压时，其输出端输出低电平信号。
可选地，在具体实施时，在本公开实施例中，如图3所示，比较器VC可以包括：第六晶体管M6、第七晶体管M7、第八晶体管M8、第九晶体管M9、第十晶体管M10、第十一晶体管M11、第十二晶体管M12、第十三晶体管M13、第十四晶体管M14、第十五晶体管M15以及第十六晶体管M16；其中，
第七晶体管M7的第一极与第一电压信号端VGH电连接，第七晶体管M7的栅极和其第二极与第十一晶体管M11的第一极电连接。
第十一晶体管M11的栅极作为比较器VC的同相输入端PA，第十一晶体管M11的第二极与第十四晶体管M14的第一极电连接。
第六晶体管M6的第一极与第一电压信号端VGH电连接，第六晶体管M6的栅极与第七晶体管M7的栅极电连接，第六晶体管M6的第二极与第十二晶体管M12的第一极电连接。
第十二晶体管M12的栅极作为比较器VC的反相输入端PB，第十二晶体 管M12的第二极与第十四晶体管M14的第一极电连接。
第十四晶体管M14的栅极分别与第十五晶体管M15的栅极以及第十三晶体管M13的栅极电连接，第十四晶体管M14的第二极与第二电压信号端VGL电连接。
第八晶体管M8的第一极与第一电压信号端VGH电连接，第八晶体管M8的栅极和其第二极分别与第十三晶体管M13的栅极和其第一极电连接。
第十三晶体管M13的第二极与第二电压信号端VGL电连接。
第九晶体管M9的栅极与第十二晶体管M12的第一极电连接，第九晶体管M9的第一极与第一电压信号端VGH电连接，第九晶体管M9的第二极分别与第十五晶体管M15的第一极、第十晶体管M10的栅极以及第十六晶体管M16的栅极电连接。
第十五晶体管M15的第二极与第二电压信号端VGL电连接。
第十晶体管M10的第一极与第一电压信号端VGH电连接，第十晶体管M10的第二极与第十六晶体管M16的第一极电连接，作为比较器VC的输出端VC-OUT。
第十六晶体管M16的第二极与第二电压信号端VGL电连接。
在具体实施时，第六晶体管至第十晶体管M6～M10可以设置为P型晶体管。第十一晶体管至第十六晶体管M11～M16可以设置为N型晶体管。当然，在实际应用中，可以根据实际应用环境来设置上述晶体管的具体类型和结构，在此不作限定。
在具体实施时，第一电压信号端VGH的电压大于第二电压信号端VGL的电压。例如可以使第一电压信号端VGH与第一电源端VDD为同一信号端。当然，在实际应用中，可以根据实际应用环境来设计确定第一电压信号端VGH的电压与第二电压信号端VGL的电压，具体在此不作限定。
当然，在实际应用中，比较器VC的结构和工作原理还可以与相关技术中的其他比较器基本相同，在此不作赘述。
在具体实施时，在本公开实施例中，如图2所示，电流控制电路10可以 包括：驱动晶体管M0、第四晶体管M4以及第二电容C2；
第四晶体管M4的栅极与扫描信号端SC电连接，第四晶体管M4的第一极与数据信号端DA电连接，第四晶体管M4的第二极与驱动晶体管M0的栅极电连接；
驱动晶体管M0的第一极与第一电源端VDD电连接，驱动晶体管M0的第二极与第一晶体管M1的第一极电连接；
第二电容C2电连接于驱动晶体管M0的栅极与第一电源端VDD之间。
在具体实施时，在本公开实施例中，第四晶体管M4在扫描信号端SC的控制下处于导通状态时，可以将数据信号端DA的信号提供给驱动晶体管M0的栅极。第二电容C2可以存储驱动晶体管M0的栅极与第一电源端VDD的信号。这样可以使像素电路的结构较简单，从而降低占用空间，降低工艺复杂度。
在具体实施时，在本公开实施例中，如图2所示，驱动晶体管M0可以为P型晶体管；其中，驱动晶体管M0的第一极为其源极，驱动晶体管M0的第二极为其漏极，并且该驱动晶体管M0处于饱和状态时，电流由驱动晶体管M0的源极流向其漏极。
当然，在具体实施时，在本公开实施例中，驱动晶体管也可以为N型晶体管；其中，驱动晶体管的第一极为其漏极，驱动晶体管的第二极为其源极，并且该驱动晶体管处于饱和状态时，电流由驱动晶体管的漏极流向其源极。
在具体实施时，在本公开实施例中，电流控制电路也可以为能够补偿驱动晶体管M0的阈值电压V th的像素补偿电路。该像素补偿电路的结构和工作原理可以与相关技术中的基本相同，在此不作赘述。
以上仅是举例说明本公开实施例提供的驱动电路中的各电路的具体结构，在具体实施时，上述电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，这些均在本公开的保护范围之内，具体在此不作限定。
可选地，为了降低制备工艺，在具体实施时，在本公开实施例中，如图2 所示，第一至第四晶体管M1～M4可以均为P型晶体管。当然，第一至第四晶体管M1～M4也可以均为N型晶体管，这也可以根据实际应用环境来设计确定，在此不作限定。
进一步的，在具体实施时，在本公开实施例中，P型晶体管在高电平信号作用下截止，在低电平信号作用下导通。N型晶体管在高电平信号作用下导通，在低电平信号作用下截止。
需要说明的是，本公开上述实施例中提到的晶体管可以是薄膜晶体管(Thin Film Transistor，TFT)，也可以是金属氧化物半导体场效应管(Metal Oxide Scmiconductor，MOS)，在此不作限定。
在具体实施中，可以根据晶体管的类型以及其栅极的信号，将晶体管的第一极作为其源极，第二极作为其漏极；或者，反之，将晶体管的第一极作为其漏极，第二极作为其源极，这可以根据实际应用环境来设计确定，具体在此不做具体区分。
在具体实施时，在本公开实施例中，第一电源端的电压V dd一般为正值，第二电源端的电压V ss一般接地或为负值。在实际应用中，第一电源端的电压V dd和第二电源端的电压V ss的具体数值可以根据实际应用环境来设计确定，在此不作限定。
在具体实施时，在本公开实施例中，基准电压信号端VREF的电压V ref可以在预设时长内单调变化。示例性地，如图4a所示，基准电压信号端VREF的电压V ref可以在预设时长内由第一电压V 01增加至第二电压V 02。示例性地，如图4b所示，基准电压信号端VREF的电压V ref可以在第一个预设时长内由第一电压V 01增加至第二电压V 02，并在第二个预设时长内由第二电压V 02降低至第一电压V 01。其中，第一个预设时长与第二个预设时长连续出现。示例性地，如图4b所示，基准电压信号端VREF的电压V ref可以在第一个预设时长内由第一电压V 01增加至第二电压V 02，之后由第二电压V 02跳至第一电压V 01，并在第二个预设时长内由第一电压V 01增加至第二电压V 02。其中，第一个预设时长与第二个预设时长连续出现。需要说明的是，第一个预设时长与 第二个预设时长可以相同，也可以不同，在此不作限定。
在具体实施时，在本公开实施例中，基准电压信号端VREF的电压V ref可以在预设时长内由第二电压V 02降低至第一电压V 01。当然，在实际应用中，基准电压信号端VREF的电压变化情况可以根据实际应用环境来设计确定，在此不作限定。
在具体实施时，在本公开实施例中，时长控制信号端SM的电压可以为固定电压且时长控制信号端SM的电压处于基准电压信号端VREF单调变化的电压范围内。示例性地，时长控制信号端SM的电压可以为大于或等于第一电压V 01且小于或等于第二电压V 02的固定电压。例如，时长控制信号端SM的电压V 03可以为大于第一电压V 01且小于第二电压V 02。时长控制信号端SM的电压可以等于第一电压V 01。时长控制信号端SM的电压也可以为等于第二电压V 02。在实际应用中，第一电压V 01、第二电压V 02以及时长控制信号端SM的电压的具体数值需要根据实际应用环境来设计确定，在此不作限定。下面以图2所示的驱动电路的结构为例，结合图4a所示的电路时序图对本公开实施例提供的驱动电路的工作过程作以描述。
其中，主要选取图4a所示的电路时序图中的信号输入子阶段T11、发光阶段T20。需要说明的是，基准电压信号端VREF的电压在预设时长内可以由第一电压V 01增加至第二电压V 02，时长控制信号端SM的电压V 03可以为大于第一电压V 01且小于第二电压V 02的固定电压。
并且，驱动电路在一帧时间内的工作过程可以具有：信号输入子阶段T11和发光阶段T20。其中，发光阶段T20可以包括：调制子阶段T21和发光子阶段T22。
在信号输入子阶段T11中，扫描信号端SC为低电平信号，可以控制第二晶体管M2和第四晶体管M4导通。发光控制信号端EM为高电平信号，可以控制第三晶体管M3截止。导通的第四晶体管M4可以将数据信号端DA的信号提供给驱动晶体管M0的栅极，并通过第二电容C2进行存储。由于驱动晶体管M0的栅极电压为数据信号端DA的信号的电压V DA，源极电压为V dd， 因此驱动晶体管M0可以产生驱动电流I，I＝K(V sg-|V th|) 2＝K(V dd-V DA-|V th|) 2；其中，V sg为驱动晶体管M0的源栅电压；K为结构参数，相同结构中此数值相对稳定，可以算作常量。导通的第二晶体管M2可以将时长控制信号端SM的信号提供给连接节点N0，使连接节点N0的信号的电压为V 03，并通过第一电容C1进行存储。
在调制子阶段T21，扫描信号端SC为高电平信号，可以控制第二晶体管M2和第四晶体管M4截止。发光控制信号端EM为低电平信号，可以控制第三晶体管M3导通。导通的第三晶体管M3可以将输入连接节点N0的信号提供给比较器AC的同相输入端PA，使比较器AC的同相输入端PA的电压为V 03。由于比较器AC的反相输入端PB的电压由V 01增加为V 03，因此同相输入端PA的电压大于反相输入端PB的电压，从而使得比较器AC的输出端输出高电平信号。由于比较器AC输出高电平信号，可以控制第一晶体管M1截止，从而可以使发光器件DL在调制子阶段T21中停止发光。
在发光子阶段T22，扫描信号端SC为高电平信号，可以控制第二晶体管M2和第四晶体管M4截止。发光控制信号端EM为低电平信号，可以控制第三晶体管M3导通。导通的第三晶体管M3可以将输入连接节点N0的信号提供给比较器AC的同相输入端PA，使比较器AC的同相输入端PA的电压为V 03。由于比较器AC的反相输入端PB的电压由V 03增加为V 02，因此同相输入端PA的电压小于反相输入端PB的电压，从而使得比较器AC的输出端输出低电平信号。由于比较器AC输出低电平信号，可以控制第一晶体管M1导通，从而可以将驱动晶体管M0产生的驱动电流I提供给发光器件DL，以驱动发光器件DL在发光子阶段T22发光。
通过调制子阶段T21和发光子阶段T22的工作过程可知，可以通过设置时长控制信号端SM的电压V 03的大小，来控制调制子阶段T21的维持时长和发光子阶段T22的维持时长。例如，结合图5所示，在将时长控制信号端SM的电压设置为V 03-1时，发光子阶段T22的维持时长为t22-1且调制子阶段T21的维持时长为t21-1。在将时长控制信号端SM的电压设置为V 03-2时，发光子 阶段T22的维持时长为t22-2且调制子阶段T21的维持时长为t21-2。其中，V 03-1<V 03-2。因此，可以看出当将时长控制信号端SM的电压增加时，可以使发光子阶段T22的维持时长降低。反之，当将时长控制信号端SM的电压降低时，可以使发光子阶段T22的维持时长增加。因此，在实际应用中，可以通过调控时长控制信号端SM的电压大小，以控制发光器件DL的发光时长，进而可以通过对发光时长的控制实现较多灰阶的显示，提高显示效果。
下面以图2所示的驱动电路的结构为例，结合图4b所示的电路时序图对本公开实施例提供的驱动电路的工作过程作以描述。下面仅说明与上述实施例的区别之处，其相同之处在此不作赘述。
发光阶段T20可以包括：调制子阶段T21、发光子阶段T22以及调制子阶段T23。其中，调制子阶段T21的工作过程可以参见上述图4a实施方式中的工作过程，在此不作赘述。
在发光子阶段T22中的前时间段，扫描信号端SC为高电平信号，可以控制第二晶体管M2和第四晶体管M4截止。发光控制信号端EM为低电平信号，可以控制第三晶体管M3导通。导通的第三晶体管M3可以将输入连接节点N0的信号提供给比较器AC的同相输入端PA，使比较器AC的同相输入端PA的电压为V 03。由于比较器AC的反相输入端PB的电压由V 03增加为V 02，因此同相输入端PA的电压小于反相输入端PB的电压，从而使得比较器AC的输出端输出低电平信号。由于比较器AC输出低电平信号，可以控制第一晶体管M1导通，从而可以将驱动晶体管M0产生的驱动电流I提供给发光器件DL，以驱动发光器件DL发光。
在发光子阶段T22中的后时间段，扫描信号端SC为高电平信号，可以控制第二晶体管M2和第四晶体管M4截止。发光控制信号端EM为低电平信号，可以控制第三晶体管M3导通。导通的第三晶体管M3可以将输入连接节点N0的信号提供给比较器AC的同相输入端PA，使比较器AC的同相输入端PA的电压为V 03。由于比较器AC的反相输入端PB的电压由V 02降低为V 02，因此同相输入端PA的电压小于反相输入端PB的电压，从而使得比较器AC的 输出端输出低电平信号。由于比较器AC输出低电平信号，可以控制第一晶体管M1导通，从而可以将驱动晶体管M0产生的驱动电流I提供给发光器件DL，以驱动发光器件DL发光。
在调制子阶段T23，扫描信号端SC为高电平信号，可以控制第二晶体管M2和第四晶体管M4截止。发光控制信号端EM为低电平信号，可以控制第三晶体管M3导通。导通的第三晶体管M3可以将输入连接节点N0的信号提供给比较器AC的同相输入端PA，使比较器AC的同相输入端PA的电压为V 03。由于比较器AC的反相输入端PB的电压由V 03降低为V 01，因此同相输入端PA的电压大于反相输入端PB的电压，从而使得比较器AC的输出端输出高电平信号。由于比较器AC输出高电平信号，可以控制第一晶体管M1截止，从而可以使发光器件DL在调制子阶段T23中停止发光。
下面以图2所示的驱动电路的结构为例，结合图4c所示的电路时序图对本公开实施例提供的驱动电路的工作过程作以描述。下面仅说明与上述实施例的区别之处，其相同之处在此不作赘述。
发光阶段T20可以包括：调制子阶段T21、发光子阶段T22、调制子阶段T23以及发光子阶段T22。其中，调制子阶段T21和发光子阶段T22的工作过程可以参见上述图4a实施方式中调制子阶段T21和发光子阶段T22的工作过程。并且，调制子阶段T23的工作过程可以参见上述图4a实施方式中调制子阶段T21的工作过程。发光子阶段T22的工作过程可以参见上述图4a实施方式中发光子阶段T22的工作过程，在此不作赘述。
通过上述实施例可以看出，还可以通过调节基准电压信号端VREF的电压以调节发光时长。
本公开实施例提供的另一些驱动电路的结构示意图如图6所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在具体实施时，在本公开实施例中，如图6所示，驱动电路还包括：第五晶体管M5；其中，第一晶体管M1通过第五晶体管M5与待驱动器件DL 电连接；其中，第五晶体管M5的栅极与发光控制信号端EM电连接。
在信号输入子阶段T11中驱动晶体管M0会产生驱动电流，由于晶体管存在漏电流现象，因此第一晶体管M1可能会存在漏电流情况，从而导致驱动晶体管M0产生的驱动电流通过第一晶体管M1存在的漏电流情况流入发光器件中，进而使发光器件发光，降低显示效果。本公开实施例通过设置第五晶体管M5，并控制第五晶体管M5在信号输入子阶段T11中截止，从而可以改善由于漏电流现象导致的降低显示效果的问题。并且，通过控制第五晶体管M5在发光阶段T20中导通，从而可以将第一晶体管M1与发光器件导通，进而在第一晶体管M1导通时可以将驱动晶体管M0产生的驱动电流输入发光器件中，驱动发光器件发光。
在具体实施时，在本公开实施例中，第五晶体管M5也可以设置为P型晶体管或N型晶体管，在此不作限定。
图6所示的驱动电路的结构对应的电路时序图也可以如图4a所示，其具体工作过程可以参见上述实施例，具体在此不作赘述。
基于同一发明构思，本公开实施例还提供了一种显示装置，如图7所示，可以包括：衬底基板100；位于衬底基板一侧的多个子像素110。其中，多个子像素中的至少一个可以包括：发光器件111和上述驱动电路112；其中，发光器件111作为待驱动器件DL。其中，驱动电路112的结构和工作原理可以参见上述实施例，在此不作赘述。
示例性地，在具体实施时，在本公开实施例中，可以对各子像素中的驱动电路的基准电压信号端加载同一基准电压信号。这样通过使显示装置中的所有驱动电路112的基准电压信号端VREF采用同一个信号，可以使降低向基准电压信号端VREF输出信号的电路的复杂性，便于控制，以及降低信号线的数量。
示例性地，在具体实施时，在本公开实施例中，结合图2与图7所示，显示装置还可以包括：位于衬底基板100上的一个基准电压输入端子120；基准电压输入端子120可以位于衬底基板100的绑定区BG其中，各驱动电路 112的基准电压信号端VREF均电连接基准电压输入端子120。这样通过一个基准电压输入端子120为显示装置中的所有驱动电路112的基准电压信号端VREF输入同一个信号，可以降低基准电压输入端子120的占用空间。
在具体实施时，在本公开实施例中，可以对各子像素中的驱动电路的发光控制信号端加载同一发光控制信号。这样通过使显示装置中的所有驱动电路112的发光控制信号端EM采用同一个信号，可以使降低向发光控制信号端EM输出信号的电路的复杂性，便于控制，以及降低信号线的数量。
示例性地，在具体实施时，在本公开实施例中，结合图2与图7所示，显示装置还可以包括：多条发光控制信号线130以及位于衬底基板100的绑定区BG的一个发光控制输入端子140。其中，一行子像素110的驱动电路111的发光控制信号端EM对应电连接一条发光控制信号线130；各发光控制信号线140均电连接发光控制输入端子140。这样通过一个发光控制输入端子140为显示装置中的所有驱动电路112的发光控制信号端EM输入同一个信号，可以降低发光控制输入端子140的占用空间。
在具体实施时，在本公开实施例中，显示装置还可以包括：多条相互独立的栅线、多条相互独立的数据线以及多条相互独立的时长控制信号线。其中，一行子像素的驱动电路的扫描信号端对应电连接一条栅线，一列子像素的驱动电路的数据信号端对应电连接一条数据线，一列子像素的驱动电路的时长控制信号端对应电连接一条时长控制信号线。
在具体实施时，在本公开实施例中，栅线、数据线、时长控制信号线、发光控制信号线以及与基准电压输入端子电连接的信号分别相互绝缘设置。
在具体实施时，在本公开实施例中，各子像素可以位于衬底基板的显示区，以实现显示效果。例如，一般显示装置包括多个像素单元，该多个像素单元中的至少一个可以包括多个子像素。示例性地，像素单元可以包括红色子像素、绿色子像素以及蓝色子像素，这样可以通过红绿蓝混色实现显示。像素单元也可以包括红色子像素、绿色子像素、蓝色子像素以及白色子像素，这样可以通过红绿蓝白混色实现显示。
在具体实施时，在本公开实施例中，如图7与图9所示，衬底基板还设置有绑定区BG。该绑定区BG中可以设置有用于进行绑定的端子。在实际应用中，可以将基准电压输入端子120和发光控制输入端子140设置在绑定区BG。并且，由于仅设置一个基准电压输入端子120和一个发光控制输入端子140，这样可以降低占用绑定区BG的占用空间。
基于同一发明构思，本公开实施例还提供了一种显示装置驱动方法，如图11所示，针对每一行子像素，一帧时间包括：
S101、信号输入阶段，电流控制电路响应于扫描信号端的信号，输入数据信号端的信号；以及时长控制电路响应于扫描信号端的信号，输入时长控制信号端的信号；
S102、发光阶段，电流控制电路根据数据信号端的信号产生驱动待驱动器件发光的驱动信号；时长控制电路根据发光控制信号端、基准电压信号端以及输入的时长控制信号端的信号的共同作用，向第一晶体管的栅极提供发光时长调制信号，以控制第一晶体管的导通时长；其中，基准电压信号端的电压在预设时长内单调变化，时长控制信号端的电压为固定电压且时长控制信号端的电压处于基准电压信号端单调变化的电压范围内。
下面以图6与图7所示的结构为例，结合图8所示的电路时序图对本公开实施例提供的显示装置的工作过程作以描述。其中，主要选取图8所示的电路时序图中的信号输入阶段T10、发光阶段T20。需要说明的是，基准电压信号端VREF的电压在预设时长内可以由第一电压V 01增加至第二电压V 02，时长控制信号端SM的电压可以为大于第一电压V 01且小于第二电压V 02的固定电压V 03。
显示装置在一帧时间内的工作阶段可以具有信号输入阶段T10和发光阶段T20。其中，信号输入阶段T10可以包括多个信号输入子阶段T11-n(1≤n≤N，且N和n均为整数，N代表显示装置中子像素的总行数)。发光阶段T20可以包括：调制子阶段T21和发光子阶段T22。
在信号输入阶段T10中，逐行对每一行子像素中的驱动电路的扫描信号 端加载信号，以逐行驱动每一行子像素。其中，以第一行至第三行子像素为例进行说明。SC-1代表第一行子像素的驱动电路的扫描信号端SC接收到的信号，SC-2代表第二行子像素的驱动电路的扫描信号端SC接收到的信号，SC-3代表第三行子像素的驱动电路的扫描信号端SC接收到的信号。da代表一条数据线上传输的信号，sm代表一条时长控制信号线上传输的信号。
具体地，在信号输入子阶段T11-1，驱动第一行子像素。其中，第一行子像素中驱动电路的扫描信号端SC为低电平信号，可以控制第二晶体管M2和第四晶体管M4导通。发光控制信号端EM为高电平信号，可以控制第三晶体管M3和第五晶体管M5截止。导通的第四晶体管M4可以将通过数据线传输到数据信号端DA的信号da提供给驱动晶体管M0的栅极，并通过第二电容C2进行存储。由于驱动晶体管M0的栅极电压为数据信号端DA的信号的电压V DA-1，源极电压为V dd，因此驱动晶体管M0可以产生驱动电流I，I＝K(V sg-|V th|) 2＝K(V dd-V DA-1-|V th|) 2；其中，V sg为驱动晶体管M0的源栅电压；K为结构参数，相同结构中此数值相对稳定，可以算作常量。导通的第二晶体管M2可以将时长控制信号线传输到时长控制信号端SM的信号sm提供给连接节点N0，使连接节点N0的信号的电压为V 03-1，并通过第一电容C1进行存储。
在信号输入子阶段T11-2，驱动第二行子像素。其中，第二行子像素中驱动电路的扫描信号端SC为低电平信号，可以控制第二晶体管M2和第四晶体管M4导通。发光控制信号端EM为高电平信号，可以控制第三晶体管M3和第五晶体管M5截止。导通的第四晶体管M4可以将通过数据线传输到数据信号端DA的信号da提供给驱动晶体管M0的栅极，并通过第二电容C2进行存储。由于驱动晶体管M0的栅极电压为数据信号端DA的信号的电压V DA-2，源极电压为V dd，因此驱动晶体管M0可以产生驱动电流I，I＝K(V sg-|V th|) 2＝K(V dd-V DA-2-|V th|) 2；其中，V sg为驱动晶体管M0的源栅电压；K为结构参数，相同结构中此数值相对稳定，可以算作常量。导通的第二晶体管M2可以将时长控制信号线传输到时长控制信号端SM的信号sm提供给 连接节点N0，使连接节点N0的信号的电压为V 03-2，并通过第一电容C1进行存储。
在信号输入子阶段T11-3，驱动第三行子像素。其中，第三行子像素中驱动电路的扫描信号端SC为低电平信号，可以控制第二晶体管M2和第四晶体管M4导通。发光控制信号端EM为高电平信号，可以控制第三晶体管M3和第五晶体管M5截止。导通的第四晶体管M4可以将通过数据线传输到数据信号端DA的信号da提供给驱动晶体管M0的栅极，并通过第二电容C2进行存储。由于驱动晶体管M0的栅极电压为数据信号端DA的信号的电压V DA-3，源极电压为V dd，因此驱动晶体管M0可以产生驱动电流I，I＝K(V sg-|V th|) 2＝K(V dd-V DA-3-|V th|) 2；其中，V sg为驱动晶体管M0的源栅电压；K为结构参数，相同结构中此数值相对稳定，可以算作常量。导通的第二晶体管M2可以将时长控制信号线传输到时长控制信号端SM的信号sm提供给连接节点N0，使连接节点N0的信号的电压为V 03-3，并通过第一电容C1进行存储。
之后，依次驱动第四行子像素至最后一行子像素，其工作过程可以依次类推，在此不作赘述。
之后进入发光阶段T20，显示装置中的每一个驱动电路的扫描信号端SC为高电平信号，可以控制第二晶体管M2和第四晶体管M4截止。显示装置中的每一个驱动电路的发光控制信号端EM为低电平信号，可以控制第三晶体管M3和第五晶体管M5导通。导通的第三晶体管M3可以将输入连接节点N0的信号提供给比较器AC的同相输入端PA。
针对显示装置的第一行中一个子像素内的驱动电路，发光阶段T20可以包括调制子阶段T21-1和发光子阶段T22-1。其中，在调制子阶段T21-1中，由于导通的第三晶体管M3可以将输入连接节点N0的信号提供给比较器AC的同相输入端PA，使比较器AC的同相输入端PA的电压为V 03-1。由于比较器AC的反相输入端PB的电压由V01增加为V03-1，因此同相输入端PA的电压大于反相输入端PB的电压，从而使得比较器AC的输出端输出高电平信 号。由于比较器AC输出高电平信号，可以控制第一晶体管M1截止，从而可以使发光器件DL在调制子阶段T21-1中停止发光。
在发光子阶段T22-1中，由于比较器AC的反相输入端PB的电压由V 03-1增加为V 02，因此同相输入端PA的电压小于反相输入端PB的电压，从而使得比较器AC的输出端输出低电平信号。由于比较器AC输出低电平信号，可以控制第一晶体管M1导通，从而可以将驱动晶体管M0产生的驱动电流I提供给发光器件DL，以驱动发光器件DL在发光子阶段T22-1发光。
针对显示装置的第二行中一个子像素内的驱动电路，发光阶段T20可以包括调制子阶段T21-2和发光子阶段T22-2。其中，在调制子阶段T21-2中，由于导通的第三晶体管M3可以将输入连接节点N0的信号提供给比较器AC的同相输入端PA，使比较器AC的同相输入端PA的电压为V 03-2。由于比较器AC的反相输入端PB的电压由V01增加为V 03-2，因此同相输入端PA的电压大于反相输入端PB的电压，从而使得比较器AC的输出端输出高电平信号。由于比较器AC输出高电平信号，可以控制第一晶体管M1截止，从而可以使发光器件DL在调制子阶段T21-2中停止发光。
在发光子阶段T22-1中，由于比较器AC的反相输入端PB的电压由V 03-2增加为V 02，因此同相输入端PA的电压小于反相输入端PB的电压，从而使得比较器AC的输出端输出低电平信号。由于比较器AC输出低电平信号，可以控制第一晶体管M1导通，从而可以将驱动晶体管M0产生的驱动电流I提供给发光器件DL，以驱动发光器件DL在发光子阶段T22-2发光。
针对显示装置的第三行中一个子像素内的驱动电路，发光阶段T20可以包括调制子阶段T21-3和发光子阶段T22-3。其中，在调制子阶段T21-3中，由于导通的第三晶体管M3可以将输入连接节点N0的信号提供给比较器AC的同相输入端PA，使比较器AC的同相输入端PA的电压为V 03-3。由于比较器AC的反相输入端PB的电压由V01增加为V 03-3，因此同相输入端PA的电压大于反相输入端PB的电压，从而使得比较器AC的输出端输出高电平信号。由于比较器AC输出高电平信号，可以控制第一晶体管M1截止，从而可以使 发光器件DL在调制子阶段T21-3中停止发光。
在发光子阶段T22-1中，由于比较器AC的反相输入端PB的电压由V 03-3增加为V 02，因此同相输入端PA的电压小于反相输入端PB的电压，从而使得比较器AC的输出端输出低电平信号。由于比较器AC输出低电平信号，可以控制第一晶体管M1导通，从而可以将驱动晶体管M0产生的驱动电流I提供给发光器件DL，以驱动发光器件DL在发光子阶段T22-3发光。
根据上述可知，通过设置时长控制信号端SM的电压的大小，可以调节发光器件DL的发光时长，从而可以通过对发光时长的控制实现较多灰阶的显示，提高显示效果。
需要说明的是，基于上述实施例，预设时长可以设置为发光阶段T20的维持时长。当然，在实际应用中，预设时长也可以设置为其他时间，在此不作限定。
可以理解的是，在一些实施例中，基准电压信号端VREF的电压Vref也可以在预设时长内振荡变化，时长控制信号端的电压为固定电压且时长控制信号端的电压处于基准电压信号端所能提供的电压范围内。
本公开实施例提供的另一些显示装置的结构示意图如图9所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在具体实施时，在本公开实施例中，结合图2、图6以及图9所示，显示装置还可以包括：多条相互独立的发光控制信号线150；其中，一行子像素的驱动电路112的发光控制信号端EM对应电连接一条发光控制信号线150。这样可以通过对每一条发光控制信号线150输入不同的信号，以逐行控制第三晶体管M3和第五晶体管M5导通。当然，也可以通过对每一条发光控制信号线150输入相同的信号，以控制第三晶体管M3和第五晶体管M5同时导通。
下面以图6与图9所示的结构为例，结合图10所示的电路时序图对本公开实施例提供的显示装置的工作过程作以描述。其中，主要选取图9所示的电路时序图中的信号输入阶段T10、发光阶段T20。需要说明的是，基准电压 信号端VREF的电压在预设时长内可以由第一电压V 01增加至第二电压V 02，时长控制信号端SM的电压可以为大于第一电压V 01且小于第二电压V 02的固定电压V 03。
显示装置在一帧时间内的工作阶段可以具有信号输入阶段T10和发光阶段T20。其中，信号输入阶段T10可以包括多个信号输入子阶段T11-n(1≤n≤N，且N和n均为整数，N代表显示装置中子像素的总行数)。发光阶段T20可以包括：调制子阶段T21和发光子阶段T22。
在信号输入阶段T10中，逐行对每一行子像素中的驱动电路的扫描信号端加载信号，以逐行驱动每一行子像素。其中，以第一行至第三行子像素为例进行说明。SC-1代表第一行子像素的驱动电路的扫描信号端SC接收到的信号，EM-1代表第一行子像素的驱动电路的发光控制信号端EM接收到的信号。SC-2代表第二行子像素的驱动电路的扫描信号端SC接收到的信号，EM-2代表第二行子像素的驱动电路的发光控制信号端EM接收到的信号。SC-3代表第三行子像素的驱动电路的扫描信号端SC接收到的信号，EM-3代表第三行子像素的驱动电路的发光控制信号端EM接收到的信号。da代表一条数据线上传输的信号，sm代表一条时长控制信号线上传输的信号。
具体地，在信号输入子阶段T11-1，驱动第一行子像素。其中，第一行子像素中驱动电路的扫描信号端SC为低电平信号，可以控制第二晶体管M2和第四晶体管M4导通。发光控制信号端EM为高电平信号，可以控制第三晶体管M3和第五晶体管M5截止。导通的第四晶体管M4可以将通过数据线传输到数据信号端DA的信号da提供给驱动晶体管M0的栅极，并通过第二电容C2进行存储。由于驱动晶体管M0的栅极电压为数据信号端DA的信号的电压V DA-1，源极电压为V dd，因此驱动晶体管M0可以产生驱动电流I，I＝K(V sg-|V th|) 2＝K(V dd-V DA-1-|V th|) 2；其中，V sg为驱动晶体管M0的源栅电压；K为结构参数，相同结构中此数值相对稳定，可以算作常量。导通的第二晶体管M2可以将时长控制信号线传输到时长控制信号端SM的信号sm提供给连接节点N0，使连接节点N0的信号的电压为V 03-1，并通过第一电容C1进 行存储。
之后，第一行子像素中驱动电路的扫描信号端SC为高电平信号，可以控制第二晶体管M2和第四晶体管M4截止。发光控制信号端EM为低电平信号，可以控制第三晶体管M3和第五晶体管M5导通。
在信号输入子阶段T11-2，驱动第二行子像素。其中，第二行子像素中驱动电路的扫描信号端SC为低电平信号，可以控制第二晶体管M2和第四晶体管M4导通。发光控制信号端EM为高电平信号，可以控制第三晶体管M3和第五晶体管M5截止。导通的第四晶体管M4可以将通过数据线传输到数据信号端DA的信号da提供给驱动晶体管M0的栅极，并通过第二电容C2进行存储。由于驱动晶体管M0的栅极电压为数据信号端DA的信号的电压V DA-2，源极电压为V dd，因此驱动晶体管M0可以产生驱动电流I，I＝K(V sg-|V th|) 2＝K(V dd-V DA-2-|V th|) 2；其中，V sg为驱动晶体管M0的源栅电压；K为结构参数，相同结构中此数值相对稳定，可以算作常量。导通的第二晶体管M2可以将时长控制信号线传输到时长控制信号端SM的信号sm提供给连接节点N0，使连接节点N0的信号的电压为V 03-2，并通过第一电容C1进行存储。
之后，第二行子像素中驱动电路的扫描信号端SC为高电平信号，可以控制第二晶体管M2和第四晶体管M4截止。发光控制信号端EM为低电平信号，可以控制第三晶体管M3和第五晶体管M5导通。
在信号输入子阶段T11-3，驱动第三行子像素。其中，第三行子像素中驱动电路的扫描信号端SC为低电平信号，可以控制第二晶体管M2和第四晶体管M4导通。发光控制信号端EM为高电平信号，可以控制第三晶体管M3和第五晶体管M5截止。导通的第四晶体管M4可以将通过数据线传输到数据信号端DA的信号da提供给驱动晶体管M0的栅极，并通过第二电容C2进行存储。由于驱动晶体管M0的栅极电压为数据信号端DA的信号的电压V DA-3，源极电压为V dd，因此驱动晶体管M0可以产生驱动电流I，I＝K(V sg-|V th|) 2＝K(V dd-V DA-3-|V th|) 2；其中，V sg为驱动晶体管M0的源栅电压； K为结构参数，相同结构中此数值相对稳定，可以算作常量。导通的第二晶体管M2可以将时长控制信号线传输到时长控制信号端SM的信号sm提供给连接节点N0，使连接节点N0的信号的电压为V 03-3，并通过第一电容C1进行存储。
之后，第三行子像素中驱动电路的扫描信号端SC为高电平信号，可以控制第二晶体管M2和第四晶体管M4截止。发光控制信号端EM为低电平信号，可以控制第三晶体管M3和第五晶体管M5导通。
之后，依次驱动第四行子像素至最后一行子像素，其工作过程可以依次类推，在此不作赘述。
之后进入发光阶段T20，显示装置中的每一个驱动电路的扫描信号端SC为高电平信号，可以控制第二晶体管M2和第四晶体管M4截止。显示装置中的每一个驱动电路的发光控制信号端EM为低电平信号，可以控制第三晶体管M3和第五晶体管M5导通。导通的第三晶体管M3可以将输入连接节点N0的信号提供给比较器AC的同相输入端PA。
针对显示装置的第一行中一个子像素内的驱动电路，发光阶段T20可以包括调制子阶段T21-1和发光子阶段T22-1。其中，在调制子阶段T21-1中，由于导通的第三晶体管M3可以将输入连接节点N0的信号提供给比较器AC的同相输入端PA，使比较器AC的同相输入端PA的电压为V 03-1。由于比较器AC的反相输入端PB的电压由V01增加为V 03-1，因此同相输入端PA的电压大于反相输入端PB的电压，从而使得比较器AC的输出端输出高电平信号。由于比较器AC输出高电平信号，可以控制第一晶体管M1截止，从而可以使发光器件DL在调制子阶段T21-1中停止发光。
在发光子阶段T22-1中，由于比较器AC的反相输入端PB的电压由V 03-1增加为V 02，因此同相输入端PA的电压小于反相输入端PB的电压，从而使得比较器AC的输出端输出低电平信号。由于比较器AC输出低电平信号，可以控制第一晶体管M1导通，从而可以将驱动晶体管M0产生的驱动电流I提供给发光器件DL，以驱动发光器件DL在发光子阶段T22-1发光。
针对显示装置的第二行中一个子像素内的驱动电路，发光阶段T20可以包括调制子阶段T21-2和发光子阶段T22-2。其中，在调制子阶段T21-2中，由于导通的第三晶体管M3可以将输入连接节点N0的信号提供给比较器AC的同相输入端PA，使比较器AC的同相输入端PA的电压为V 03-2。由于比较器AC的反相输入端PB的电压由V 01增加为V 03-2，因此同相输入端PA的电压大于反相输入端PB的电压，从而使得比较器AC的输出端输出高电平信号。由于比较器AC输出高电平信号，可以控制第一晶体管M1截止，从而可以使发光器件DL在调制子阶段T21-2中停止发光。
在发光子阶段T22-1中，由于比较器AC的反相输入端PB的电压由V 03-2增加为V 02，因此同相输入端PA的电压小于反相输入端PB的电压，从而使得比较器AC的输出端输出低电平信号。由于比较器AC输出低电平信号，可以控制第一晶体管M1导通，从而可以将驱动晶体管M0产生的驱动电流I提供给发光器件DL，以驱动发光器件DL在发光子阶段T22-2发光。
针对显示装置的第三行中一个子像素内的驱动电路，发光阶段T20可以包括调制子阶段T21-3和发光子阶段T22-3。其中，在调制子阶段T21-3中，由于导通的第三晶体管M3可以将输入连接节点N0的信号提供给比较器AC的同相输入端PA，使比较器AC的同相输入端PA的电压为V 03-3。由于比较器AC的反相输入端PB的电压由V 01增加为V 03-3，因此同相输入端PA的电压大于反相输入端PB的电压，从而使得比较器AC的输出端输出高电平信号。由于比较器AC输出高电平信号，可以控制第一晶体管M1截止，从而可以使发光器件DL在调制子阶段T21-3中停止发光。
在发光子阶段T22-1中，由于比较器AC的反相输入端PB的电压由V 03-3增加为V 02，因此同相输入端PA的电压小于反相输入端PB的电压，从而使得比较器AC的输出端输出低电平信号。由于比较器AC输出低电平信号，可以控制第一晶体管M1导通，从而可以将驱动晶体管M0产生的驱动电流I提供给发光器件DL，以驱动发光器件DL在发光子阶段T22-3发光。
根据上述可知，通过设置时长控制信号端SM的电压的大小，可以调节 发光器件DL的发光时长，从而可以通过对发光时长的控制实现较多灰阶的显示，提高显示效果。
在具体实施时，在本公开实施例中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
本公开实施例提供的驱动电路、其驱动方法及显示装置，通过设置电流控制电路可以产生驱动待驱动器件工作的驱动电流，通过设置时长控制电路可以产生输入第一晶体管的栅极的发光时长调制信号，以控制第一晶体管的导通时长。从而可以对待驱动器件接收驱动电流的时长进行控制。并且，这样还可以对流入待驱动器件的驱动电流和控制第一晶体管的导通时长进行单独控制，从而可以使控制第一晶体管的导通时长进行独立控制，进而可以使流入待驱动器件驱动电流的时长的调节范围较大。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (11)

  1. 一种驱动电路，其中，包括：
    电流控制电路，被配置为根据数据信号端的信号向待驱动器件提供驱动信号；
    第一晶体管，电连接于所述电流控制电路与所述待驱动器件之间；
    时长控制电路，与所述第一晶体管的栅极电连接，且被配置为根据扫描信号端、发光控制信号端、时长控制信号端以及基准电压信号端的信号的共同作用，向所述第一晶体管的栅极提供发光时长调制信号，以控制所述第一晶体管的导通时长。
  2. 如权利要求1所述的驱动电路，其中，所述时长控制电路包括：输入控制子电路和比较子电路；
    所述输入控制子电路被配置为响应于所述扫描信号端的信号，将所述时长控制信号端的信号提供给连接节点；以及响应于所述发光控制信号端的信号，将所述连接节点的信号提供给所述比较子电路；
    所述比较子电路被配置为根据所述输入控制子电路输出的信号与所述基准电压信号端的信号，输出所述发光时长调制信号。
  3. 如权利要求2所述的驱动电路，其中，所述输入控制子电路包括：第二晶体管、第三晶体管以及第一电容；
    所述第二晶体管的栅极与所述扫描信号端电连接，所述第二晶体管的第一极与所述时长控制信号端电连接，所述第二晶体管的第二极与所述连接节点电连接；
    所述第三晶体管的栅极与所述发光控制信号端电连接，所述第三晶体管的第一极与所述连接节点电连接，所述第三晶体管的第二极与所述比较子电路电连接；
    所述第一电容电连接于第一电源端与所述连接节点之间。
  4. 如权利要求2所述的驱动电路，其中，所述比较子电路包括：比较器；
    所述比较器的同相输入端与所述输入控制子电路电连接，所述比较器的反相输入端与所述基准电压信号端电连接，所述比较器的输出端与所述第一晶体管的栅极电连接。
  5. 如权利要求1-4任一项所述的驱动电路，其中，所述电流控制电路包括：驱动晶体管、第四晶体管以及第二电容；
    所述第四晶体管的栅极与所述扫描信号端电连接，所述第四晶体管的第一极与数据信号端电连接，所述第四晶体管的第二极与所述驱动晶体管的栅极电连接；
    所述驱动晶体管的第一极与第一电源端电连接，所述驱动晶体管的第二极与所述第一晶体管的第一极电连接；
    所述第二电容电连接于所述驱动晶体管的栅极与所述第一电源端之间。
  6. 如权利要求1-5任一项所述的驱动电路，还包括：第五晶体管；其中，所述第一晶体管通过所述第五晶体管与所述待驱动器件电连接；
    所述第五晶体管的栅极与所述发光控制信号端电连接。
  7. 一种显示装置，其中，包括：
    衬底基板；
    多个子像素，位于所述衬底基板一侧；
    所述多个子像素中的至少一个包括：发光器件和如权利要求1-7任一项所述的驱动电路；其中，所述发光器件作为所述待驱动器件。
  8. 如权利要求7所述的显示装置，其中，所述显示装置还包括：多条发光控制信号线与一个发光控制输入端子；一行子像素的驱动电路的发光控制信号端对应电连接一条发光控制信号线；各所述发光控制信号线均电连接所述发光控制输入端子。
  9. 如权利要求7所述的显示装置，其中，所述显示装置还包括：多条相互独立的发光控制信号线；
    一行子像素的驱动电路的发光控制信号端对应电连接一条发光控制信号线。
  10. 如权利要求7-9任一项所述的显示装置，其中，所述待驱动器件包括；微型发光二极管、有机电致发光二极管以及量子点发光二极管中的至少一种。
  11. 一种如权利要求7-10任一项所述的显示装置的驱动方法，其中，针对每一行子像素，一帧时间包括：
    信号输入阶段，所述电流控制电路响应于所述扫描信号端的信号，输入所述数据信号端的信号；以及所述时长控制电路响应于所述扫描信号端的信号，输入时长控制信号端的信号；
    发光阶段，所述电流控制电路根据数据信号端的信号产生驱动所述待驱动器件发光的驱动信号；所述时长控制电路根据所述发光控制信号端、所述基准电压信号端以及输入的时长控制信号端的信号的共同作用，向所述第一晶体管的栅极提供发光时长调制信号，以控制所述第一晶体管的导通时长；其中，所述基准电压信号端的电压在预设时长内单调变化，所述时长控制信号端的电压为固定电压且所述固定电压处于所述基准电压信号端单调变化的电压范围内。
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