WO2018016029A1 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
WO2018016029A1
WO2018016029A1 PCT/JP2016/071276 JP2016071276W WO2018016029A1 WO 2018016029 A1 WO2018016029 A1 WO 2018016029A1 JP 2016071276 W JP2016071276 W JP 2016071276W WO 2018016029 A1 WO2018016029 A1 WO 2018016029A1
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Prior art keywords
semiconductor device
substrate
back surface
region
manufacturing
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PCT/JP2016/071276
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English (en)
French (fr)
Inventor
和豊 高野
松尾　一成
柾宜 平尾
淳二 八尋
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三菱電機株式会社
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to US16/082,957 priority Critical patent/US10665670B2/en
Priority to PCT/JP2016/071276 priority patent/WO2018016029A1/ja
Priority to DE112016007081.0T priority patent/DE112016007081T5/de
Priority to JP2018528145A priority patent/JP6708257B2/ja
Priority to CN201680087689.3A priority patent/CN109478561B/zh
Publication of WO2018016029A1 publication Critical patent/WO2018016029A1/ja

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    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
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    • H01L29/861—Diodes
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    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

Definitions

  • the present invention relates to, for example, a semiconductor device used for high power applications and a method of manufacturing the same.
  • Patent Document 1 discloses a semiconductor device.
  • the central portion of the substrate is thinned to reduce resistance. Further, in order to maintain the strength, the outer peripheral portion of the substrate is made thicker than the central portion.
  • Patent Document 1 a process such as etching is added to form a thin central portion of the substrate. Therefore, the manufacturing process is complicated.
  • the present invention has been made to solve the above-described problems, and an object thereof is to obtain a semiconductor device capable of achieving resistance reduction and strength retention in an easy manner, and a method of manufacturing the same.
  • a semiconductor device is provided on a substrate provided with a cell portion through which a main current flows, and an end portion surrounding the cell portion, a surface structure provided on the substrate, and a back surface of the substrate.
  • a back surface electrode, the surface structure having a convex portion protruding upward at the top of the cell portion, at least a part of the cell portion being thinner than the end portion.
  • a surface process of forming a surface layer on the surface side of a substrate provided with a cell section and an end section surrounding the cell section, and after performing the surface process A surface structure step of forming a surface structure having a convex portion protruding upward on the cell portion, a step of attaching a protective film so as to cover the surface structure, and a state in which the protective film is attached
  • the method includes a polishing step of polishing the back surface of the substrate, a back surface step of forming a back surface semiconductor layer on the back surface side of the substrate, and a step of forming a back surface electrode on the back surface of the back surface semiconductor layer after performing the polishing step.
  • the semiconductor device according to the present invention has a convex portion on the surface side. By polishing the back surface of the substrate in this state, it is possible to thin the position facing the convex portion of the substrate. For this reason, it is possible to form the cell portion thinner than the end portion without adding a process. Therefore, the semiconductor device according to the present invention can reduce resistance and maintain its strength, and can be obtained by a simple manufacturing method.
  • the convex portion is formed on the surface side of the semiconductor device.
  • polishing the back surface of the substrate in this state it is possible to thin the position facing the convex portion of the substrate. Therefore, the cell portion can be formed thinner than the end portion without adding a process. Therefore, in the method of manufacturing a semiconductor device according to the present invention, it is possible to obtain a semiconductor device capable of achieving low resistance and maintaining strength in a simple process.
  • FIG. 1 is a cross-sectional view of a semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 7 is a diagram showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 7 is a diagram showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 7 is a diagram showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 7 is a diagram showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 7 is a diagram showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 7 is a diagram showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 16 is a cross-sectional view of a semiconductor device in a variation of the first embodiment of the present invention.
  • FIG. 16 is a cross-sectional view of a semiconductor device in a variation of the first embodiment of the present invention.
  • FIG. 7 is a plan view of a semiconductor device according to Embodiment 2 of the present invention.
  • FIG. 7 is a cross-sectional view of a semiconductor device in accordance with a second embodiment of the present invention. It is a figure which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention. It is a figure which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention.
  • FIG. 10 is a plan view of a semiconductor device according to Embodiment 3 of the present invention.
  • FIG. 6 is a cross-sectional view of a semiconductor device in accordance with a third embodiment of the present invention. It is a figure which shows the manufacturing method of the semiconductor device which concerns on Embodiment 3 of this invention. It is a figure which shows the manufacturing method of the semiconductor device which concerns on Embodiment 3 of this invention.
  • FIG. 1 is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention.
  • the semiconductor device 100 according to the present embodiment includes a substrate 30.
  • the substrate 30 includes the cell unit 10.
  • the cell unit 10 is a region in the substrate 30 in which a cell through which a main current flows is formed.
  • the substrate 30 includes the end portion 20 surrounding the cell portion 10.
  • the end portion 20 is a region in the substrate 30 where an edge termination structure is formed.
  • An edge termination structure is provided to suppress the concentration of the electric field at the end of the semiconductor device 100.
  • the semiconductor device 100 is a trench IGBT (Insulated Gate Bipolar Transistor).
  • the substrate 30 is provided with an N-type drift layer 31.
  • a P ⁇ type base 32 on the surface of the drift layer 31, a P ⁇ type base 32, an N + type emitter 33 and a gate 34 are formed.
  • the gate 34 is a trench gate.
  • an FLR (Field Limiting Ling) structure 37 is formed on the surface of the drift layer 31.
  • An N-type buffer layer 35 is formed on the back surface of the drift layer 31.
  • a P-type collector 36 is formed on the back surface of the buffer layer 35.
  • the substrate 30 includes the drift layer 31, the surface layer 38, and the back surface semiconductor layer 39.
  • the surface layer 38 is a layer formed on the surface side of the substrate 30 and includes a base 32, an emitter 33, a gate 34 and an FLR structure 37.
  • the back surface semiconductor layer 39 is a layer formed on the back surface side of the substrate 30 and includes a buffer layer 35 and a collector 36.
  • An insulating layer 46 is provided on the gate 34.
  • an aluminum electrode 41 is provided on the insulating layer 46 and the substrate 30.
  • a metal electrode 42 is provided on the aluminum electrode 41 in the upper part of the cell unit 10. The metal electrode 42 is formed on the entire top of the cell unit 10. The aluminum electrode 41 and the metal electrode 42 form a surface electrode 44.
  • An insulating film 50 is provided on the surface electrode 44 above the end portion 20.
  • the insulating film 50 is a so-called glass represented by an oxide film and a nitride film.
  • the insulating layer 46, the surface electrode 44, and the insulating film 50 constitute a surface structure 60.
  • the upper surface of the metal electrode 42 is higher than the upper surface of the insulating film 50. For this reason, the surface structure 60 is provided with the convex portion 61 protruding upward at the top of the cell portion 10.
  • a back surface electrode 43 is provided on the back surface of the substrate 30 so as to be in contact with the collector 36.
  • a recess 19 is formed at a position facing the metal electrode.
  • FIG. 2 to 7 are views showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention.
  • the surface process is performed.
  • the substrate 30 is implanted and diffused to form the drift layer 31 and the surface layer 38.
  • the surface structure process is performed.
  • the insulating layer 46 is formed on the gate 34.
  • an aluminum electrode 41 is formed on the substrate 30 and the insulating layer 46.
  • the insulating film 50 is formed on the aluminum electrode 41 in the upper portion of the terminal end portion 20.
  • the insulating film 50 is formed by glass coating.
  • the metal electrode 42 is formed on the aluminum electrode 41 so as to cover the entire upper portion of the cell portion 10.
  • the metal electrode 42 is formed so that the upper surface is located higher than the upper surface of the insulating film 50.
  • the surface structure 60 is formed on the substrate 30.
  • the surface structure 60 has a convex portion 61 protruding upward on the cell portion 10.
  • the metal electrode 42 is formed so that the upper surface of the metal electrode 42 is higher than the upper surface of the pad electrode.
  • the metal electrode 42 is formed such that the surface structure 60 has a convex shape.
  • a protective film 80 is attached to cover the surface structure 60.
  • the protective film 80 is an adhesive sheet for protecting the wafer surface at the time of wafer polishing.
  • a polishing process is performed. In the polishing step, first, the wafer with the protective film 80 attached is placed on the stage 70 such that the back surface of the substrate 30 faces upward. At this time, the protective film 80 and the stage 70 are in contact with each other. Next, the back of the substrate 30 is polished with a grinder.
  • the position facing the convex portion 61 is deeply polished.
  • the surface structure 60 includes the convex portion 61 on the top of the cell portion 10, a gap 72 is formed between the protective film 80 and the stage 70 on the top of the end portion 20. Therefore, the pressure applied to the end portion 20 at the time of polishing becomes weak. Therefore, the end portion 20 is polished to be shallower than the cell portion 10. From the above, the cell portion 10 is thinner than the end portion 20.
  • the protective film 80 is provided so that the unevenness on the surface of the wafer is easily transferred to the back surface during polishing.
  • the shape of the convex portion 61 needs to appear on the surface of the protective film 80.
  • the protective film 80 is in close contact with the surface structure 60.
  • the protective film 80 is thin.
  • the protective film may cancel the unevenness of the wafer surface. Therefore, the protective film 80 is made of one having high rigidity. From the above, the unevenness of the wafer surface is easily transferred to the back surface.
  • CMP Chemical Mechanical Polishing
  • FIG. 6 shows a state in which the protective film 80 is removed after the polishing process is performed.
  • the surface structure 60 includes the convex portion 61.
  • the shape of the convex portion 61 is transferred to the back surface of the substrate 30 by the polishing process. Therefore, the cell portion 10 is formed thinner than the end portion 20.
  • the back surface process is performed.
  • implantation and diffusion are performed on the back surface side of the substrate 30 to form the back surface semiconductor layer 39.
  • the back surface electrode 43 is formed on the back surface of the back surface semiconductor layer 39.
  • the semiconductor device 100 according to the present embodiment is formed.
  • FIG. 8 is a cross-sectional view of a semiconductor device according to a comparative example.
  • the semiconductor device 110 according to the comparative example does not include the metal electrode 42. Therefore, when the back surface of the substrate 30 is polished, the end portion is formed thin together with the cell portion 10. Alternatively, asperities on the surface of the semiconductor device 110 may be transferred, and the cell portion 10 may be thicker than the end portion 20.
  • the semiconductor device when the substrate becomes thinner, the semiconductor device has low resistance. On the other hand, as the substrate becomes thinner, the strength decreases. Therefore, while the resistance of the semiconductor device 110 according to the comparative example is reduced by the polishing of the substrate 30, the strength is reduced. On the other hand, a structure is conceivable in which only the central portion of the substrate is thinned and the outer peripheral portion is left thick. The semiconductor device having this structure has low resistance because the central portion of the substrate is thin, and strength is maintained because the outer peripheral portion is thick.
  • the surface structure 60 includes the convex portion 61.
  • the shape of the convex portion 61 is transferred to the back surface of the substrate 30.
  • the cell portion 10 is formed thinner than the end portion 20.
  • the polishing process of the substrate 30 is a process conventionally performed for the purpose of thinning the wafer, removing the oxide film, or removing the polysilicon. Therefore, in the present embodiment, the cell portion 10 can be thinner than the end portion 20 without adding a process. Therefore, the semiconductor device 100 capable of reducing resistance and maintaining strength can be obtained by a simple manufacturing process.
  • the convex portion 61 is formed so as to cover the entire region of the upper portion of the cell portion 10. For this reason, the entire region of the cell unit 10 which is a region through which the main current flows is formed thin. For this reason, the effect of low resistance by thinning the substrate 30 can be obtained high.
  • the end portion 20 is provided thicker than the cell portion 10. Therefore, a region in which the substrate 30 is thick is provided in the outer peripheral portion of the semiconductor device 100. Therefore, the strength of the semiconductor device 100 can be maintained.
  • the termination portion 20 is a region where a structure for improving the withstand voltage of the semiconductor device 100 is provided. In general, the withstand voltage tends to improve as the end portion is thicker. Therefore, in the present embodiment, by providing the terminal end 20 thicker than the cell unit 10, the terminal end 20 can maintain a higher withstand voltage than the cell unit 10.
  • a corner may be formed in the step formed by the recess. At this time, the electric field may be concentrated at the corner of the step.
  • the convex portion 61 on the front surface of the wafer is transferred to the back surface by the polishing process, so that the corner is not formed in the drift layer 31. Therefore, no corners are formed on the back surface semiconductor layer 39 and the back surface electrode 43. Therefore, the electric field is easily relaxed as compared with the case of using dry etching or sand blasting. Therefore, the withstand voltage can be improved.
  • the back surface electrode 43 under the cell portion 10 and the back surface electrode 43 under the end portion 20 form a concave shape. The lower surface of the back surface electrode 43 under the cell portion 10 and the lower surface of the back surface electrode 43 under the end portion 20 are smoothly connected.
  • the metal electrode 42 is provided on the aluminum electrode 41.
  • the metal electrode 42 is formed thick so as to form the convex portion 61 in the surface structure 60.
  • strength against wire bonding can be enhanced.
  • reliability of bonding of the terminal and the metal electrode 42 at the time of direct lead bonding can be enhanced.
  • the electric field inside the substrate may be intensified during the transition period of the switching operation.
  • the electric field inside the substrate is stronger as the substrate is thinner.
  • current may be concentrated due to an increase in the electric field.
  • the current concentration raises the temperature. Therefore, the resistance of the switching element to the current may be reduced. That is, the breakdown resistance of the switching element may be reduced.
  • the metal electrode 42 is provided on the aluminum electrode 41. By providing the thick metal electrode 42, the spreading resistance of the surface electrode 44 can be reduced. When the spreading resistance of the surface electrode 44 decreases, current concentration is suppressed. This improves the resistance to current. As a result, the breakdown tolerance of the semiconductor device 100 can be improved.
  • the semiconductor device 100 is a vertical trench IGBT.
  • the semiconductor device 100 may be a vertical power device.
  • the semiconductor device 100 may be an IGBT, a power MOSFET, or a diode.
  • the convex portion 61 is formed so as to cover the entire region of the upper portion of the cell portion 10.
  • the convex portion 61 may be formed on a part of the upper portion of the cell portion 10. In this case, a part of the cell portion 10 is formed thinner than the end portion 20.
  • FIG. 9 is a cross-sectional view of a semiconductor device according to a modification of the first embodiment of the present invention.
  • the semiconductor device 400 according to the modification includes the metal electrode 442.
  • the other structure is the same as that of the semiconductor device 100.
  • the gap 451 is formed between the insulating film 50 and the metal electrode 442.
  • the metal electrode 442 protrudes upward on the top surface of the semiconductor device 400. Therefore, when the back surface of the substrate 30 is polished, a strong stress may be applied to the metal electrode 442.
  • the gap 451 is formed between the insulating film 50 and the metal electrode 442. Thereby, the stress applied to the metal electrode 442 in the polishing step is suppressed from being transmitted to the insulating film 50. Therefore, it is possible to prevent the insulating film 50 which is glass from being broken.
  • FIG. 10 is a cross-sectional view of a semiconductor device 500 according to another modification of the first embodiment of the present invention.
  • the semiconductor device 500 according to the modification includes a metal electrode 542.
  • the thickness A of the convex portion 561 formed by the metal electrode 542 is thinner than the thickness B of the substrate 30. Thereby, when the back surface of the substrate 30 is polished, it is possible to prevent the polished portion from penetrating the substrate 30. In addition, cracking of the substrate 30 due to the thinning of the substrate 30 can be prevented.
  • the substrate 30 may be formed of a wide band gap semiconductor.
  • a wide band gap semiconductor By using a wide band gap semiconductor, the withstand voltage and the resistance to current can be improved. That is, the breakdown tolerance of the semiconductor device 100 can be improved. Silicon carbide, gallium nitride based materials and diamond can be used as the wide band gap semiconductor.
  • FIG. 11 is a plan view of the semiconductor device according to the second embodiment of the present invention.
  • an IGBT 292 and a diode 291 are formed in the semiconductor device 200 according to the present embodiment.
  • the diode 291 is formed adjacent to the IGBT 292.
  • the IGBT 292 and the diode 291 are surrounded by the termination 20.
  • the structure of the substrate 230 at the end portion 20 is the same as that of the first embodiment.
  • a gate pad 213 for applying a gate voltage to the gate 234 of the IGBT 292 is formed at the end of the IGBT 292.
  • FIG. 12 is a cross-sectional view of the semiconductor device according to the second embodiment of the present invention.
  • FIG. 12 is a cross-sectional view obtained by cutting the semiconductor device 200 shown in FIG. 11 along I-II straight line.
  • the semiconductor device 200 includes a substrate 230, a surface structure 260 provided on the substrate 230, and a back electrode 243 provided on the back surface of the substrate 230.
  • the substrate 230 includes the cell portion 210 and the end portion 20 surrounding the cell portion 210.
  • an IGBT region 212 and a diode region 211 provided adjacent to the IGBT region 212 are provided.
  • the IGBT region 212 is a region in which the IGBT 292 of the cell unit 210 is formed.
  • the diode region 211 is a region in which the diode 291 of the cell unit 210 is formed.
  • the substrate 230 includes an N-type drift layer 231, a surface layer 238, and a back surface semiconductor layer 239.
  • a P ⁇ type base 232 on the surface of the drift layer 231, a P ⁇ type base 232, an N + type emitter 233 and a gate 234 which is a trench gate are provided.
  • a P-type anode 252 and a gate 234 are provided on the surface of the drift layer 231.
  • the base 232 is the same layer as the anode 252.
  • the diode region 211 may not have the gate 234.
  • N-type buffer layer 235 is formed on the back surface of the drift layer 231.
  • a P-type collector 236 is formed on the back surface of the buffer layer 235. In the diode region 211, a part of the collector 236 is replaced with the N-type cathode 256.
  • the surface layer 238 includes a base 232, an anode 252, an emitter 233, a gate 234 and an FLR structure 37.
  • the back surface semiconductor layer 239 also includes a buffer layer 235, a collector 236 and a cathode 256.
  • An insulating layer 246 is provided over the gate 234. Further, an aluminum electrode 241 is provided over the insulating layer 246 and the substrate 230. A metal electrode 242 is provided on the aluminum electrode 241 above the IGBT region 212. The metal electrode 242 is formed on the entire top of the IGBT region 212. The aluminum electrode 241 and the metal electrode 242 form a surface electrode 244. The insulating layer 246, the surface electrode 244 and the insulating film 50 constitute a surface structure 260. The upper surface of the metal electrode 242 is higher than the upper surface of the insulating film 50. For this reason, the surface structure 260 is provided with the convex part 261 which protrudes upwards in the upper part of the IGBT area
  • a back surface electrode 243 is provided on the back surface of the substrate 230 so as to be in contact with the collector 236 and the cathode 256.
  • the IGBT 292 which is a trench IGBT and the diode 291 are formed. Therefore, the semiconductor device 200 becomes RC (Reverse Conducting) -IGBT.
  • the diode 291 is formed by replacing a part of the P-type collector 236 with an N-type cathode 256.
  • a recess 219 is formed at a position facing the metal electrode 242. The provision of the recess 219 on the back surface side of the substrate 230 makes the IGBT region 212 thinner than the diode region 211.
  • 13 to 17 are views showing a method of manufacturing a semiconductor device according to the second embodiment of the present invention.
  • the surface process is performed.
  • the drift layer 231 and the surface layer 238 are formed on the substrate 230.
  • the surface structure process is performed.
  • the insulating layer 246 is formed over the gate 234.
  • an aluminum electrode 241 is formed over the substrate 230 and the insulating layer 246.
  • the insulating film 50 is formed on the aluminum electrode 241 in the upper portion of the terminal end portion 20.
  • a metal electrode 242 is formed on the aluminum electrode 241 above the IGBT region 212.
  • the metal electrode 242 is formed to cover the entire top of the IGBT region 212.
  • the metal electrode 242 is formed so that the upper surface thereof is higher than the upper surface of the insulating film 50. Thereby, the surface structure 260 provided with the convex part 261 is formed.
  • a protective film 280 is attached on the surface structure 260.
  • a polishing process is performed to polish the back surface of the substrate 230.
  • the convex portion 261 is formed in the upper portion of the IGBT region 212. Therefore, by polishing the back surface of the substrate 230, the portion facing the convex portion 261 is deeply polished. For this reason, as shown in FIG. 16, the IGBT region 212 of the substrate 230 is formed thin.
  • the back surface process is performed.
  • the buffer layer 235 is formed on the back surface side of the substrate 230.
  • the cathode 256 is formed on the back surface of the buffer layer 235.
  • a collector 236 is formed by resist injection by photolithography.
  • the back surface electrode 243 is formed on the back surface of the collector 236 and the cathode 256.
  • the semiconductor device 200 according to the present embodiment is formed.
  • convex portion 261 is formed in the upper part of IGBT region 212. Therefore, the IGBT region 212 of the substrate 230 is formed thinner than the diode region 211 by the polishing process. Therefore, it is possible to reduce the resistance of the IGBT region 212 through which the main current flows. Further, the termination 20 and the diode region 211 are thicker than the IGBT region 212. Therefore, the strength and the pressure resistance can be maintained.
  • the diode when the bias direction is switched from the forward bias state, there is a period in which current flows in the reverse direction.
  • the surge voltage during recovery which is a period in which current flows in the reverse direction, is less likely to oscillate as the substrate is thicker.
  • the diode region 211 of the substrate 230 is formed thicker than the IGBT region. Therefore, improvement in recovery tolerance can be expected compared to the first embodiment.
  • FIG. 18 is a plan view of the semiconductor device according to the third embodiment of the present invention.
  • an IGBT 392 and a diode 391 are formed in the semiconductor device 300 according to the present embodiment.
  • the diode 391 is formed adjacent to the IGBT 392.
  • the IGBT 392 and the diode 391 are surrounded by the termination 20.
  • the structure of the end portion 20 is the same as that of the first embodiment.
  • a gate pad 313 for supplying power to the gate 234 of the IGBT 392 is formed at the end of the IGBT 392, a gate pad 313 for supplying power to the gate 234 of the IGBT 392 is formed.
  • FIG. 19 is a cross-sectional view of the semiconductor device according to the third embodiment of the present invention.
  • FIG. 19 is a cross-sectional view obtained by cutting the semiconductor device 300 shown in FIG. 18 along a line I-II.
  • the semiconductor device 300 includes a substrate 330, a surface structure 360 provided on the substrate 330, and a back electrode 343 provided on the back surface of the substrate 330.
  • the substrate 330 includes the cell portion 310 and the end portion 20 surrounding the cell portion 310.
  • Cell portion 310 is provided with an IGBT region 312 and a diode region 311 provided adjacent to IGBT region 312.
  • the IGBT region 312 is a region in which the IGBT 392 of the cell unit 310 is formed.
  • the diode region 311 is a region in which the diode 391 of the cell unit 310 is formed.
  • the substrate 330 includes the drift layer 331, the surface layer 238, and the back surface semiconductor layer 339.
  • the structure of the surface layer 238 is the same as that of the second embodiment.
  • an N-type buffer layer 335 is formed on the back surface of the drift layer 331.
  • a P-type collector 336 is formed on the back surface of the buffer layer 335.
  • the buffer layer 335 is formed on the back surface of the drift layer 331. Buffer layer 335 is exposed from collector 336 in diode region 311.
  • the back surface semiconductor layer 339 includes a buffer layer 335 and a collector 336.
  • the structures of the insulating layer 246 and the aluminum electrode 241 according to the present embodiment are the same as those of the second embodiment.
  • the metal electrode 342 is provided on the aluminum electrode 241 above the diode region 311.
  • the metal electrode 342 is formed on the entire top of the diode region 311.
  • the aluminum electrode 241 and the metal electrode 342 form a surface electrode 344.
  • the insulating layer 246, the surface electrode 344 and the insulating film 50 constitute a surface structure 360.
  • the upper surface of the metal electrode 342 is higher than the upper surface of the insulating film 50. For this reason, the surface structure 360 is provided with the convex part 361 which protrudes upwards in the upper part of the diode area
  • the back surface electrode 343 is provided on the back surface of the substrate 330.
  • buffer layer 335 is exposed from collector 336 in diode region 311. Therefore, in the diode region 311, the buffer layer 335 is in contact with the back electrode 343.
  • the diode 391 is formed by bringing the N-type buffer layer 335 and the back electrode 343 into contact with each other. From the above, in the semiconductor device 300, the IGBT 392, which is a trench IGBT, and the diode 391 are formed. Therefore, the semiconductor device 300 becomes an RC-IGBT as the semiconductor device 200 does.
  • 20 to 25 are views showing a method of manufacturing a semiconductor device according to the third embodiment of the present invention. As shown in FIG. 20, the method of manufacturing the semiconductor device 300 is the same as that of the second embodiment up to the step of forming the insulating film 50.
  • a metal electrode 342 is formed on the aluminum electrode 241 so as to cover the entire region of the upper portion of the diode region 311.
  • the metal electrode 342 is formed such that the upper surface thereof is positioned higher than the upper surface of the insulating film 50.
  • the back surface process is performed.
  • a back surface semiconductor layer 339 is formed.
  • the buffer layer 335 is formed on the back surface side of the substrate 330.
  • a collector 336 is formed on the back surface of the buffer layer 335.
  • a protective film 380 is attached on the surface structure 360.
  • the polishing process is performed.
  • the polishing process is performed after the back surface process. Therefore, in the polishing process, the back surface semiconductor layer 339 is polished.
  • the surface electrode 344 includes the convex portion 361 in the upper part of the diode region 311. Therefore, on the back surface of the back surface semiconductor layer 339, the position facing the convex portion 361 is deeply polished. Therefore, as shown in FIG. 24, the diode region 311 of the substrate 330 is formed thin. In the polishing process, the collector 336 in the diode region 311 is removed, and polishing is performed so that the buffer layer 335 is exposed.
  • the back electrode 343 is formed on the back surface of the collector 336.
  • the back electrode 343 is provided to be in contact with the buffer layer 335 in a portion where the collector 336 is removed and the buffer layer 335 is exposed.
  • the semiconductor device 300 according to the present embodiment is formed.
  • the diode 391 is formed by removing a part of the collector 336 in the polishing process. Therefore, in this embodiment mode, the diode 391 can be formed without adding the steps of photolithography and etching. Therefore, the RC-IGBT can be obtained by a simple process. In addition, since a part of the cell portion 310 is thinned, an effect of reducing resistance can be obtained.
  • the buffer layer 335 is exposed in the polishing step.
  • the drift layer 331 may be exposed in the polishing process.
  • the back surface electrode 343 is formed such that the N-type drift layer 331 and the back surface electrode 343 are in contact with each other.

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Abstract

本願の発明に係る半導体装置は、セル部と、セル部を囲む終端部と、を備えた基板と、基板の上に設けられた表面構造と、基板の裏面に設けられた裏面電極と、を備え、表面構造は、セル部の上部に、上方に突出した凸部を有し、セル部の少なくとも一部は、終端部よりも薄い。

Description

半導体装置およびその製造方法
　この発明は、例えば、大電力用途に用いられる半導体装置およびその製造方法に関する。
　特許文献１には、半導体装置が開示されている。この半導体装置では、低抵抗化のために、基板の中央部を薄くしている。また、強度を保持するために基板の外周部を中央部に比べて厚くしている。
日本特開２００３－３０３９６６号公報
　特許文献１に示される半導体装置では、基板の中央部を薄く形成するためにエッチング等の工程を追加している。従って、製造工程が複雑化する。
　本発明は上述の問題を解決するためになされたものであり、その目的は、容易な方法で低抵抗化および強度の保持が可能な半導体装置およびその製造方法を得ることである。
　本願の発明に係る半導体装置は、主電流が流れるセル部と、前記セル部を囲む終端部と、を備えた基板と、前記基板の上に設けられた表面構造と、前記基板の裏面に設けられた裏面電極と、を備え、前記表面構造は、前記セル部の上部に、上方に突出した凸部を有し、前記セル部の少なくとも一部は、前記終端部よりも薄い。
　本願の発明に係る半導体装置の製造方法は、セル部と、前記セル部を囲む終端部と、を備えた基板の表面側に、表面層を形成する表面工程と、前記表面工程の実施後に、前記セル部の上に上方に突出した凸部を有する表面構造を形成する表面構造工程と、前記表面構造を覆うように保護膜を貼り付ける工程と、前記保護膜を貼り付けた状態で、前記基板の裏面を研磨する研磨工程と、前記基板の裏面側に裏面半導体層を形成する裏面工程と、前記研磨工程の実施後に、前記裏面半導体層の裏面に裏面電極を形成する工程と、を備える。
　この発明に係る半導体装置は表面側に凸部を備える。この状態で、基板の裏面を研磨することにより、基板の凸部に対向した位置を薄く形成する事が出来る。このため、工程を追加せずに終端部よりもセル部を薄く形成することが可能になる。従って、本発明に係る半導体装置は、低抵抗化および強度の保持が可能であり、簡単な製造方法で得ることが出来る。
　この発明に係る半導体装置の製造方法によれば、半導体装置の表面側に凸部を形成する。この状態で、基板の裏面を研磨することにより、基板の凸部に対向した位置を薄く形成する事が出来る。このため、工程を追加せずに終端部よりもセル部を薄く形成することが出来る。従って、本発明に係る半導体装置の製造方法では、低抵抗化および強度の保持が可能な半導体装置を簡単な工程で得ることが可能になる。
本発明の実施の形態１に係る半導体装置の断面図である。 本発明の実施の形態１に係る半導体装置の製造方法を示す図である。 本発明の実施の形態１に係る半導体装置の製造方法を示す図である。 本発明の実施の形態１に係る半導体装置の製造方法を示す図である。 本発明の実施の形態１に係る半導体装置の製造方法を示す図である。 本発明の実施の形態１に係る半導体装置の製造方法を示す図である。 本発明の実施の形態１に係る半導体装置の製造方法を示す図である。 比較例に係る半導体装置の断面図である。 本発明の実施の形態１の変形例に係る半導体装置の断面図である。 本発明の実施の形態１の変形例に係る半導体装置の断面図である。 本発明の実施の形態２に係る半導体装置の平面図である。 本発明の実施の形態２に係る半導体装置の断面図である。 本発明の実施の形態２に係る半導体装置の製造方法を示す図である。 本発明の実施の形態２に係る半導体装置の製造方法を示す図である。 本発明の実施の形態２に係る半導体装置の製造方法を示す図である。 本発明の実施の形態２に係る半導体装置の製造方法を示す図である。 本発明の実施の形態２に係る半導体装置の製造方法を示す図である。 本発明の実施の形態３に係る半導体装置の平面図である。 本発明の実施の形態３に係る半導体装置の断面図である。 本発明の実施の形態３に係る半導体装置の製造方法を示す図である。 本発明の実施の形態３に係る半導体装置の製造方法を示す図である。 本発明の実施の形態３に係る半導体装置の製造方法を示す図である。 本発明の実施の形態３に係る半導体装置の製造方法を示す図である。 本発明の実施の形態３に係る半導体装置の製造方法を示す図である。 本発明の実施の形態３に係る半導体装置の製造方法を示す図である。
　本発明の実施の形態に係る半導体装置およびその製造方法について図面を参照して説明する。同じ又は対応する構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。
実施の形態１．
　図１は、本発明の実施の形態１に係る半導体装置の断面図である。本実施の形態に係る半導体装置１００は、基板３０を備える。基板３０は、セル部１０を備える。セル部１０は、基板３０において主電流が流れるセルが形成される領域である。また、基板３０は、セル部１０を囲む終端部２０を備える。終端部２０は、基板３０において、エッジターミネーション構造が形成される領域である。エッジターミネーション構造は、半導体装置１００の端部での電界集中を抑制するために設けられる。
　本実施の形態に係る半導体装置１００は、トレンチＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ　Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ）である。基板３０はＮ型のドリフト層３１を備える。セル部１０において、ドリフト層３１の表面には、Ｐ－型のベース３２、Ｎ＋型のエミッタ３３およびゲート３４が形成される。ゲート３４はトレンチゲートである。また、終端部２０において、ドリフト層３１の表面には、ＦＬＲ（Ｆｉｅｌｄ　Ｌｉｍｉｔｉｎｇ　Ｌｉｎｇ）構造３７が形成される。ドリフト層３１の裏面には、Ｎ型のバッファ層３５が形成される。バッファ層３５の裏面には、Ｐ型のコレクタ３６が形成される。
　本実施の形態では、基板３０は、ドリフト層３１と、表面層３８と、裏面半導体層３９を備える。表面層３８は、基板３０の表面側に形成された層であり、ベース３２、エミッタ３３、ゲート３４およびＦＬＲ構造３７を含む。また、裏面半導体層３９は、基板３０の裏面側に形成された層であり、バッファ層３５およびコレクタ３６を含む。
　ゲート３４の上には絶縁層４６が設けられる。また、絶縁層４６および基板３０の上には、アルミ電極４１が設けられる。セル部１０の上部において、アルミ電極４１上にメタル電極４２が設けられる。メタル電極４２は、セル部１０の上部の全域に形成される。アルミ電極４１と、メタル電極４２は表面電極４４を形成する。
　終端部２０の上部において、表面電極４４の上には絶縁膜５０が設けられる。絶縁膜５０は、酸化膜および窒化膜に代表される所謂ガラスである。絶縁層４６と、表面電極４４と、絶縁膜５０は表面構造６０を構成する。メタル電極４２の上面は、絶縁膜５０の上面よりも高い。このため、表面構造６０は、セル部１０の上部に、上方に突出した凸部６１を備えることとなる。
　基板３０の裏面において、コレクタ３６と接するように裏面電極４３が設けられる。また、基板３０の裏面側には、メタル電極４２と対向する位置に凹部１９が形成される。基板３０の裏面側に凹部１９が設けられることで、終端部２０と比較して、セル部１０は薄くなる。
　次に、本実施の形態に係る半導体装置１００の製造方法を説明する。図２～図７は、本発明の実施の形態１に係る半導体装置の製造方法を示す図である。まず、表面工程を実施する。表面工程では、図２に示すように、基板３０に注入および拡散を行い、ドリフト層３１および表面層３８を形成する。次に、表面構造工程を実施する。表面構造工程では、まず、ゲート３４の上に絶縁層４６を形成する。次に、基板３０および絶縁層４６の上にアルミ電極４１を形成する。次に、終端部２０の上部において、アルミ電極４１の上に絶縁膜５０を形成する。絶縁膜５０はガラスコーティングにより形成する。
　次に、図３に示すように、セル部１０の上部の全域を覆うように、アルミ電極４１上にメタル電極４２を形成する。メタル電極４２は、上面が絶縁膜５０の上面よりも高い位置に配置されるように形成する。以上から、基板３０の上に表面構造６０が形成される。表面構造６０は、セル部１０の上に、上方に突出した凸部６１を有する。ここで、絶縁膜５０の上にパッド電極が設けられる場合は、パッド電極の上面よりもメタル電極４２の上面が高い位置に配置されるように、メタル電極４２を形成する。メタル電極４２は、表面構造６０の形状が凸型となるように形成する。
　次に、図４に示すように、表面構造６０を覆うように保護膜８０を貼る。保護膜８０は、ウエハ研磨時にウエハ表面を保護するための粘着シートである。次に、図５に示すように、研磨工程を実施する。研磨工程では、まず、保護膜８０を貼り付けた状態のウエハを、基板３０の裏面が上を向くように、ステージ７０に置く。この時、保護膜８０とステージ７０が接する。次に、グラインダーで基板３０の裏面を研磨する。
　ここで、表面に凹凸があるウエハにおいて、ウエハ表面に保護膜を貼り付けた状態で、ウエハ裏面を研磨すると、ウエハ裏面にウエハ表面の凹凸が転写される。これは、ウエハ表面の凹凸によって、研磨時にウエハに加わる圧力がウエハ面内で不均一となる為である。ウエハ表面に凸部がある部分では研磨時に圧力が強く働き、ウエハは深く研磨される。また、ウエハ表面に凹部が形成される部分では、ステージとの間に隙間が生じる。このため、研磨時に加わる圧力が弱くなり、ウエハは浅く研磨される。
　従って、本実施の形態では、基板３０の裏面において、凸部６１と対向する位置は、深く研磨される。また、表面構造６０はセル部１０の上部に凸部６１を備えるため、終端部２０の上部では、保護膜８０とステージ７０との間には隙間７２が形成される。従って、研磨時に終端部２０に加わる圧力は弱くなる。このため、終端部２０は、セル部１０よりも浅く研磨されることとなる。以上から、セル部１０は、終端部２０よりも薄くなる。
　ここで、本実施の形態では、研磨時にウエハ表面の凹凸が裏面に転写され易いように、保護膜８０を設ける。ウエハ表面の凹凸が裏面に転写されるためには、凸部６１の形状が保護膜８０の表面に現れることが必要となる。このため、保護膜８０は表面構造６０に密着させる。また、保護膜８０は薄いものを用いる。また、保護膜が柔らかいと、ウエハ表面の凹凸を保護膜が打ち消す可能性がある。このため、保護膜８０は剛性が高いものを用いる。以上から、ウエハ表面の凹凸が裏面に転写され易くなる。また、本実施の形態では、基板３０の研磨にグラインダーを用いたが、ＣＭＰ（Ｃｈｅｍｉｃａｌ　Ｍｅｃｈａｎｉｃａｌ　Ｐｏｌｉｓｈｉｎｇ）を用いて研磨を行っても良い。
　図６は、研磨工程の実施後に保護膜８０を取り除いた状態を示す。本実施の形態では、表面構造６０が凸部６１を備える。研磨工程によって凸部６１の形状が基板３０の裏面に転写される。従って、セル部１０は終端部２０よりも薄く形成される。
　次に、図７に示すように、裏面工程を実施する。裏面工程では、基板３０の裏面側に、注入および拡散を行い、裏面半導体層３９を形成する。次に、裏面半導体層３９の裏面に裏面電極４３を形成する。以上で、本実施の形態に係る半導体装置１００が形成される。
　図８は、比較例に係る半導体装置の断面図である。比較例に係る半導体装置１１０はメタル電極４２を備えない。従って、基板３０の裏面を研磨すると、セル部１０とともに終端部も薄く形成される。もしくは、半導体装置１１０の表面の凹凸が転写され、終端部２０と比較して、セル部１０が厚くなる可能性がある。
　一般に、基板が薄くなると半導体装置は低抵抗となる。一方で、基板が薄くなると、強度が低下する。従って、比較例に係る半導体装置１１０は、基板３０の研磨によって低抵抗化される一方で、強度が低下する。これに対し、基板の中央部のみを薄くし、外周部は厚く残す構造が考えられる。この構造の半導体装置は、基板の中央部が薄いことで低抵抗となり、外周部が厚いことで強度が保持される。
　ここで、基板の中央部のみを薄くする方法として、写真製版処理でマスクを形成し、その後、ドライエッチングまたはサンドブラストを実施することが考えられる。しかし、この方法では、基板の中央部を薄くするために、写真製版処理およびドライエッチングまたはサンドブラストの工程を追加する必要がある。従って、製造工程が複雑化する。
　これに対し、本実施の形態では、表面構造６０は凸部６１を備える。研磨工程では、凸部６１の形状が基板３０の裏面に転写される。この結果、セル部１０が終端部２０よりも薄く形成される。ここで、基板３０の研磨工程は、従来からウエハの薄化、酸化膜の除去またはポリシリコンの除去の目的で実施されている工程である。従って、本実施の形態では、工程を追加せずに、セル部１０を終端部２０よりも薄く出来る。このため、低抵抗化および強度の保持が可能な半導体装置１００を、簡単な製造工程で得ることが出来る。
　また、本実施の形態では、セル部１０の上部の全域を覆うように、凸部６１が形成される。このため、主電流が流れる領域となるセル部１０の全域が薄く形成される。このため、基板３０を薄くすることによる低抵抗化の効果を高く得ることができる。
　また、本実施の形態では、終端部２０はセル部１０よりも厚く設けられる。このため、半導体装置１００の外周部に基板３０が厚い領域が設けられる。従って、半導体装置１００の強度を保持することが出来る。また、終端部２０は、半導体装置１００の耐圧を向上するための構造が設けられる領域である。一般に、終端部が厚いほど耐圧は向上する傾向にある。従って、本実施の形態では、終端部２０がセル部１０よりも厚く設けられることで、終端部２０がセル部１０よりも高い耐圧を保持することが可能になる。
　また、ＲＩＥ（Ｒｅａｃｔｉｖｅ　Ｉｏｎ　Ｅｔｃｈｉｎｇ）などのドライエッチングまたはサンドブラストを用いて基板の裏面側に凹部を形成すると、凹部によって形成される段差に角が形成される場合がある。このとき、段差の角の部分に電界が集中することがある。
　これに対し、本実施の形態では、ウエハ表面の凸部６１を研磨工程によって裏面に転写するため、ドリフト層３１には角が形成されない。このため、裏面半導体層３９および裏面電極４３にも角が形成されない。従って、ドライエッチングまたはサンドブラストを用いる場合と比較して、電界が緩和され易くなる。このため、耐圧を向上できる。本実施の形態では、セル部１０の下の裏面電極４３と、終端部２０の下の裏面電極４３は凹形状を形成する。セル部１０の下の裏面電極４３の下面と、終端部２０の下の裏面電極４３の下面は滑らかに接続されている。
　また、本実施の形態では、アルミ電極４１上にメタル電極４２が設けられる。メタル電極４２は、表面構造６０に凸部６１を形成するように、厚く形成される。厚いメタル電極４２を設けることで、ワイヤボンディングに対する強度を高めることが出来る。また、ダイレクトリードボンディング時の端子とメタル電極４２の接合の信頼性を高めることが出来る。
　また、スイッチング素子では、スイッチング動作の過渡期間に、基板内部の電界が強まることがある。基板内部の電界は、基板が薄いほど強くなる。このようなスイッチング素子に５μｍ程度の厚さのアルミ電極を形成した構造では、電界が強まることにより電流が集中することがある。電流の集中によって温度が上昇する。このため、スイッチング素子の電流に対する耐性が低下することがある。つまり、スイッチング素子の破壊耐量が低下する場合がある。ここで、本実施の形態ではアルミ電極４１上にメタル電極４２が設けられる。厚いメタル電極４２が設けられることで、表面電極４４の広がり抵抗を低下させることが出来る。表面電極４４の広がり抵抗が低下すると、電流の集中が抑制される。このため、電流に対する耐性が向上する。この結果、半導体装置１００の破壊耐量を向上出来る。
　本実施の形態に係る半導体装置１００は縦型のトレンチＩＧＢＴである。この変形例として、半導体装置１００は、縦型のパワーデバイスであれば良い。例えば、半導体装置１００は、ＩＧＢＴ、パワーＭＯＳＦＥＴ、ダイオードであってもよい。また、本実施の形態では、セル部１０の上部の全域を覆うように、凸部６１が形成される。これに対し、凸部６１は、セル部１０の上部の一部に形成されても良い。この場合、セル部１０の一部が終端部２０よりも薄く形成されることとなる。
　図９は、本発明の実施の形態１の変形例に係る半導体装置の断面図である。変形例に係る半導体装置４００は、メタル電極４４２を備える。その他の構造は、半導体装置１００と同様である。半導体装置４００では、絶縁膜５０と、メタル電極４４２との間に隙間４５１が形成される。
　メタル電極４４２は、半導体装置４００の上面において上方に突出している。このため、基板３０の裏面を研磨する際に、メタル電極４４２に強い応力が加わる場合がある。本実施の形態では、絶縁膜５０と、メタル電極４４２との間に隙間４５１が形成される。これにより、研磨工程においてメタル電極４４２に加わる応力が絶縁膜５０に伝わることが抑制される。従って、ガラスである絶縁膜５０が割れることを防止する事が出来る。
　図１０は、本発明の実施の形態１の他の変形例に係る半導体装置５００の断面図である。変形例に係る半導体装置５００は、メタル電極５４２を備える。メタル電極５４２によって形成される凸部５６１の厚さＡは、基板３０の厚さＢよりも薄い。これにより、基板３０の裏面を研磨する際に、研磨部分が基板３０を貫通することを防止できる。また、基板３０が薄くなることによる基板３０の割れを防止する事が出来る。
　基板３０はワイドバンドギャップ半導体で形成されても良い。ワイドバンドギャップ半導体を用いることで、耐圧および電流に対する耐性を向上出来る。つまり、半導体装置１００の破壊耐量を向上出来る。ワイドバンドギャップ半導体として、炭化珪素、窒化ガリウム系材料およびダイヤモンドを用いることが出来る。
　これらの変形は以下の実施の形態に係る半導体装置およびその製造方法について適宜応用することができる。なお、以下の実施の形態に係る半導体装置およびその製造方法については実施の形態１との共通点が多いので、実施の形態１との相違点を中心に説明する。
実施の形態２．
　図１１は、本発明の実施の形態２に係る半導体装置の平面図である。本実施の形態に係る半導体装置２００は、ＩＧＢＴ２９２とダイオード２９１が形成されている。ダイオード２９１はＩＧＢＴ２９２に隣接して形成される。ＩＧＢＴ２９２とダイオード２９１は、終端部２０に囲まれる。終端部２０での基板２３０の構造は、実施の形態１と同様である。また、ＩＧＢＴ２９２の端部には、ＩＧＢＴ２９２のゲート２３４にゲート電圧を印加するためのゲートパッド２１３が形成されている。
　図１２は、発明の実施の形態２に係る半導体装置の断面図である。図１２は、図１１に示す半導体装置２００をI-II直線で切断することで得られる断面図である。半導体装置２００は、基板２３０と、基板２３０の上に設けられた表面構造２６０と、基板２３０の裏面に設けられた裏面電極２４３を備える。基板２３０は、セル部２１０とセル部２１０を囲む終端部２０を備える。
　セル部２１０には、ＩＧＢＴ領域２１２と、ＩＧＢＴ領域２１２に隣接して設けられたダイオード領域２１１と、が設けられる。ＩＧＢＴ領域２１２は、セル部２１０のＩＧＢＴ２９２が形成される領域である。また、ダイオード領域２１１は、セル部２１０のダイオード２９１が形成される領域である。
　基板２３０は、Ｎ型のドリフト層２３１、表面層２３８および裏面半導体層２３９を備える。ＩＧＢＴ領域２１２において、ドリフト層２３１の表面には、Ｐ－型のベース２３２、Ｎ＋型のエミッタ２３３およびトレンチゲートであるゲート２３４が設けられる。ダイオード領域２１１において、ドリフト層２３１の表面には、Ｐ－型のアノード２５２およびゲート２３４が設けられる。ここで、ベース２３２はアノード２５２と同じ層である。また、ダイオード領域２１１は、ゲート２３４を備えなくても良い。
　ドリフト層２３１の裏面には、Ｎ型のバッファ層２３５が形成される。バッファ層２３５の裏面には、Ｐ型のコレクタ２３６が形成される。また、ダイオード領域２１１において、コレクタ２３６の一部がＮ型のカソード２５６に置き換わっている。本実施の形態では、表面層２３８は、ベース２３２、アノード２５２、エミッタ２３３、ゲート２３４およびＦＬＲ構造３７を含む。また、裏面半導体層２３９は、バッファ層２３５、コレクタ２３６およびカソード２５６を含む。
　ゲート２３４の上には、絶縁層２４６が設けられる。また、絶縁層２４６および基板２３０の上には、アルミ電極２４１が設けられる。ＩＧＢＴ領域２１２の上部において、アルミ電極２４１上にメタル電極２４２が設けられる。メタル電極２４２は、ＩＧＢＴ領域２１２の上部の全域に形成される。アルミ電極２４１と、メタル電極２４２は表面電極２４４を形成する。絶縁層２４６、表面電極２４４および絶縁膜５０は表面構造２６０を構成する。メタル電極２４２の上面は、絶縁膜５０の上面よりも高い。このため、表面構造２６０は、ＩＧＢＴ領域２１２の上部に、上方に突出した凸部２６１を備えることとなる。
　基板２３０の裏面には、コレクタ２３６およびカソード２５６と接するように裏面電極２４３が設けられる。以上から、半導体装置２００には、トレンチＩＧＢＴであるＩＧＢＴ２９２と、ダイオード２９１が形成される。従って、半導体装置２００は、ＲＣ（Ｒｅｖｅｒｓｅ　Ｃｏｎｄｕｃｔｉｎｇ）－ＩＧＢＴとなる。ダイオード２９１は、Ｐ型のコレクタ２３６の一部をＮ型のカソード２５６に置きかえることで形成される。また、基板２３０の裏面側には、メタル電極２４２と対向する位置に凹部２１９が形成される。基板２３０の裏面側に凹部２１９が設けられることで、ダイオード領域２１１と比較して、ＩＧＢＴ領域２１２は薄くなる。
　次に、本実施の形態に係る半導体装置２００の製造方法を説明する。図１３～図１７は、本発明の実施の形態２に係る半導体装置の製造方法を示す図である。まず、表面工程を実施する。表面工程では、図１３に示すように、基板２３０にドリフト層２３１と表面層２３８を形成する。次に、表面構造工程を実施する。表面構造工程では、まず、ゲート２３４の上に絶縁層２４６を形成する。次に、基板２３０および絶縁層２４６の上にアルミ電極２４１を形成する。次に、終端部２０の上部において、アルミ電極２４１の上に絶縁膜５０を形成する。
　次に、図１４に示すように、ＩＧＢＴ領域２１２の上部において、アルミ電極２４１上にメタル電極２４２を形成する。メタル電極２４２は、ＩＧＢＴ領域２１２の上部の全域を覆うように形成する。実施の形態１と同様に、メタル電極２４２は、上面が絶縁膜５０の上面よりも高い位置に配置されるように形成する。これにより、凸部２６１を備えた表面構造２６０が形成される。
　次に、図１５に示すように、表面構造２６０の上に、保護膜２８０を貼る。次に、研磨工程を実施し、基板２３０の裏面を研磨する。本実施の形態では、ＩＧＢＴ領域２１２の上部に凸部２６１が形成されている。従って、基板２３０の裏面を研磨することで、凸部２６１と対向する部分が深く研磨される。このため、図１６に示すように、基板２３０のＩＧＢＴ領域２１２が薄く形成される。
　次に、図１７に示すように、裏面工程を実施する。裏面工程では、基板２３０の裏面側に、バッファ層２３５を形成する。次に、バッファ層２３５の裏面にカソード２５６を形成する。次に、写真製版処理によるレジスト注入により、コレクタ２３６を形成する。次に、コレクタ２３６およびカソード２５６の裏面に裏面電極２４３を形成する。以上で、本実施の形態に係る半導体装置２００が形成される。
　本実施の形態に係る半導体装置２００では、ＩＧＢＴ領域２１２の上部に凸部２６１が形成される。従って、研磨工程によって基板２３０のＩＧＢＴ領域２１２がダイオード領域２１１よりも薄く形成される。このため、主電流が流れるＩＧＢＴ領域２１２を低抵抗化することが可能になる。また、終端部２０およびダイオード領域２１１はＩＧＢＴ領域２１２に比べて厚い。従って、強度および耐圧を保持することができる。
　また、ダイオードでは、順バイアス状態からバイアス方向が切り替わった際に、逆方向に電流が流れる期間がある。逆方向に電流が流れる期間であるリカバリー時のサージ電圧は一般に基板が厚いほど発振しにくくなる。本実施の形態では、基板２３０のダイオード領域２１１はＩＧＢＴ領域に比べて厚く形成される。従って、実施の形態１と比較してリカバリー耐量の向上が期待できる。
実施の形態３．
　図１８は、本発明の実施の形態３に係る半導体装置の平面図である。本実施の形態に係る半導体装置３００には、ＩＧＢＴ３９２とダイオード３９１が形成されている。ダイオード３９１はＩＧＢＴ３９２に隣接して形成される。ＩＧＢＴ３９２とダイオード３９１は、終端部２０に囲まれる。終端部２０の構造は、実施の形態１と同様である。また、ＩＧＢＴ３９２の端部には、ＩＧＢＴ３９２のゲート２３４に電力を供給するためのゲートパッド３１３が形成されている。
　図１９は、発明の実施の形態３に係る半導体装置の断面図である。図１９は、図１８に示す半導体装置３００をI-II直線で切断することで得られる断面図である。半導体装置３００は、基板３３０と、基板３３０の上に設けられた表面構造３６０と、基板３３０の裏面に設けられた裏面電極３４３を備える。基板３３０は、セル部３１０とセル部３１０を囲む終端部２０を備える。
　セル部３１０は、ＩＧＢＴ領域３１２と、ＩＧＢＴ領域３１２に隣接して設けられたダイオード領域３１１と、が設けられる。ＩＧＢＴ領域３１２は、セル部３１０のＩＧＢＴ３９２が形成される領域である。また、ダイオード領域３１１は、セル部３１０のダイオード３９１が形成される領域である。
　本実施の形態では、基板３３０は、ドリフト層３３１、表面層２３８および裏面半導体層３３９を備える。表面層２３８の構造は、実施の形態２と同様である。ＩＧＢＴ領域３１２において、ドリフト層３３１の裏面には、Ｎ型のバッファ層３３５が形成される。バッファ層３３５の裏面には、Ｐ型のコレクタ３３６が形成される。また、ダイオード領域３１１において、ドリフト層３３１の裏面には、バッファ層３３５が形成される。バッファ層３３５は、ダイオード領域３１１においてコレクタ３３６から露出している。裏面半導体層３３９は、バッファ層３３５およびコレクタ３３６を含む。
　本実施の形態に係る絶縁層２４６およびアルミ電極２４１の構造は、実施の形態２と同様である。本実施の形態では、ダイオード領域３１１の上部において、アルミ電極２４１上にメタル電極３４２が設けられる。メタル電極３４２は、ダイオード領域３１１の上部の全域に形成される。アルミ電極２４１と、メタル電極３４２は表面電極３４４を形成する。絶縁層２４６、表面電極３４４および絶縁膜５０は表面構造３６０を構成する。メタル電極３４２の上面は、絶縁膜５０の上面よりも高い。このため、表面構造３６０は、ダイオード領域３１１の上部に、上方に突出した凸部３６１を備えることとなる。
　基板３３０の裏面には、裏面電極３４３が設けられる。ここで、バッファ層３３５は、ダイオード領域３１１においてコレクタ３３６から露出している。従って、ダイオード領域３１１では、バッファ層３３５は裏面電極３４３と接触する。本実施の形態では、Ｎ型のバッファ層３３５と裏面電極３４３を接触させることでダイオード３９１を形成している。以上から、半導体装置３００には、トレンチＩＧＢＴであるＩＧＢＴ３９２と、ダイオード３９１が形成される。従って、半導体装置３００は、半導体装置２００と同様にＲＣ－ＩＧＢＴとなる。
　次に、本実施の形態に係る半導体装置３００の製造方法を説明する。図２０～図２５は、本発明の実施の形態３に係る半導体装置の製造方法を示す図である。図２０に示すように、半導体装置３００の製造方法は、絶縁膜５０を形成する工程までは実施の形態２と同様である。
　次に、図２１に示すように、ダイオード領域３１１の上部の全域を覆うように、アルミ電極２４１上にメタル電極３４２を形成する。実施の形態１と同様に、メタル電極３４２は、上面が絶縁膜５０の上面よりも高い位置に配置されるように形成する。
　次に、図２２に示すように、裏面工程を実施する。裏面工程では、裏面半導体層３３９を形成する。まず、基板３３０の裏面側に、バッファ層３３５を形成する。次に、バッファ層３３５の裏面にコレクタ３３６を形成する。
　次に、図２３に示すように、表面構造３６０の上に、保護膜３８０を貼る。次に、研磨工程を実施する。本実施の形態では、裏面工程の後に研磨工程を実施する。したがって、研磨工程では、裏面半導体層３３９が研磨される。本実施の形態では、ダイオード領域３１１の上部において、表面電極３４４が凸部３６１を備える。従って、裏面半導体層３３９の裏面において、凸部３６１と対向する位置が深く研磨される。従って、図２４に示すように、基板３３０のダイオード領域３１１が薄く形成される。研磨工程では、ダイオード領域３１１におけるコレクタ３３６が除去され、バッファ層３３５が露出する様に研磨を行う。
　次に、図２５に示すように、コレクタ３３６の裏面に、裏面電極３４３を形成する。裏面電極３４３は、コレクタ３３６が除去され、バッファ層３３５が露出した部分において、バッファ層３３５と接するように設けられる。以上で、本実施の形態に係る半導体装置３００が形成される。
　実施の形態２では、写真製版処置およびイオン注入を実施して、Ｐ型のコレクタ２３６の一部をＮ型のカソード２５６と置き換えることでダイオード２９１を形成した。これに対し、本実施の形態では、研磨工程でコレクタ３３６の一部を除去することでダイオード３９１を形成する。従って、本実施の形態では、写真製版処理およびエッチングの工程を追加せずに、ダイオード３９１を形成することができる。このため、簡単な工程でＲＣ－ＩＧＢＴを得ることができる。また、セル部３１０の一部が薄くなるため、低抵抗化の効果を得ることができる。
　本実施の形態では、研磨工程でバッファ層３３５を露出させた。この変形例として、研磨工程でドリフト層３３１を露出させても良い。この場合、Ｎ型のドリフト層３３１と裏面電極３４３が接触するように裏面電極３４３を形成する。なお、各実施の形態で説明した技術的特徴は適宜に組み合わせて用いてもよい。
　１００、２００、３００、４００、５００　半導体装置、　１０、２１０、３１０　セル部、　２０　終端部、　３０、２３０、３３０　基板、　６０、２６０、３６０　表面構造、　６１、２６１、３６１、５６１　凸部、　４４、２４４、３４４　表面電極、　４３、２４３、３４３　裏面電極、　２１２、３１２　ＩＧＢＴ領域、　２１１、３１１　ダイオード領域、　５０　絶縁膜、　４５１　隙間、　８０、２８０、３８０　保護膜、　３８、２３８　表面層、　３９、２３９、３３９　裏面半導体層、　３２、２３２　ベース、　３３、２３３　エミッタ、　３４、２３４　ゲート、　３５、２３５、３３５　バッファ層、　３６、２３６、３３６　コレクタ、　２５６　カソード、　２５２　アノード

Claims (18)

  1. 　セル部と、前記セル部を囲む終端部と、を備えた基板と、
    　前記基板の上に設けられた表面構造と、
    　前記基板の裏面に設けられた裏面電極と、
    　を備え、
    　前記表面構造は、前記セル部の上部に、上方に突出した凸部を有し、
    　前記セル部の少なくとも一部は、前記終端部よりも薄いことを特徴とする半導体装置。
  2. 　前記セル部の下の前記裏面電極と、前記終端部の下の前記裏面電極は凹形状を形成し、
    　前記セル部の下の前記裏面電極の下面と、前記終端部の下の前記裏面電極の下面は滑らかに接続されていることを特徴とする請求項１に記載の半導体装置。
  3. 　前記表面構造は、前記基板の上に設けられた表面電極を備え、
    　前記凸部は、前記表面電極の一部であることを特徴とする請求項１または２に記載の半導体装置。
  4. 　前記表面構造は、前記終端部の上部において前記表面電極の上に設けられた絶縁膜を備え、
    　前記絶縁膜と、前記凸部との間には隙間が設けられることを特徴とする請求項３に記載の半導体装置。
  5. 　前記セル部には、ＩＧＢＴ領域と、前記ＩＧＢＴ領域に隣接して設けられたダイオード領域と、が設けられ、
    　前記凸部は、前記ＩＧＢＴ領域の上部に設けられ、
    　前記ＩＧＢＴ領域は、前記ダイオード領域よりも薄いことを特徴とする請求項１～４の何れか１項に記載の半導体装置。
  6. 　前記セル部には、ＩＧＢＴ領域と、前記ＩＧＢＴ領域に隣接して設けられたダイオード領域と、が設けられ、
    　前記凸部は、前記ダイオード領域の上部に設けられ、
    　前記ダイオード領域は、前記ＩＧＢＴ領域よりも薄いことを特徴とする請求項１～４の何れか１項に記載の半導体装置。
  7. 　前記基板はＮ型であり、
    　前記基板は、前記ＩＧＢＴ領域の裏面側にＮ型のバッファ層と、Ｐ型のコレクタと、を備え、前記ダイオード領域の裏面側に前記バッファ層を備えることを特徴とする請求項６に記載の半導体装置。
  8. 　前記凸部は、前記基板よりも薄いことを特徴とする請求項１～７の何れか１項に記載の半導体装置。
  9. 　前記基板は、ワイドバンドギャップ半導体によって形成されていることを特徴とする請求項１～８の何れか１項に記載の半導体装置。
  10. 　前記ワイドバンドギャップ半導体は、炭化珪素、窒化ガリウム系材料またはダイヤモンドであることを特徴とする請求項９に記載の半導体装置。
  11. 　セル部と、前記セル部を囲む終端部と、を備えた基板の表面側に、表面層を形成する表面工程と、
    　前記表面工程の実施後に、前記セル部の上に上方に突出した凸部を有する表面構造を形成する表面構造工程と、
    　前記表面構造を覆うように保護膜を貼り付ける工程と、
    　前記保護膜を貼り付けた状態で、前記基板の裏面を研磨する研磨工程と、
    　前記基板の裏面側に裏面半導体層を形成する裏面工程と、
    　前記研磨工程の実施後に、前記裏面半導体層の裏面に裏面電極を形成する工程と、
    　を備えることを特徴とする半導体装置の製造方法。
  12. 　前記凸部は、前記基板の上に設けられた表面電極の一部であることを特徴とする請求項１１に記載の半導体装置の製造方法。
  13. 　前記表面構造工程では、前記終端部の上部において前記表面電極の上に絶縁膜を設ける工程を備え、
    　前記絶縁膜は、前記凸部との間に隙間を設けて形成されることを特徴とする請求項１２に半導体装置の製造方法。
  14. 　前記表面工程では、前記セル部にベースと、エミッタと、前記ベースに隣接したアノードと、を形成し、
    　前記表面構造工程では、前記ベースおよび前記エミッタの上部に前記凸部を形成し、
    　前記裏面工程では、前記基板にバッファ層を形成し、前記バッファ層の裏面にコレクタと、カソードと、を形成し、
    　前記研磨工程は、前記裏面工程に先んじて実施されることを特徴とする請求項１１～１３の何れか１項に記載の半導体装置の製造方法。
  15. 　前記表面工程では、前記セル部にベースと、エミッタと、前記ベースに隣接したアノードと、を形成し、
    　前記表面構造工程では、前記アノードの上部に前記凸部を形成し、
    　前記裏面工程では、前記基板にバッファ層を形成し、前記バッファ層の裏面にコレクタを形成し、
    　前記研磨工程は、前記裏面工程の後に実施されることを特徴とする請求項１１～１３の何れか１項に記載の半導体装置の製造方法。
  16. 　前記凸部は、前記基板よりも薄く形成されることを特徴とする請求項１１～１５の何れか１項に記載の半導体装置の製造方法。
  17. 　前記基板は、ワイドバンドギャップ半導体によって形成されていることを特徴とする請求項１１～１６の何れか１項に記載の半導体装置の製造方法。
  18. 　前記ワイドバンドギャップ半導体は、炭化珪素、窒化ガリウム系材料またはダイヤモンドであることを特徴とする請求項１７に記載の半導体装置の製造方法。
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