JP7000971B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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JP7000971B2
JP7000971B2 JP2018079227A JP2018079227A JP7000971B2 JP 7000971 B2 JP7000971 B2 JP 7000971B2 JP 2018079227 A JP2018079227 A JP 2018079227A JP 2018079227 A JP2018079227 A JP 2018079227A JP 7000971 B2 JP7000971 B2 JP 7000971B2
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layer
region
semiconductor device
semiconductor substrate
wiring
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JP2019186504A (ja
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拓弥 吉田
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to US16/151,853 priority patent/US10672761B2/en
Priority to DE102019202108.5A priority patent/DE102019202108A1/de
Priority to CN201910295529.3A priority patent/CN110391225B/zh
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Description

本発明は、トランジスタと還流ダイオードを備えた逆導通特性を有する半導体装置に関する。
絶縁ゲートバイポーラトランジスタ（Insulated Gate Bipolar Transistor： IGBT）、パワーＭＯＳＦＥＴ又はダイオード等のパワー半導体装置には、導通状態での定常損失とスイッチング時のスイッチング損失との和からなるパワーロスの低減が求められている。これに対し、デバイス構造設計の最適化を行うことでその市場要求に応えている。これらパワー半導体装置は、一般的にスイッチング素子と、それに逆並列で接続される還流ダイオードを複数個組み合わせたインバータ装置として使用される場合が多い。
逆導通型ＩＧＢＴ（Reverse Conducting Insulated Gate Bipolar Transistor、以下ＲＣ－ＩＧＢＴと記載。）は、ＩＧＢＴと還流ダイオードの機能を１つの半導体基板に集約、即ち１つのチップで形成したものである。通常のＩＧＢＴのチップと還流ダイオードのチップを個々に組み合わせたインバータ回路に比べ、ＲＣ－ＩＧＢＴでインバータ回路を構成するとチップ数を半減でき、小型化、低コスト化を実現できる。このようにパワーロスの低減に加え、小型化と低コスト化を目的としてＲＣ－ＩＧＢＴの開発が進められている。
ＲＣ－ＩＧＢＴにおけるＩＧＢＴと還流ダイオードは、半導体基板の表裏の電極に電圧を印加することで、半導体基板の縦方向に電流が流れるように動作するセル領域に設けられている。セル領域の外周部には、耐圧を保持するための終端領域が配置されている。セル領域と終端領域の間又はセル領域間には配線領域が配置されている。配線領域には、ワイヤボンド用のゲートパッド、及びゲートパッドとセル領域のＩＧＢＴセルのゲートとの間を電気的に接続するゲート配線が設けられている。終端領域及び配線領域には、不純物濃度が高く深さが深い拡散層が設けられ、半導体装置に逆バイアスを印加した際にこれらの領域にかかる電界は緩和される。また、終端領域及び配線領域は、ｐｎｐ又はｎｐｎバイポーラトランジスタを構成して順バイアスを印加した際に電流が流れず、意図的に半導体装置として動作させない無効領域である。
このように無効領域が広いので、所望の性能を得るためにセル領域を拡大させ、半導体装置のサイズを大きくする必要があった。これに対して、配線領域で基板裏面にｎカソード層を形成することで、意図的にダイオードとして動作させ、有効領域を拡大させた構造が提案されている（例えば、特許文献１参照）。これによりダイオードの性能を向上できる。
特開２００９－２６７３９４号公報
しかし、配線領域に終端領域と同様に不純物濃度が高く深さが深いｐ＋ウェル層をアノード層として形成していた。このため、リカバリー電流が増大するという問題があった。これを防ぐために、配線領域に部分的に電子線又はヘリウム線を照射してライフタイムを制御するか、又は別工程で配線領域に低濃度のアノード層を形成することもできるが、製造工程が増加する。また、配線領域及び終端領域において基板表面のｐ層の不純物濃度を低く深さを浅くすると、耐圧が低下し、急峻なスイッチング動作時の破壊等が懸念される。
本発明は、上述のような課題を解決するためになされたもので、その目的は製造工程を増加することなく、リカバリー電流の増大を抑制し、高耐圧・高破壊耐量を実現できる半導体装置を得るものである。
本発明に係る半導体装置は、セル領域と、前記セル領域の外周に配置された終端領域と、前記セル領域と前記終端領域の間又は前記セル領域間に配置された配線領域とを有する半導体基板と、前記セル領域に設けられたＩＧＢＴと、前記配線領域において前記半導体基板の上に設けられた絶縁膜と、前記絶縁膜の上に設けられ、前記ＩＧＢＴのゲートに接続されたゲート電極と、前記終端領域において前記半導体基板の表面に設けられたｐウェル層と、一部が前記配線領域に設けられたダイオードとを備え、前記ダイオードは、前記半導体基板の前記表面に設けられたｐベース層と、前記半導体基板の裏面に設けられたｎカソード層とを有し、前記ダイオードの前記ｐベース層及び前記ｎカソード層の一部が前記配線領域において前記絶縁膜及び前記ゲート電極の下方に設けられ、前記ｐベース層は、前記配線領域と前記セル領域に共通に設けられ、前記ｐウェル層に比べて不純物濃度が低く深さが浅いことを特徴とする。
本発明では、配線領域に設けられたダイオードのｐベース層は、終端領域のｐウェル層に比べて不純物濃度が低く、深さが浅い。これにより、ホールの供給量を低減し、リカバリー電流の増大を抑制できる。また、ダイオードのｐベース層は配線領域とセル領域に共通に設けられているため、ダイオードを形成するために製造工程が増加しない。また、不純物濃度が高く深さが深いｐウェル層を終端領域に形成することで、終端領域にかかる電界集中を抑制し、高耐圧・高破壊耐量を実現できる。
実施の形態１に係る半導体装置の領域を示す上面図である。 実施の形態１に係る半導体基板を示す上面図である。 実施の形態１に係る半導体基板を示す下面図である。 実施の形態１に係る半導体装置を示す断面図である。 比較例に係る半導体装置を示す断面図である。 実施の形態２に係る半導体装置を示す断面図である。 実施の形態３に係る半導体装置を示す断面図である。 実施の形態４に係る半導体装置を示す断面図である。 実施の形態５に係る半導体装置を示す断面図である。 実施の形態６に係る半導体装置を示す断面図である。
実施の形態に係る半導体装置について図面を参照して説明する。同じ又は対応する構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。
実施の形態１．
図１は、実施の形態１に係る半導体装置の領域を示す上面図である。ＲＣ－ＩＧＢＴのセル領域１の外周に、耐圧保持のための終端領域２が配置されている。セル領域１と終端領域２の間又はセル領域１間に配線領域３が配置されている。この配線領域３にゲート配線４及びゲートパッド５が設けられている。また、セル領域１を含む配線領域３で囲まれた領域を、終端領域２と区別するため、活性領域と称する。
図２は、実施の形態１に係る半導体基板を示す上面図である。図３は、実施の形態１に係る半導体基板を示す下面図である。図４は、実施の形態１に係る半導体装置を示す断面図であり、図１～３のＩ－ＩＩに沿った断面図に対応する。セル領域にＩＧＢＴ及び還流ダイオードが設けられている。
半導体基板６のｎ－ドリフト層７は全領域で共通である。セル領域及び配線領域において半導体基板６のｎ－ドリフト層７の上にｐベース層８が設けられている。ＩＧＢＴではｐベース層８の表面にｎ＋エミッタ層９及びｐ＋エミッタ層１０が設けられている。ｎ＋エミッタ層９を貫通するトレンチ内にゲート酸化膜１１を介してポリシリコンからなるトレンチゲート１２が設けられている。還流ダイオードではｐベース層８の表面にｐ＋エミッタ層１０が設けられている。また、耐圧保持のために還流ダイオードにもトレンチを設けているが、ゲートとして機能しないようにトレンチゲート１２とは電気的に分離されている。表面電極１３がｐベース層８、ｎ＋エミッタ層９及びｐ＋エミッタ層１０に接続されている。トレンチゲート１２と表面電極１３とは層間絶縁膜１４によって電気的に分離されている。
なお、還流ダイオードのｐベース層８及びｐ＋エミッタ層１０は、ダイオードのアノード電極として機能する。低コストで製造するために還流ダイオードとＩＧＢＴのｐベース層８及びｐ＋エミッタ層１０は同時に形成される。しかし、性能面を重視して還流ダイオードとＩＧＢＴを個別に形成してもよい。
複数のｐ＋ウェル層１５が終端領域において半導体基板６の表面に部分的に設けられている。図２に示すように、半導体基板６の表面で複数のｐ＋ウェル層１５がセル領域及び配線領域のｐベース層８を囲んでいる。最も内側のｐ＋ウェル層１５はｐベース層８に接する。両者を同電位にすることで、セル領域又は配線領域の終端側にかかる電界集中を緩和させることができる。
配線領域及び終端領域において絶縁膜１６が半導体基板６の上に設けられている。ＩＧＢＴのゲートに接続されたゲート電極１７，１８が絶縁膜１６の上に設けられている。ｐ＋ウェル層１５とゲート電極１７，１８は絶縁膜１６によって電気的に分離されている。ゲート電極１７，１８は図１のゲート配線４又はゲートパッド５に対応する。
全領域で共通にｎ－ドリフト層７の下にｎバッファ層１９が設けられている。ＩＧＢＴと終端領域でｎバッファ層１９の下にｐコレクタ層２０が設けられている。還流ダイオード及び配線領域ではｎバッファ層１９の下にｎ＋カソード層２１が設けられている。全領域で共通にｐコレクタ層２０及びｎ＋カソード層２１の下に裏面電極２３が設けられている。
配線領域において半導体基板６の表面に設けられたｐベース層８と、半導体基板６の裏面に設けられたｎ＋カソード層２１とからダイオードが構成されている。ｐベース層８はｐ＋ウェル層１５に比べて不純物濃度が低く深さが浅い。終端領域では半導体基板６の裏面側にｐコレクタ層２０を設けてｐｎｐバイポーラトランジスタを構成することで、意図的に電流を流さない構造にしている。
続いて、本実施の形態の効果を比較例と比較して説明する。図５は、比較例に係る半導体装置を示す断面図である。比較例では、配線領域に終端領域と同様に不純物濃度が高く深さが深いｐ＋ウェル層１５をアノード層として形成している。このため、リカバリー電流が増大する。これに対して、本実施の形態では、配線領域に設けられたダイオードのｐベース層８は、終端領域のｐ＋ウェル層１５に比べて不純物濃度が低く、深さが浅い。これにより、ホールの供給量を低減し、リカバリー電流の増大を抑制できる。
また、本実施の形態では、ダイオードのｐベース層８は配線領域とセル領域に共通に設けられているため、ダイオードを形成するために製造工程が増加しない。また、不純物濃度が高く深さが深いｐ＋ウェル層１５を終端領域に形成することで、終端領域にかかる電界集中を抑制し、高耐圧・高破壊耐量を実現できる。
実施の形態２．
図６は、実施の形態２に係る半導体装置を示す断面図である。本実施の形態では、不純物濃度が高く、深さが深いｐ＋ウェル層１５からｎ＋カソード層２１までの距離Ｄ１を、ｐ＋ウェル層１５の直下におけるｎ－ドリフト層７の厚みｔ以上にしている。このようにｐ＋ウェル層１５からｎ＋カソード層２１までの距離Ｄ１を広くすることにより、ｎ＋カソード層２１からのホールの供給を抑制でき、リカバリー電流を低減できる。また、ホールが表面のｐ＋ウェル層１５から裏面のｎ＋カソード層２１に向かって拡散していく角度を４５°と考えた場合、ｎ＋カソード層２１からのホールの供給を抑制するには、距離Ｄ１がｎ－ドリフト層７の厚みｔ以上であればよい。
実施の形態３．
図７は、実施の形態３に係る半導体装置を示す断面図である。本実施の形態では、ｐベース層８より不純物濃度が高いｐ＋エミッタ層２４が、配線領域においてｐベース層８の表面に設けられている。これにより、表面電極１３とのコンタクト抵抗を低減でき、順方向損失を低減できる。特に、表面電極１３にＴｉ、ＴｉＮ、ＴｉＷなどのバリアメタルを形成する場合に、接合表面の不純物濃度を高くすることでバリアメタルとの良好なオーミックコンタクトが得られる。
また、ｐ＋エミッタ層２４はｐ＋ウェル層１５から距離Ｄ２だけ離れており、結合しないように両者の間に比較的不純物濃度の低いｐベース層８が設けられている。このため、ｐ＋ウェル層１５からのホールの供給を抑制し、リカバリー電流の増加を抑制することができる。
また、配線領域のｐ＋エミッタ層２４は、ＩＧＢＴ及び還流ダイオードのｐ＋エミッタ層１０と不純物濃度及び深さが同じである。従って、ｐ＋エミッタ層２４はｐ＋エミッタ層１０と同時に形成することができるため、新たな製造工程を必要としない。
実施の形態４．
図８は、実施の形態４に係る半導体装置を示す断面図である。本実施の形態では、ｐ＋エミッタ層２４が、配線領域において表面電極１３と接続する部分に局所的に設けられ、ゲート配線４の下には設けられていない。このようにｐ＋エミッタ層２４を表面電極１３と接合する部分にのみ形成することにより、表面電極１３との良好なオーミックコンタクト性能を維持しつつ、不純物濃度が高いｐ＋エミッタ層２４の体積を削減してリカバリー電流を低減できる。
実施の形態５．
図９は、実施の形態５に係る半導体装置を示す断面図である。本実施の形態では、ｐ＋ウェル層１５からｎ＋カソード層２１までの距離Ｄ１をｎ－ドリフト層７の厚みｔ以上にしている。さらに、ｐベース層８より不純物濃度が高いｐ＋エミッタ層２４が、配線領域においてｐベース層８の表面に設けられている。これにより、実施の形態２及び３の効果を得ることができる。
実施の形態６．
図１０は、実施の形態６に係る半導体装置を示す断面図である。本実施の形態では、ｐ＋ウェル層１５からｎ＋カソード層２１までの距離Ｄ１をｎ－ドリフト層７の厚みｔ以上にしている。さらに、ｐ＋エミッタ層２４が、配線領域において表面電極１３と接続する部分に局所的に設けられ、ゲート配線４の下には設けられていない。これにより、実施の形態２及び４の効果を得ることができる。
なお、半導体基板６は、珪素によって設けられたものに限らず、珪素に比べてバンドギャップが大きいワイドバンドギャップ半導体によって設けられたものでもよい。ワイドバンドギャップ半導体は、例えば、炭化珪素、窒化ガリウム系材料、又はダイヤモンドである。このようなワイドバンドギャップ半導体によって設けられた半導体装置は、耐電圧性や許容電流密度が高いため、小型化できる。この小型化された半導体装置を用いることで、この半導体装置を組み込んだ半導体モジュールも小型化・高集積化できる。また、半導体装置の耐熱性が高いため、ヒートシンクの放熱フィンを小型化でき、水冷部を空冷化できるので、半導体モジュールを更に小型化できる。また、半導体装置の電力損失が低く高効率であるため、半導体モジュールを高効率化できる。
６ 半導体基板、７ ｎ－ドリフト層、８ ｐベース層、１３ 表面電極、１５ ｐ＋ウェル層、１６ 絶縁膜、１７，１８ ゲート電極、２１ ｎ＋カソード層、２４ ｐ＋エミッタ層

Claims (5)

  1. セル領域と、前記セル領域の外周に配置された終端領域と、前記セル領域と前記終端領域の間又は前記セル領域間に配置された配線領域とを有する半導体基板と、
    前記セル領域に設けられたＩＧＢＴと、
    前記配線領域において前記半導体基板の上に設けられた絶縁膜と、
    前記絶縁膜の上に設けられ、前記ＩＧＢＴのゲートに接続されたゲート電極と、
    前記終端領域において前記半導体基板の表面に設けられたｐウェル層と、
    一部が前記配線領域に設けられたダイオードとを備え、
    前記ダイオードは、前記半導体基板の前記表面に設けられたｐベース層と、前記半導体基板の裏面に設けられたｎカソード層とを有し、
    前記ダイオードの前記ｐベース層及び前記ｎカソード層の一部が前記配線領域において前記絶縁膜及び前記ゲート電極の下方に設けられ、
    前記ｐベース層は、前記配線領域と前記セル領域に共通に設けられ、前記ｐウェル層に比べて不純物濃度が低く深さが浅いことを特徴とする半導体装置。
  2. 前記半導体基板において前記ｐベース層と前記ｎカソード層の間にｎドリフト層が設けられ、
    前記ｐウェル層から前記ｎカソード層までの距離は前記ｐウェル層の直下における前記ｎドリフト層の厚み以上であることを特徴とする請求項１に記載の半導体装置。
  3. 一部が前記配線領域の前記絶縁膜の下方において前記ｐベース層の表面に設けられ、前記ｐベース層より不純物濃度が高いｐエミッタ層と、
    前記絶縁膜の下方以外の領域で前記ｐベース層及び前記ｐエミッタ層に接続された表面電極とを更に備え、
    前記ｐエミッタ層は前記ｐウェル層から離れていることを特徴とする請求項１又は２に記載の半導体装置。
  4. 前記ｐエミッタ層は前記表面電極と接続する部分に局所的に設けられていることを特徴とする請求項３に記載の半導体装置。
  5. 前記半導体基板はワイドバンドギャップ半導体によって設けられていることを特徴とする請求項１～４の何れか１項に記載の半導体装置。
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WO2016120999A1 (ja) 2015-01-27 2016-08-04 三菱電機株式会社 半導体装置

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