WO2018010545A1 - 一种异质结终端的碳化硅功率器件及其制备方法 - Google Patents

一种异质结终端的碳化硅功率器件及其制备方法 Download PDF

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WO2018010545A1
WO2018010545A1 PCT/CN2017/090512 CN2017090512W WO2018010545A1 WO 2018010545 A1 WO2018010545 A1 WO 2018010545A1 CN 2017090512 W CN2017090512 W CN 2017090512W WO 2018010545 A1 WO2018010545 A1 WO 2018010545A1
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silicon carbide
power device
anode electrode
heterojunction
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PCT/CN2017/090512
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English (en)
French (fr)
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刘成
叶念慈
黄侯魁
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厦门市三安集成电路有限公司
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Publication of WO2018010545A1 publication Critical patent/WO2018010545A1/zh
Priority to US16/236,806 priority Critical patent/US20190140046A1/en

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Definitions

  • Silicon carbide power device with heterojunction termination and preparation method thereof Silicon carbide power device with heterojunction termination and preparation method thereof
  • the present invention relates to semiconductor devices, and more particularly to a silicon carbide power device having a heterojunction termination and a method of fabricating the same.
  • Power devices based on wide-bandgap semiconductor materials such as silicon carbide (SiC) and gallium nitride (GaN) can provide greater breakdown voltage and power density and are expected to be widely used in next-generation power conversion.
  • SiC power devices due to the discontinuity of the junction, power lines tend to concentrate at the edges of the junction, causing the presence of high electric fields at the junction edges. The presence of a high field will cause an early breakdown of the junction edge, greatly limiting the reverse breakdown voltage of the device. Therefore, in the design and fabrication of SiC power devices, various junction termination techniques are often used to mitigate the edge electric field concentration effect and improve the breakdown voltage of the device.
  • Common junction termination technologies include protection loops, termination junction extensions, and field architectures.
  • SiC power devices are typically based on an N-type SiC substrate and a weak N-type epitaxial layer as a drift region. Accordingly, P-type SiC is used as a junction termination to form a depletion region to disperse the junctional fringe electric field.
  • the P-type SiC region can be fabricated by epitaxial growth and ion implantation.
  • epitaxial growth is the direct growth of P-type SiC on the N-type SiC layer. Since the growth temperature of P-type SiC tends to be high (>150 0 ° C), some P-type impurities (such as Al) are inevitable during the growth process.
  • P-type ion implantation for SiC often requires advanced equipment such as high-temperature ion implanter and ultra-high temperature annealing furnace, and has a complicated process technology and high cost, which restricts its industrial development.
  • the object of the present invention is to overcome the deficiencies of the prior art and provide a silicon carbide power device with a heterojunction termination. And its preparation method.
  • a heterojunction termination silicon carbide power device including a cathode electrode, a substrate layer, an N-type SiC epitaxial layer and an anode electrode from bottom to top, and also including a spacer a plurality of discrete P-type structures formed by heteroepitaxial growth of a P-type semiconductor material having a growth temperature lower than SiC on the N-type SiC epitaxial layer and distributed at least on the periphery of the anode electrode to constitute a heterogeneity End terminal.
  • the growth temperature of the P-type semiconductor material is 600 ° C to 1200 ° C.
  • the P-type semiconductor material is P-type GaN or P-type AlGaN.
  • the P-type structures comprise a plurality of closed loop structures disposed around the periphery of the anode electrode, and the closed loop structures are arranged equidistantly or unequally spaced apart.
  • the anode electrode and the N-type SiC epitaxial layer at least partially form a Schottky contact.
  • the P-type structure further comprises a plurality of discrete structures disposed between the anode electrode and the N-type SiC epitaxial layer.
  • the P-type structure further comprises a layered structure disposed between the anode electrode and the N-type SiC epitaxial layer and isolating the anode electrode and the N-type SiC epitaxial layer.
  • the upper surface of the N-type SiC epitaxial layer is provided with a plurality of grooves, and the P-type structures are correspondingly formed in the grooves.
  • a dielectric layer is further disposed on the N-type SiC epitaxial layer and covers a region other than the anode electrode and the P-type structures located in the region.
  • the dielectric layer is one or a combination of SiN x , Si0 2 , A1 2 0 3 , A1N, wherein X is greater than 0 and less than 1.
  • a method for preparing the above silicon carbide power device comprising the steps of:
  • the growth temperature of the P-type semiconductor material is lower than SiC
  • step 2) selective epitaxial growth, dry etching or wet etching is performed by a mask.
  • the plurality of P-type structures are formed.
  • step 3 a dielectric layer is deposited over the structure obtained in step 2) and a germanium window is etched to form the anode electrode in the germanium window portion.
  • the anode electrode and the cathode electrode are formed by electron beam evaporation, magnetron sputtering, ion evaporation or arc ion deposition, and the Schottky contact is formed by annealing or Advantages of ohmic contact invention
  • [0022] Forming a plurality of spaced apart P-type structures over the N-type SiC epitaxial layer, the P-type structures being distributed at least on the periphery of the anode electrode to form a junction termination structure for dispersing the fringe electric field, the P-type structures It is formed by heteroepitaxial growth of a P-type semiconductor material with a growth temperature lower than that of SiC. Due to the lower growth temperature and different miscellaneous mechanisms, the influence on the miscellaneous properties of the N-type SiC epitaxial layer can be effectively avoided.
  • the silicon carbide device with high breakdown voltage and low device turn-on voltage has good device performance; the same has greatly reduced the requirements for high-temperature complex processes, the process is simple, and the manufacturing cost is reduced.
  • FIG. 1 is a schematic structural view of a first embodiment of the present invention
  • FIG. 2 is a schematic structural view of a second embodiment of the present invention.
  • FIG 3 is a schematic structural view of a third embodiment of the present invention.
  • the silicon carbide power device of the present embodiment is a silicon carbide Schottky barrier diode (SBD) 100, and includes a cathode electrode 110, a substrate layer 120, an N-type SiC epitaxial layer 130, and an anode electrode from bottom to top. 140, wherein the anode electrode 140 forms a metal-semiconductor Schottky contact with the N-type SiC epitaxial layer 130.
  • a plurality of spaced apart P-type structures 150 are formed on the periphery of the anode electrode 140 over the N-type SiC epitaxial layer 130 to form a junction termination. In a region other than the anode electrode 140, the exposed N-type SiC epitaxial layer 130 and the P-type structure 150 are covered with a dielectric layer 160.
  • the P-type structure 150 is formed directly on the N-type SiC epitaxial layer 130 by heteroepitaxial growth from a P-type semiconductor material having a growth temperature lower than that of SiC.
  • the growth temperature of the P-type semiconductor material is between 600 ° C and 1200 ° C, and may be, for example, P-type GaN or P-type AlGaN. Taking P-type GaN as an example, the growth temperature is about 700 ° C, and the conventional SiC growth temperature is above 1500 ° C. At this temperature, the P-type impurity does not penetrate into the N-type SiC epitaxial layer 130.
  • the traits of the N-type SiC epitaxial layer 130 are not affected, thereby maintaining their characteristics, and the obtained device has good overall performance. Further, the impurity concentration of the N-type SiC epitaxial layer 130 is ⁇ 5 ⁇ 10 16 /cm 3 , the impurity concentration of the P-type semiconductor material is >5 ⁇ 10 17 /cm 3 , and the P-type structure 150 forms a depletion region to disperse the junction fringe electric field. . Compared to P-type SiC (>lxl0 i8/cm 3 ), a heterogeneously grown P-type semiconductor can have a lower impurity concentration to achieve the same effect.
  • the P-type structures 150 are a plurality of closed loop structures disposed around the periphery of the anode electrode 140, and the closed loop structures are arranged equidistantly or unequally spaced apart.
  • the arrangement of the closed loop can effectively avoid premature breakdown of the device caused by the high electric field being too concentrated on the SiC main junction.
  • the depletion region is generated at the main junction and expands to the periphery.
  • the potential on the closed loop can effectively assist in further expansion of the depletion region, avoiding electric field concentration due to the small depletion region.
  • the dimensions of the closed loops including thickness, width and spacing need to be determined according to the actual voltage rating of the device (thickness of 130).
  • the thickness of the N-type SiC epitaxial layer 130 is 4 ⁇ 12 ⁇
  • the thickness of the closed ring corresponding to the P-type structure 150 can be 200 ⁇ 800nm
  • the width can be 0.5 ⁇ 10 ⁇
  • the spacing can be In 1 ⁇ 10 ⁇ .
  • the dielectric layer 160 covers a region outside the anode electrode 140 of the diode structure to diffuse an electric field and effectively increase a breakdown voltage.
  • the dielectric layer 160 is a type of SiN x , Si0 2 , A1 2 0 3 , A1N. Or a combination thereof, wherein X is greater than 0 and less than 1.
  • the diode of this embodiment preferably has a substrate of a homogenous SiC substrate, and the anode electrode and the cathode electrode are metals such as Ti, Ni, Pt, Al, Ag, Au, W, Pb, Si, or alloys thereof. Or a layered composite structure thereof.
  • a P-type structure of GaN is taken as an example to describe the fabrication method thereof.
  • a silicon carbide epitaxial structure including a stacked substrate layer and an N-type SiC epitaxial layer is grown on the N-type SiC epitaxial layer by chemical vapor deposition.
  • a P-type GaN layer specifically, trimethylgallium, trimethylaluminum, and ammonia are respectively used as a Ga source, an A1 source, and an N source, and ferrocene is used as a P-type miscellaneous source at a temperature of 700 ° C.
  • the P-type GaN layer is deposited on the N-type SiC epitaxial layer, and the P-type GaN layer is formed by dry etching (for example, ICP or RIE) to define a plurality of discrete P-type structures.
  • the P-type is formed.
  • the structure is a plurality of closed ring structures; then, a dielectric layer is deposited on the surface of the epitaxial structure by chemical vapor deposition, atomic layer deposition, sputtering, etc., and the germanium window is etched; by electron beam evaporation, magnetron sputtering, ion evaporation Or arc ion deposition deposited metal on the back side of the substrate layer to form a cathode electrode, preferably Ti/Ni, and annealed at 1000 ° C for 2 minutes to form an ohmic contact; finally, the etching window of the dielectric layer passes electricity Beam evaporation, magnetron sputtering, ion evaporation or arc ion deposition deposition of metal to form an anode electrode, preferably Ti/Ni, and annealing at 550 ° C for 5 minutes to form a Schottky contact, the thickness of the anode electrode can be greater than The dielectric layer covers a portion of
  • the P-type semiconductor material can also be grown by organic vapor deposition or molecular beam epitaxy, and the patterning can also be achieved by selective epitaxy, for example, by forming a patterned dielectric mask, and by wet etching.
  • the silicon carbide power device of the present embodiment is a silicon carbide junction barrier Schottky diode 200, which differs from Embodiment 1 in that a P-type structure is distributed over the N-type SiC epitaxial layer 230.
  • the P-type structure 251 around the anode electrode 240 forms a heterojunction termination, and further includes a plurality of discrete P-type structures 252 disposed between the anode electrode 240 and the N-type SiC epitaxial layer 230 to form a junction barrier, specifically, a P-type
  • the structure 252 may be a plurality of parallel strip structures, and a plurality of discretely arranged PN junctions are formed between the N-type SiC epitaxial layers 230, and the exposed N-type SiC epitaxial layer 230 between the adjacent P-type structures 252 is in contact with the anode electrode 240.
  • the upper surface of the N-type SiC epitaxial layer 230 is provided with a plurality of grooves 231, and the P-type structures 251 and 252 are correspondingly formed in the grooves. With the depth of the groove, the PN junction is transferred from the SiC surface to the inside, effectively reducing the reverse leakage current without sacrificing the forward conduction voltage drop.
  • the remaining structures, such as the cathode electrode 210, the substrate layer 220, and the dielectric layer 160, are referred to in Embodiment 1.
  • the manufacturing method of the present embodiment further includes the step of etching the upper surface of the N-type SiC epitaxial layer to form the above-mentioned grooves before forming the P-type structure.
  • the junction barrier structure and the junction termination structure are formed simultaneously.
  • the P-type structure 251 is a closed loop
  • the P-type structure 252 is a strip shape, which is patterned by etching or selective epitaxy.
  • the silicon carbide power device of the present embodiment is a silicon carbide PN junction diode 300, which differs from Embodiment 2 in that a P-type structure is distributed on the periphery of the anode electrode 340 except for the N-type SiC epitaxial layer 330.
  • the P-type structure 351 further includes a layered P-type structure 352 disposed between the anode electrode 340 and the N-type SiC epitaxial layer 330 and isolating the anode electrode 340 and the N-type SiC epitaxial layer 330, in addition to forming the heterojunction termination.
  • a P-type structure 352 forms a PN junction with the N-type SiC epitaxial layer 330.

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  • Electrodes Of Semiconductors (AREA)

Abstract

一种异质结终端的碳化硅功率器件(100,200,300)，包括阴极电极(110,210,310)、衬底层(120,220,320)、N型SiC外延层(130,230,330)及阳极电极(140,240,340)，还包括间隔分立的若干P型结构(150,251,252,351,352)，该些P型结构(150,251,252,351,352)由生长温度低于SiC的P型半导体材料通过异质外延生长形成于所述N型SiC外延层(130,230,330)之上并至少分布于阳极电极(140,240,340)***以构成异质结终端，有效避免了对N型SiC外延层(130,230,330)掺杂特性的影响，可以获得高击穿电压及低器件开启电压的碳化硅器件。还公开了其制作方法，减少了对高温复杂工艺的要求，制程简单，减少了制作成本。

Description

一种异质结终端的碳化硅功率器件及其制备方法 技术领域
[0001] 本发明涉及半导体器件， 特别是涉及一种异质结终端的碳化硅功率器件及其制 备方法。
背景技术
[0002] 基于宽禁带半导体材料 (如碳化硅 (SiC)， 氮化镓 (GaN))的功率器件可以提供更 大的击穿电压和功率密度， 有望被广泛应用于下一代电力转换中。 在 SiC功率器 件中， 由于结的不连续性， 电力线往往集中在结的边缘， 造成结边缘处高电场 的存在。 高场的存在将导致结边缘的提早击穿， 极大地限制了器件的反向击穿 电压。 于是在 SiC功率器件的设计及制作中， 往往会采用各式的结终端技术来缓 解边缘电场集中效应， 提高器件的击穿电压。 常见的结终端技术包括保护环、 终端结扩展以及场版结构等。 其中， 保护环、 终端结扩展技术由于不依赖于高 质量的介质材料， 广为实际器件制作所采用。 SiC功率器件一般基于 N型 SiC衬底 和作为漂移区的弱 N型外延层。 相应的， 采用 P型 SiC作为结终端以形成耗尽区来 分散结边缘电场。
技术问题
[0003] 目前， 该 P型 SiC区域的制作可以通过外延生长和离子注入的方式。 其中， 外延 生长是在 N型 SiC层上直接整面生长 P型 SiC， 由于 P型 SiC生长温度往往较高 (>150 0°C)， 在生长过程中不可避免有一些 P型杂质 (如 Al)扩散到弱 N型 SiC中， 对 N型 Si C表面形成自惨杂， 甚至将该区域转化成 P型， 导致 N型 SiC表面惨杂特性改变， 进而影响到低器件幵启电压的获得； 针对 SiC的 P型离子注入往往需要先进的设 备如高温离子注入机和超高温退火炉来完成， 且具有复杂的制程工艺， 成本高 ， 这制约了其产业化发展。
问题的解决方案
技术解决方案
[0004] 本发明的目的在于克服现有技术之不足， 提供一种异质结终端的碳化硅功率器 件及其制备方法。
[0005] 本发明解决其技术问题所采用的技术方案是： 一种异质结终端的碳化硅功率器 件， 由下至上包括阴极电极、 衬底层， N型 SiC外延层及阳极电极， 还包括间隔 分立的若干 P型结构， 该些 P型结构由生长温度低于 SiC的 P型半导体材料通过异 质外延生长形成于所述 N型 SiC外延层之上并至少分布于阳极电极***以构成异 质结终端。
[0006] 优选的， 所述 P型半导体材料的生长温度是 600°C〜1200°C。
[0007] 优选的， 所述 P型半导体材料是 P型 GaN或 P型 AlGaN。
[0008] 优选的， 该些 P型结构包括绕设于所述阳极电极***的若干封闭环结构， 且该 些封闭环结构等距离或不等距离间隔排布。
[0009] 优选的， 所述阳极电极与所述 N型 SiC外延层至少部分形成肖特基接触。
[0010] 优选的， 所述 P型结构还包括设置于阳极电极和 N型 SiC外延层之间的若干分立 结构。
[0011] 优选的， 所述 P型结构还包括设置于阳极电极和 N型 SiC外延层之间并隔离所述 阳极电极和 N型 SiC外延层的层状结构。
[0012] 优选的， 所述 N型 SiC外延层上表面设置有若干凹槽， 该些 P型结构对应形成于 凹槽之内。
[0013] 优选的， 还包括一介质层， 该介质层设置于所述 N型 SiC外延层之上并覆盖所述 阳极电极之外的区域以及位于所述区域的该些 P型结构。
[0014] 优选的， 所述介质层是 SiN x、 Si0 2、 A1 20 3、 A1N的一种或其组合， 其中 X大 于 0小于 1。
[0015] 一种上述碳化硅功率器件的制备方法， 包括以下步骤：
[0016] (1)提供一碳化硅外延结构， 包括层叠的衬底层以及 N型 SiC外延层；
[0017] (2)于 N型 SiC外延层上通过异质外延生长 P型半导体材料并定义形成所述若干间 隔分立的 P型结构， 所述异质外延生长方法包括化学气相沉积法和分子束外延法
， 且所述 P型半导体材料的生长温度低于 SiC;
[0018] (3)于步骤 2)结构的两侧分别制作阳极电极和阴极电极。
[0019] 优选的， 步骤 2)中， 通过掩膜选择性外延生长、 干法蚀刻或湿法蚀刻的方式定 义形成所述若干 P型结构。
[0020] 优选的， 步骤 3)中， 在步骤 2)得到的结构上方沉积一介质层并蚀刻幵窗， 于所 述幵窗部分制作所述阳极电极。
[0021] 优选的， 步骤 3)中， 所述阳极电极和阴极电极通过电子束蒸镀、 磁控溅镀、 离 子蒸镀或电弧离子蒸镀沉积金属形成， 并通过退火形成肖特基接触或欧姆接触 发明的有益效果
有益效果
[0022] 1.于 N型 SiC外延层之上形成若干间隔分立的 P型结构， 该些 P型结构至少分布于 阳极电极***以形成结终端结构以用于分散边缘电场， 该些 P型结构是由生长温 度低于 SiC的 P型半导体材料通过异质外延生长形成的， 由于较低的生长温度及 不同的惨杂机制， 有效避免了对 N型 SiC外延层惨杂特性的影响， 可以获得高击 穿电压及低器件幵启电压的碳化硅器件， 得到的器件性能好； 同吋大大减少了 对高温复杂工艺的要求， 制程简单， 减少了制作成本。
[0023] 2.适用于肖特基势垒二极管 (SBD)、 结势垒肖特基二极管 (JBS)以及 PN结二极管 等， 其中后两者于阳极电极和 N型 SiC外延层之间的 P型惨杂区亦可以与结终端结 构同吋形成， 简化了制程， 适用性广。
对附图的简要说明
附图说明
[0024] 图 1为本发明第一实施例之结构示意图；
[0025] 图 2为本发明第二实施例之结构示意图；
[0026] 图 3为本发明第三实施例之结构示意图。
本发明的实施方式
[0027] 以下结合附图及实施例对本发明作进一步详细说明。 本发明的各附图仅为示意 以更容易了解本发明， 其具体比例可依照设计需求进行调整。 文中所描述的图 形中相对元件的上下关系， 在本领域技术人员应能理解是指构件的相对位置而 言， 因此皆可以翻转而呈现相同的构件， 此皆应同属本说明书所揭露的范围。 此外， 图中所示的元件及结构的个数， 均仅为示例， 并不以此对数目进行限制 ， 实际可依照设计需求进行调整。
[0028] 实施例 1
[0029] 参考图 1， 本实施例的碳化硅功率器件是碳化硅肖特基势垒二极管 (SBD)100， 由下至上包括阴极电极 110、 衬底层 120、 N型 SiC外延层 130及阳极电极 140， 其 中阳极电极 140与 N型 SiC外延层 130形成金属-半导体的肖特基接触。 在 N型 SiC外 延层 130之上阳极电极 140的***具有若干间隔分立的 P型结构 150以形成结终端 。 在阳极电极 140以外的区域， 裸露的 N型 SiC外延层 130以及 P型结构 150之上覆 盖有介质层 160。
[0030] P型结构 150是由生长温度低于 SiC的 P型半导体材料通过异质外延生长直接形成 于 N型 SiC外延层 130之上。 具体的， P型半导体材料的生长温度在 600°C〜1200°C 之间， 例如可以是 P型 GaN或 P型 AlGaN。 以 P型 GaN为例， 其生长温度约为 700°C ， 而常规 SiC生长温度在 1500°C以上， 在此温度下， P型惨杂杂质并不会渗透到 N 型 SiC外延层 130中， 对 N型 SiC外延层 130的惨杂特质不产生影响， 从而保持了其 特性， 得到的器件综合性能好。 进一步， N型 SiC外延层 130的惨杂浓度为 <5xl0 16/cm 3， P型半导体材料的惨杂浓度为 >5xl0 17/cm 3， P型结构 150形成耗尽区来分 散结边缘电场。 相对 P型 SiC(>lxl0 i8/cm 3)， 异质生长的 P型半导体可以具有较低 的惨杂浓度来实现相同的效果。
[0031] 优选的， 该些 P型结构 150是绕设于阳极电极 140***的若干封闭环结构， 且该 些封闭环结构等距离或不等距离间隔排布。 封闭环的设置可以有效地避免高电 场过于集中于 SiC主结而导致的器件过早击穿。 在高压关断状态下， 耗尽区在主 结产生并向周围扩展。 耗尽区在沿着 SiC表面横向的扩展一旦接触到封闭环 150 区域， 该 P型封闭环就会感应到一个电势。 封闭环上的电势可以有效的帮助耗尽 区的进一步扩展， 避免由于耗尽区域较小造成的电场集中。 进一步， 该些封闭 环的尺寸包括厚度、 宽度和间距需要根据实际的器件的耐压等级 (130的厚度)而 定。 针对 600〜1200V耐压规格器件， N型 SiC外延层 130的厚度在 4〜12μηι,对应 P 型结构 150封闭环的厚度可以在 200〜800nm， 宽度可以在 0.5〜10μηι， 间距可以 在 1〜10μηι。
[0032] 介质层 160覆盖该二极管结构上方阳极电极 140之外的区域以扩散电场并有效增 加击穿电压， 优选的， 介质层 160是 SiN x、 Si0 2、 A1 20 3、 A1N的一种或其组合 ， 其中 X大于 0小于 1。
[0033] 本实施例的二极管， 其衬底优选为同质的 SiC衬底， 阳极电极和阴极电极是例 如 Ti、 Ni、 Pt、 Al、 Ag、 Au、 W、 Pb、 Si等金属或其合金或其层状复合结构。
[0034] 以下以 GaN的 P型结构为例说明其制作方法， 首先提供一碳化硅外延结构， 包 括层叠的衬底层以及 N型 SiC外延层， 于 N型 SiC外延层上通过化学气相沉积法生 长 P型 GaN层， 具体， 以三甲基镓、 三甲基铝、 氨分别作为 Ga源、 A1源和 N源， 二茂镁作为 P型惨杂源， 于 700°C的温度下， 上述气体裂解， 于 N型 SiC外延层上 沉积形成 P型 GaN层， 通过干法蚀刻 (例如 ICP或 RIE)该 P型 GaN层以定义形成若干 间隔分立的 P型结构， 本实施例中， 该 P型结构是若干封闭环结构； 接着， 通过 化学气相沉积、 原子层沉积、 溅射等方法在上述外延结构上表面沉积介质层并 蚀刻幵窗； 通过电子束蒸镀、 磁控溅镀、 离子蒸镀或电弧离子蒸镀沉积金属于 衬底层背面制作阴极电极， 优选为 Ti/Ni， 并于 1000°C退火 2分钟形成欧姆接触； 最后， 于介质层的蚀刻窗口通过电子束蒸镀、 磁控溅镀、 离子蒸镀或电弧离子 蒸镀沉积金属制作阳极电极， 优选为 Ti/Ni， 并于 550°C退火 5分钟形成肖特基接 触， 该阳极电极的厚度可大于介质层并覆盖周缘介质层上表面的部分区域。
[0035] 此外， P型半导体材料亦可以通过有机气相沉积或分子束外延法进行生长， 其 图形化亦可以通过选择性外延一例如制作图形化介质掩膜， 以及湿法蚀刻等 方式来实现。
[0036] 实施例 2
[0037] 参考图 2， 本实施例的碳化硅功率器件是碳化硅结势垒肖特基二极管 200， 其与 实施例 1的差别在于， P型结构除了分布于 N型 SiC外延层 230之上阳极电极 240外 围的 P型结构 251以形成异质结终端外， 还包括设置于阳极电极 240和 N型 SiC外延 层 230之间的若干分立 P型结构 252以形成结势垒， 具体， P型结构 252可以是若干 平行的条形结构， 与 N型 SiC外延层 230之间形成若干分立排布的 PN结， 相邻 P型 结构 252之间裸露的 N型 SiC外延层 230与阳极电极 240接触形成肖特基结， 在反向 阻断状态下利用相邻 PN结的耗尽区夹断效应， 获得与 PN二极管类似的阻断特性 ； 在正向导通状态下， 低势垒高度的肖特基结幵启电流， 从而获得与肖特基二 极管类似的导通特性。
[0038] N型 SiC外延层 230上表面设置有若干凹槽 231， 该些 P型结构 251以及 252对应形 成于凹槽之内。 禾 凹槽的深度， PN结由 SiC表面转移到内部， 可在不牺牲正向 导通压降的情况下有效降低反向漏电流。 其余结构， 例如阴极电极 210、 衬底层 220以及介质层 160参照实施例 1。
[0039] 相对于实施例 1， 本实施例的制作方法， 在形成 P型结构之前， 还包括蚀刻 N型 SiC外延层上表面以形成上述凹槽的步骤。 结势垒结构以及结终端结构同吋成型 ， 优选的， P型结构 251是封闭环， P型结构 252是条形， 通过蚀刻或选择性外延 等方式进行图案化。
[0040] 实施例 3
[0041] 参考图 3， 本实施例的碳化硅功率器件是碳化硅 PN结二极管 300， 其与实施例 2 的差别在于， P型结构除了分布于 N型 SiC外延层 330之上阳极电极 340***的 P型 结构 351以形成异质结终端外， 还包括设置于阳极电极 340和 N型 SiC外延层 330之 间并隔离阳极电极 340和 N型 SiC外延层 330的层状 P型结构 352。 P型结构 352与 N 型 SiC外延层 330之间形成 PN结。 其余结构， 例如阴极电极 310、 衬底层 320以及 介质层 360参照实施例 1， 制作方法参考实施例 2， 不加以赘述。
[0042] 上述实施例仅用来进一步说明本发明的一种异质结终端的碳化硅功率器件及其 制备方法， 但本发明并不局限于实施例， 凡是依据本发明的技术实质对以上实 施例所作的任何简单修改、 等同变化与修饰， 均落入本发明技术方案的保护范 围内。

Claims

权利要求书
一种异质结终端的碳化硅功率器件， 由下至上包括阴极电极、 衬底层
， N型 SiC外延层及阳极电极， 其特征在于： 还包括间隔分立的若干 P 型结构， 该些 P型结构由生长温度低于 SiC的 P型半导体材料通过异质 外延生长形成于所述 N型 SiC外延层之上并至少分布于阳极电极*** 以构成异质结终端。
根据权利要求 1所述的异质结终端的碳化硅功率器件， 其特征在于： 所述 P型半导体材料的生长温度是 600°C〜1200°C。
根据权利要求 2所述的异质结终端的碳化硅功率器件， 其特征在于： 所述 P型半导体材料是 P型 GaN或 P型 AlGaN。
根据权利要求 1所述的异质结终端的碳化硅功率器件， 其特征在于： 该些 P型结构包括绕设于所述阳极电极***的若干封闭环结构， 且该 些封闭环结构等距离或不等距离间隔排布。
根据权利要求 1或 4所述的异质结终端的碳化硅功率器件， 其特征在于 ： 所述阳极电极与所述 N型 SiC外延层至少部分形成肖特基接触。 根据权利要求 5所述的异质结终端的碳化硅功率器件， 其特征在于： 所述 P型结构还包括设置于阳极电极和 N型 SiC外延层之间的若干分立 结构。
根据权利要求 1或 4所述的异质结终端的碳化硅功率器件， 其特征在于 ： 所述 P型结构还包括设置于阳极电极和 N型 SiC外延层之间并隔离所 述阳极电极和 N型 SiC外延层的层状结构。
根据权利要求 1所述的异质结终端的碳化硅功率器件， 其特征在于： 所述 N型 SiC外延层上表面设置有若干凹槽， 该些 P型结构对应形成于 凹槽之内。
根据权利要求 1所述的异质结终端的碳化硅功率器件， 其特征在于： 还包括一介质层， 该介质层设置于所述 N型 SiC外延层之上并覆盖所 述阳极电极之外的区域以及位于所述区域的该些 P型结构。
根据权利要求 9所述的异质结终端的碳化硅功率器件， 其特征在于： 所述介质层是 SiN x、 Si0 2、 A1 20 3、 A1N的一种或其组合， 其中 X大 于 0小于 1。
[权利要求 11] 一种如权利要求 1〜10任一项所述的碳化硅功率器件的制备方法， 其 特征在于包括以下步骤：
(1)提供一碳化硅外延结构， 包括层叠的衬底层以及 N型 SiC外延层；
(2)于 N型 SiC外延层上通过异质外延生长 P型半导体材料并定义形成所 述若干间隔分立的 P型结构， 所述异质外延生长方法包括化学气相沉 积法和分子束外延法， 且所述 P型半导体材料的生长温度低于 SiC;
(3)于步骤 2)结构的两侧分别制作阳极电极和阴极电极
[权利要求 12] 根据权利要求 11所述的制备方法， 其特征在于： 步骤 2)中， 通过掩膜 选择性外延生长、 干法蚀刻或湿法蚀刻的方式定义形成所述若干 P型 结构
[权利要求 13] 根据权利要求 11所述的制备方法， 其特征在于： 步骤 3)中， 在步骤 2) 得到的结构上方沉积一介质层并蚀刻幵窗， 于所述幵窗部分制作所述 阳极电极
[权利要求 14] 根据权利要求 11或 13所述的制备方法， 其特征在于： 步骤 3)中， 所述 阳极电极和阴极电极通过电子束蒸镀、 磁控溅镀、 离子蒸镀或电弧离 子蒸镀沉积金属形成， 并通过退火形成肖特基接触或欧姆接触。
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