WO2016142763A1 - Circuit de conversion de puissance et dispositif de conversion de puissance l'utilisant - Google Patents

Circuit de conversion de puissance et dispositif de conversion de puissance l'utilisant Download PDF

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Publication number
WO2016142763A1
WO2016142763A1 PCT/IB2016/000220 IB2016000220W WO2016142763A1 WO 2016142763 A1 WO2016142763 A1 WO 2016142763A1 IB 2016000220 W IB2016000220 W IB 2016000220W WO 2016142763 A1 WO2016142763 A1 WO 2016142763A1
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Prior art keywords
switch
electrically connected
output
power conversion
capacitor
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PCT/IB2016/000220
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English (en)
Japanese (ja)
Inventor
向志 秋政
祐輔 岩松
守雄 中村
後藤　周作
靖久 井原
光武　義雄
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パナソニックＩｐマネジメント株式会社
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Publication of WO2016142763A1 publication Critical patent/WO2016142763A1/fr

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode

Definitions

  • the present invention generally relates to a power conversion circuit and a power conversion device using the same, and more particularly to a power conversion circuit that converts DC power into AC power and a power conversion device using the same.
  • Patent Document 1 Japanese Patent
  • the control circuit (control unit) of Patent Document 1 controls on / off of the switch element of the switching circuit (bridge unit) using a phase shift control method.
  • a power conversion circuit includes a first input terminal and a second input terminal that are electrically connected to a DC power source, respectively, and a first input terminal that is electrically connected to a load.
  • An inverter circuit having one output end and a second output end, a first control unit for controlling the inverter circuit, and a clamp switch electrically connected between the first output end and the second output end And a second control unit that controls the clamp circuit.
  • the inverter circuit includes a first arm including a series circuit of a first switch and a second switch, a third switch, and a fourth switch.
  • a second arm composed of a series circuit, wherein the first arm and the second arm are electrically connected in parallel between the first input end and the second input end, and Switch And a connection point of the second switch is electrically connected to the first output terminal, and a connection point of the third switch and the fourth switch is electrically connected to the second output terminal.
  • a power conversion device includes the above-described power conversion circuit and a housing that houses the power conversion circuit. Advantageous Effects of Invention According to the present invention, it is possible to provide a power conversion circuit that suppresses common mode noise and a power conversion device using the same.
  • FIG. 1 is a circuit diagram illustrating a power conversion circuit according to the first embodiment.
  • FIG. 2 is a diagram illustrating the relationship between the operating state of the switching element and the output voltage of the power conversion circuit according to the first embodiment.
  • 3A to 3C are diagrams for explaining operations in the power conversion circuit according to the first embodiment.
  • 4A to 4C are diagrams for explaining another operation in the power conversion circuit according to the first embodiment.
  • FIG. 5 is a diagram illustrating still another operation in the power conversion circuit according to the first embodiment.
  • FIG. 6 is a diagram illustrating the output voltage of the power conversion circuit of the comparative example of the first embodiment.
  • FIG. 7 is a diagram illustrating the output voltage of the power conversion circuit according to the first embodiment.
  • FIG. 8 is a diagram illustrating the difference between the output voltage of the power conversion circuit according to the first embodiment and the output voltage of the comparative example.
  • FIG. 9 is a circuit diagram showing a power conversion circuit according to a modification of the first embodiment.
  • FIG. 10 is a circuit diagram showing a power conversion circuit according to the second embodiment.
  • FIG. 11 is a circuit diagram showing a power conversion circuit according to a modification of the second embodiment.
  • the power conversion circuit 1 includes an inverter circuit 2, a clamp circuit 4, a (first) capacitor 61, and a (second) capacitor 62.
  • the power conversion circuit 1 includes a first control unit (control unit 3) and a second control unit (control unit 3).
  • the power conversion circuit 1 of the present embodiment further includes a first reactor 51, a second reactor 52, a filter circuit 104, and a filter circuit 105.
  • the power conversion device 100 includes the above-described power conversion circuit 1 and a casing 110 that houses the power conversion circuit 1.
  • the inverter circuit 2 has a (first) input terminal 201 and a (second) input terminal 202 that are electrically connected to a power source 107 (DC power source).
  • the inverter circuit 2 is a circuit that converts DC power supplied from the power source 107 into AC power and outputs the AC power.
  • the inverter circuit 2 of the present embodiment converts a DC voltage input between the input terminals 201 and 202 into an AC voltage and outputs the AC voltage.
  • the power source 107 includes, for example, a power storage device or a solar power generation device, and is configured to output a DC voltage V0.
  • the positive electrode of the power source 107 is electrically connected to the input end 201, and the negative electrode of the power source 107 is electrically connected to the input end 202.
  • the filter circuit 104 is electrically connected between the input terminals 201 and 202.
  • the filter circuit 104 includes a series circuit of capacitors 101 and 102 that are electrically connected between the input terminals 201 and 202.
  • the filter circuit 104 is configured to suppress, for example, radiation noise or conduction noise from the power source 107. Further, the filter circuit 104 suppresses switching noise from the inverter circuit 2 from being transmitted to the power source 107.
  • Capacitors 101 and 102 have the same capacitance and are composed of the same type of capacitors. A voltage V1 that is half the voltage V0 output from the power supply 107 is applied to both ends of each of the capacitors 101 and 102.
  • the housing 110 is made of a metal material and houses the power conversion circuit 1.
  • the housing 110 is configured to have a sufficiently large capacitance with respect to the power conversion circuit 1, and defines a reference potential for the power conversion circuit 1.
  • the reference potential for the power conversion circuit 1 is not limited to being determined by the housing 110.
  • An appropriate member having a sufficiently large capacitance so that the reference potential for the power conversion circuit 1 can be determined may be electrically connected to the connection point 106. That is, the potential at the connection point 106 is equal to the reference potential.
  • the potential at the connection point 106 is described as a reference potential.
  • the voltage V1 that is half of the voltage V0 is applied to both ends of the capacitors 101 and 102.
  • the potential of the input end 201 to which one end of the capacitor 101 is electrically connected is a positive potential that is higher than the reference potential by the voltage V1.
  • the potential of the input terminal 202 to which the other end of the capacitor 102 is electrically connected is a negative potential that is lower than the reference potential by the voltage V1.
  • the inverter circuit 2 includes a series circuit (first arm) of a first switch 21 and a second switch 22 that are electrically connected between the input terminal 201 and the input terminal 202.
  • the inverter circuit 2 includes a series circuit (second arm) of a third switch 23 and a fourth switch 24 that are electrically connected between the input terminal 201 and the input terminal 202.
  • the first switch 21 includes a switching element 211 having a unidirectional conduction direction and a diode 212 connected in reverse parallel to the switching element 211.
  • the second switch 22 includes a switching element 221 having a unidirectional conduction direction and a diode 222 connected in reverse parallel to the switching element 221.
  • the third switch 23 includes a switching element 231 having a one-way conduction direction and a diode 232 connected in reverse parallel to the switching element 231.
  • the fourth switch 24 includes a switching element 241 having a unidirectional conduction direction and a diode 242 connected in reverse parallel to the switching element 241.
  • the diodes 212, 222, 232, and 242 are provided such that the conduction direction is from the input end 202 to the input end 201.
  • the switching elements 211, 221, 231, 241 are constituted by insulated gate bipolar transistors.
  • the switching element having a unidirectional conduction direction may be, for example, a gate turn-off thyristor, a gate commutation type turn-off thyristor, an optical trigger thyristor, or a bidirectional thyristor.
  • each of the first switch 21 to the fourth switch 24 may be a MOSFET (metal-oxide-field-effect transistor) having a parasitic diode.
  • the inverter circuit 2 includes a (first) output terminal 203 and a (second) output terminal 204 that are electrically connected to the load 103.
  • the output terminal 203 is electrically connected to a connection point 205 between the first switch 21 and the second switch 22.
  • the output end 204 is electrically connected to a connection point 206 between the third switch 23 and the fourth switch 24.
  • the connection point 205 is a connection point provided for convenience, and is not limited to the provision of a terminal to which the first switch 21 and the second switch 22 are connected.
  • the connection point 206 is a connection point provided for convenience, and is not limited to the provision of a terminal to which the third switch 23 and the fourth switch 24 are connected.
  • On / off of the first switch 21 to the fourth switch 24 of the inverter circuit 2 is controlled by the control unit 3 described later.
  • the control unit 3 converts the DC voltage into a rectangular AC voltage by periodically turning on and off the first switch 21 and the third switch 23 and the second switch 22 and the fourth switch 24 periodically.
  • One end of the (first) reactor 51 is electrically connected to the output end 203.
  • a connection point 511 is provided at the other end of the reactor 51.
  • One end of the load 103 is electrically connected to the connection point 511.
  • One end of the (second) reactor 52 is electrically connected to the output end 204.
  • a connection point 521 is provided at the other end of the reactor 52.
  • the other end of the load 103 is electrically connected to the connection point 521.
  • a sine wave AC voltage output from the filter circuit 105 is applied between both ends of the load 103.
  • the power conversion circuit 1 of this embodiment further includes a filter circuit 105 connected in parallel with the load 103.
  • the filter circuit 105 includes, for example, a large-capacity capacitor, and smoothes the waveform of the AC voltage V3 output from the inverter circuit 2 to a sine wave AC voltage.
  • the filter circuit 105 suppresses transmission of noise such as radiation noise, conduction noise, and switching noise from the inverter circuit 2 and the clamp circuit 4 to the load 103.
  • the clamp circuit 4 is electrically connected between the output terminals 203 and 204.
  • the clamp circuit 4 has a clamp switch composed of a series circuit of a fifth switch 45 (first clamp switch) and a sixth switch 46 (second clamp switch), and the output terminals 203 and 204 are short-circuited or Open.
  • the fifth switch 45 includes a switching element 451 having a one-way conduction direction (clamping switching element) and a diode 452 (clamping diode) connected in reverse parallel to the switching element 451.
  • the sixth switch 46 includes a switching element 461 (clamping switching element) whose conduction direction is one-way and a diode 462 (clamping diode) connected in reverse parallel to the switching element 461.
  • the diodes 452 and 462 are provided so that the conduction directions are opposite to each other.
  • the clamp circuit 4 has a function of short-circuiting or opening the reactors 51 and 52.
  • Clamp circuit 4 short-circuits reactors 51 and 52 when switching elements 451 and 461 are on.
  • the reactors 51 and 52 are short-circuited, the voltage between the output terminals 203 and 204 is clamped to zero volts, and no voltage is applied from the output terminals 203 and 204 to the load 103 side.
  • the clamp circuit 4 has a function of preventing the output voltage of the inverter circuit 2 from being applied to the load 103.
  • the reactors 51 and 52 release energy as a current, so that a regenerative current flows through the clamp circuit 4 and the load 103.
  • the switching elements 451 and 461 are constituted by insulated gate bipolar transistors in the present embodiment.
  • the switching element having a unidirectional conduction direction may be, for example, a gate turn-off thyristor, a gate commutation type turn-off thyristor, an optical trigger thyristor, or a bidirectional thyristor.
  • the fifth switch and the sixth switch may be MOSFETs having parasitic diodes.
  • the fifth switch 45 and the sixth switch 46 are ON / OFF controlled by the second control unit (control unit 3). When at least one of the fifth switch 45 and the sixth switch 46 is turned on, the reactors 51 and 52 are short-circuited, and a current flowing through the reactors 51 and 52 is caused to flow to the load 103. The operation of the second control unit will be described later.
  • Each of the first switch 21 to the fourth switch 24, the fifth switch 45, and the sixth switch 46 of the present embodiment has a parasitic capacitance, but the illustration of the capacitance component is omitted.
  • a capacitor 61 is electrically connected between the output end 203 and the input end 201.
  • the capacitor 61 of this embodiment is electrically connected directly between the connection point 511 of the reactor 51 and the load 103 and the input terminal 201.
  • the direct connection here means that two components are connected without passing through other elements or circuits.
  • the fact that two components are connected without passing through other elements or circuits is referred to as direct connection.
  • a capacitor 62 is electrically connected between the output end 204 and the input end 202.
  • the second capacitor 62 of the present embodiment is electrically directly connected between the connection point 521 of the reactor 52 and the load 103 and the input end 202.
  • Capacitors 61 and 62 have the same capacitance and are composed of the same type of capacitors.
  • Capacitors 61 and 62 are each composed of a capacitor having an impedance lower than that of load 103. Therefore, when the current flowing between the connection points 511 and 521 changes rapidly, most of the current flows to the capacitors 61 and 62 rather than the load 103.
  • the first control unit controls the inverter circuit 2.
  • the first control unit controls on / off of each of the first switch 21 to the fourth switch 24, converts a DC voltage input between the input terminals 201 and 202 into a rectangular AC voltage, and outputs between the output terminals 203 and 204. Output from.
  • the first control unit controls the on / off timing of each of the first switch 21 to the fourth switch 24 to change the duty ratio of the rectangular AC voltage.
  • the 1st control part of this embodiment is realized by control part 3 mentioned below.
  • the second control unit controls the clamp circuit 4.
  • the clamp circuit 4 of the present embodiment has a clamp switch composed of a series circuit of a fifth switch 45 (first clamp switch) and a sixth switch 46 (second clamp switch). That is, the second control unit controls the switching operation of the fifth switch 45 and the sixth switch 46.
  • the second control unit controls ON / OFF of the fifth switch 45 and the sixth switch 46 to short-circuit the reactors 51 and 52 or to control the direction of current flowing through the reactors 51 and 52.
  • the second control unit controls the current regenerated by the reactors 51 and 52 to bring the waveform of the alternating current supplied to the load 103 closer to a sine wave.
  • the second control unit of the present embodiment is realized by the control unit 3.
  • the first control unit and the second control unit are realized by the control unit 3, but the first control unit and the second control unit may be provided separately.
  • the control unit 3 is composed of a microcomputer.
  • the control unit 3 implements a desired function by reading and executing an appropriate program stored in a memory included in the microcomputer.
  • the control unit 3 has a program that realizes the control functions of the first control unit and the second control unit.
  • the control unit 3 is not limited to being configured by a microcomputer, and may be configured by an IC (Integrated Circuit) or the like.
  • the control unit 3 outputs signals S31 to S36 for ON / OFF control of the switching elements 211, 221, 231, 241, 451, and 461, respectively.
  • the control unit 3 outputs the signal S31 to the gate terminal of the switching element 211, outputs the signal S32 to the gate terminal of the switching element 221, outputs the signal S33 to the gate terminal of the switching element 231, and outputs the signal S33 to the gate terminal of the switching element 241.
  • the control unit 3 outputs a signal S35 to the gate terminal of the switching element 451 and outputs a signal S36 to the gate terminal of the switching element 461.
  • the control unit 3 outputs high level voltage signals as signals S31 to S36, and turns on the corresponding switching elements.
  • the control unit 3 outputs low level voltage signals as signals S31 to S36, and turns off the corresponding switching elements.
  • the control unit 3 may be configured to output a high level voltage signal to turn off the corresponding switching element and output a low level voltage signal to turn on the corresponding switching element. Good.
  • the control unit 3 is not limited to the on / off control of the switching element with the voltage signal, and an appropriate signal such as a current signal may be used.
  • the power source 107, the switching elements and diodes of the inverter circuit 2, the output terminals 203 and 204, the reactors 51 and 52, the load 103 is shown, and the other components are not shown.
  • 3A to 3C, 4A to 4C, and FIG. 5 to be described later, the switching elements in the on state are illustrated surrounded by dotted circles for easy understanding.
  • the control unit 3 is set with first to sixth modes having different operation modes. In each operation mode, the switching elements that are on / off controlled by the control unit 3 are different.
  • the control unit 3 converts the DC voltage into the AC voltage by periodically repeating the first mode to the sixth mode.
  • the control unit 3 In the first mode, the control unit 3 outputs high level signals S31, S34, and S36 to turn on the switching elements 211, 241, and 461.
  • a current I1 flows as shown in FIG. 3A. That is, the current I1 flows in the order of the positive electrode of the power source 107 ⁇ the switching element 211 ⁇ the reactor 51 ⁇ the load 103 ⁇ the reactor 52 ⁇ the switching element 241 ⁇ the negative electrode of the power source 107.
  • Reactors 51 and 52 store energy by current I1.
  • a voltage V4 having a voltage value equal to V0 is applied between the output terminals 203 and 204.
  • the potential at the output end 203 is a positive potential
  • the potential at the output end 204 is a negative potential.
  • the arrow direction of the voltage V4 shown in FIG. 3A (the direction from the output end 204 toward the output end 203) is defined as the positive voltage V4.
  • the first mode is an operation mode in which a positive voltage is applied between the power source 107 and the output terminals 203 and 204.
  • 3A is defined as the forward direction of the current I1 (the direction in which the current flows from the reactor 51 to the load 103). That is, in the first mode, a forward current I1 flows.
  • the control unit 3 turns on the switching element 461. However, the state of the switching element 461 may be maintained in the off state.
  • the control part 3 should just be comprised so that the switching element 461 may be turned on after 1st mode.
  • the controller 3 operates in the second mode after operating in the first mode for a desired period.
  • the second mode is an operation mode in which no voltage is applied between the power supply 107 and the output terminals 203 and 204.
  • the control unit 3 outputs low level signals S31 to S34 to turn off all the switching elements 211, 221, 231, and 241.
  • current I1 flows in the order of reactor 52 ⁇ switching element 461 ⁇ diode 452 ⁇ reactor 51 ⁇ load 103. Since the reactors 51 and 52 release the stored energy as a current, a forward current I1 flows through the load 103.
  • the control unit 3 Since the output terminals 203 and 204 are short-circuited, the voltage V4 is clamped to zero volts.
  • the controller 3 operates in the third mode after repeating the first mode and the second mode for a predetermined period.
  • the third mode is an operation mode in which a reverse voltage is applied between the power source 107 and the output terminals 203 and 204.
  • the control unit 3 outputs low level signals S31 to S36 and turns off all the switching elements 211, 221, 231, 241, 451, and 461.
  • the current I1 flowing in the forward direction flows through the diodes 232 and 222 as shown in FIG. 3C. Therefore, the output terminal 203 and the negative electrode of the power source 107 are electrically connected, and the output terminal 204 and the positive electrode of the power source 107 are electrically connected. That is, a negative voltage V4 (voltage value is ⁇ V0) is applied between the output terminals 203 and 204.
  • V4 voltage value is ⁇ V0
  • the current I1 starts flowing in the reverse direction after flowing in the forward direction until the energy stored in the reactors 51 and 52 becomes zero.
  • the controller 3 operates in the fourth mode after operating in the third mode for a desired period.
  • the control unit 3 outputs high level signals S32, S33, and S35 to turn on the switching elements 221, 231, and 451.
  • a current I1 flows in the order of positive electrode of the power source 107 ⁇ switching element 231 ⁇ reactor 52 ⁇ load 103 ⁇ reactor 51 ⁇ switching element 221 ⁇ negative electrode of the power source 107.
  • Reactors 51 and 52 store energy by current I1.
  • a negative voltage V4 (voltage value is ⁇ V0) is applied between the output terminals 203 and 204.
  • the potential at the output end 203 is a negative potential
  • the potential at the output end 204 is a positive potential.
  • the fourth mode is an operation mode in which a negative voltage V4 (voltage value is ⁇ V0) is applied between the output terminals 203 and 204, and a current I1 in the reverse direction flows.
  • the control unit 3 turns on the switching element 451.
  • the state of the switching element 451 may be maintained in the off state.
  • the control part 3 should just be comprised so that the switching element 451 may be turned on after a 4th mode.
  • the controller 3 operates in the fifth mode after operating in the fourth mode for a desired period.
  • the fifth mode is an operation mode in which no voltage is applied between the power supply 107 and the output terminals 203 and 204.
  • the control unit 3 outputs low level signals S31 to S34 to turn off all the switching elements 211, 221, 231, and 241.
  • the current I1 flows in the order of the reactor 51 ⁇ the switching element 451 ⁇ the diode 462 ⁇ the reactor 52 ⁇ the load 103. Since the reactors 51 and 52 release the stored energy as a current, a current I1 in the reverse direction flows through the load 103. Since the output terminals 203 and 204 are short-circuited, the voltage V4 is clamped to zero volts.
  • the controller 3 operates in the sixth mode after repeating the fourth mode and the fifth mode for a predetermined period.
  • the sixth mode is an operation mode in which a positive voltage is applied between the power source 107 and the output terminals 203 and 204.
  • the control unit 3 outputs low level signals S31 to S36 and turns off all the switching elements 211, 221, 231, 241, 451, and 461.
  • the current I1 flowing in the reverse direction flows through the diodes 212 and 242 as shown in FIG. 4C. Therefore, the output terminal 203 and the positive electrode of the power source 107 are electrically connected, and the output terminal 204 and the negative electrode of the power source 107 are electrically connected. That is, a positive voltage V4 (voltage value is V0) is applied between the output terminals 203 and 204.
  • the current I1 starts flowing in the forward direction after flowing in the reverse direction until the energy stored in the reactors 51 and 52 becomes zero.
  • the inverter circuit 2 outputs the positive voltage V4 (voltage value is V0) or the negative voltage V4 (voltage value is ⁇ V0) between the output terminals 203 and 204.
  • the controller 3 repeats the operations of the first mode and the second mode for a predetermined period, and switches the operation mode in the order of the second mode, the third mode, and the fourth mode.
  • the control unit 3 repeats the operations of the fourth mode and the fifth mode for a predetermined period, and switches the operation mode in the order of the fifth mode, the sixth mode, and the first mode.
  • the control unit 3 repeats the operations of the first mode to the sixth mode, so that a positive rectangular wave voltage and a negative rectangular wave voltage are alternately output from the inverter circuit 2.
  • the control unit 3 performs PWM (Pulse Width Modulation) control on the duty ratio of the rectangular wave voltage, and the rectangular wave voltage is smoothed by the filter circuit 105, whereby the sine wave voltage is applied to the load 103.
  • the control unit 3 is not limited to PWM control of the duty ratio of the rectangular wave voltage between the output terminals 203 and 204.
  • the power conversion circuit 1 should just be comprised so that the alternating voltage output between the output terminals 203 and 204 may be made into a sine wave voltage by an appropriate method.
  • the timing when the switching element 211 is turned off and the timing when the switching element 241 is turned off may be slightly different.
  • the second mode when the switching element 241 is off and the switching element 211 is on, as shown in FIG. 5, the reactor 52 ⁇ the diode 232 ⁇ the switching element 211 ⁇ the reactor 51 ⁇ the load 103.
  • a current I2 flows.
  • the output terminals 203 and 204 are short-circuited to the positive electrode of the power source 107. That is, during the period in which the current I2 flows, the potentials of the output terminals 203 and 204 are higher than the reference potential (the potential at the connection point 106 in FIG.
  • the potential between the output terminals 203 and 204 when the switching element 211 is in the on state and the switching element 241 is in the off state will be described with reference to FIGS. 5, 6, 7, and 8. explain.
  • the potential of the output terminal 203 with respect to the reference potential is denoted as voltage V203
  • the potential of the output terminal 204 with respect to the reference potential is denoted as voltage V204.
  • the voltage V203 is indicated by a solid line
  • the voltage V204 is indicated by a one-dot chain line.
  • the off timing of the switching element 211 may be delayed with respect to the off timing of the switching element 241. For example, as shown in FIG.
  • the output end 204 is short-circuited with the positive electrode of the power source 107 via the diode 232. Therefore, the potentials of the output terminals 203 and 204 are higher than the reference potential (positive potential). Therefore, at time t4, the potentials of the output terminals 203 and 204 are equal to each other in a state of being a positive potential higher than the reference potential. In this case, the voltages V203 and V204 are both the voltage V205. That is, common mode noise is generated such that the potentials of the output terminals 203 and 204 are higher than the reference potential by the voltage V205.
  • the potentials of the output terminals 203 and 204 change in phase with respect to the reference potential.
  • the potential of the output terminal 203 with respect to the reference potential when the common mode noise is generated is expressed as a voltage V206.
  • a waveform of the voltage V206 is shown by a dotted line in FIG. FIG. 8 shows a waveform in which a high level voltage and a low level voltage are alternately output for the voltage V206.
  • the voltage V206 has a waveform in which an AC component due to common mode noise is further added to the high level portion of the rectangular wave voltage. Note that common mode noise may also occur when the on-timing of the switching elements 211 and 241 is shifted.
  • One end of the capacitor 61 is electrically connected to the input end 201. Since the input terminal 201 is electrically connected to the positive electrode of the power source 107, the potential at the input terminal 201 is less likely to fluctuate even when a current flows from the other end of the capacitor 61.
  • One end of the capacitor 62 is electrically connected to the input end 202. Since the input terminal 202 is electrically connected to the negative electrode of the power source 107, the potential at the input terminal 202 is less likely to fluctuate even when a current flows from the other end of the capacitor 62.
  • the voltage waveform of the voltage V203 is shown by changing the time scale of FIG.
  • FIG. 8 shows a voltage waveform in which a high level voltage and a low level voltage are alternately output as the voltage V203. In the voltage V203 indicated by the solid line in FIG.
  • the power conversion circuit 1 of the present embodiment includes the inverter circuit 2, the first control unit (control unit 3 in the present embodiment), the clamp circuit 4, and the second control unit (control in the present embodiment). Unit 3), a first capacitor 61, and a second capacitor 62, which are configured as follows.
  • the inverter circuit 2 includes a first input terminal 201 and a second input terminal 202 that are electrically connected to a DC power supply (power supply 107 in this embodiment), respectively, and a first output that is electrically connected to the load 103. It has an end 203 and a second output end 204.
  • the first control unit controls the inverter circuit 2.
  • the clamp circuit 4 has a clamp switch (in this embodiment, a series circuit of a fifth switch 45 and a sixth switch 46) electrically connected between the first output terminal 203 and the second output terminal 204.
  • the second control unit controls the clamp circuit 4.
  • Inverter circuit 2 further includes a first arm composed of a series circuit of first switch 21 and second switch 22, and a second arm composed of a series circuit of third switch 23 and fourth switch 24. The first arm and the second arm are electrically connected in parallel between the first input end 201 and the second input end 202.
  • a connection point 205 between the first switch 21 and the second switch 22 is electrically connected to the first output terminal 203.
  • a connection point 206 between the third switch 23 and the fourth switch 24 is electrically connected to the second output end 204.
  • the first capacitor 61 is electrically connected between the first output end 203 and the first input end 201.
  • the second capacitor 62 is electrically connected between the second output end 204 and the second input end 202. According to the above configuration, the capacitor 61 is electrically connected between the input end 201 and the output end 203.
  • the potential of the input terminal 201 becomes a stable potential (positive potential in this embodiment) by the power source 107.
  • the capacitor 62 is electrically connected between the input end 202 and the output end 204.
  • the potential of the input terminal 202 becomes a stable potential (negative potential in this embodiment) by the power source 107.
  • Each of the first switch 21 to the fourth switch 24 in the power conversion circuit 1 of the present embodiment may include switching elements 211, 221, 231, 241 and diodes 212, 222, 232, 242.
  • the switching elements 211, 221, 231, and 241 are unidirectional switching elements.
  • the diodes 212, 222, 232, and 242 are connected in antiparallel with the switching elements 211, 221, 231, 241.
  • the diodes 212, 222, 232, and 242 of each of the first switch 21 to the fourth switch 24 are preferably provided so that the conduction direction is the direction from the second input end 202 to the first input end 201. According to the above configuration, even when the switching elements of each of the first switch 21 to the fourth switch 24 are in the OFF state, the current flows in the forward direction of the diode of each of the first switch 21 to the fourth switch 24. Each of the first switch 21 to the fourth switch 24 is turned on.
  • the clamp switch in the power conversion circuit 1 of the present embodiment may include a series circuit of a first clamp switch (fifth switch 45) and a second clamp switch (sixth switch 46).
  • the first clamp switch (fifth switch 45) includes a clamp switching element (switching element 451 in the present embodiment) and a clamp diode (diode 452 in the present embodiment).
  • the second clamp switch (sixth switch 46) includes a clamp switching element (switching element 461 in the present embodiment) and a clamp diode (diode 462 in the present embodiment).
  • the clamp switching elements (switching elements 451 and 461) are clamp switching elements whose conduction direction is one-way.
  • the clamping diodes (diodes 452 and 462) are connected in antiparallel with the clamping switching elements (switching elements 451 and 461).
  • the clamp diodes (diodes 452 and 462) of the first clamp switch (fifth switch 45) and the second clamp switch (sixth switch 46) are provided so that the conducting directions are opposite to each other. Is also preferable.
  • the control unit 3 may turn on one of the clamp switching elements of the first clamp switch and the second clamp switch. Moreover, the control part 3 can short-circuit or open
  • the power conversion circuit 1 of the present embodiment is electrically connected between the first reactor 51 electrically connected between the first output end 203 and the load 103, and between the second output end 204 and the load 103. It is also preferable to further include a second reactor 52 to be provided.
  • the first capacitor 61 is electrically connected between the connection point 511 of the first reactor 51 and the load 103 and the first input terminal 201.
  • the second capacitor 62 is also preferably electrically connected between the connection point 521 of the second reactor 52 and the load 103 and the second input end 202.
  • one end of each of the capacitors 61 and 62 is electrically connected to the reactors 51 and 52, and the other end of each of the capacitors 61 and 62 is connected to the power source 107.
  • the power conversion device 100 includes the above-described power conversion circuit 1 and a casing 110 that houses the power conversion circuit 1. According to the said structure, the power converter device 100 which can suppress common mode noise is realizable.
  • the capacitors 61 and 62 are directly electrically connected to the connection points 511 and 521, respectively, but the present invention is not limited to this configuration. As shown in FIG.
  • the capacitor 61 may be directly connected between a connection point 501 between the output end 203 and the reactor 51 and a connection point 502 between the output end 204 and the reactor 52.
  • the power conversion circuit 1 in which the capacitors 61 and 62 are directly connected between the connection points 501 and 502 will be described as a modification of the present embodiment.
  • the connection points 501 and 502 are connection points provided for convenience, and the connection points 501 and 502 are not limited to being provided.
  • the capacitor 61 is electrically connected directly between the output end 203 and the connection point 501 of the reactor 51 and the input end 201.
  • the capacitor 62 is electrically connected directly between the connection end 502 of the output end 204 and the reactor 52 and the input end 202.
  • one ends of the capacitors 61 and 62 are electrically directly connected to the load 103 side of the reactors 51 and 52.
  • the power conversion circuit 1A according to the modified example is different in that one end of the capacitors 61 and 62 is electrically directly connected to the clamp circuit 4 side of the reactors 51 and 52.
  • a capacitor 61 and a reactor 51 are connected in series between the input terminal 201 and one end of the load 103.
  • a capacitor 62 and a reactor 52 are connected in series between the input end 202 and the other end of the load 103.
  • the reactors 51 and 52 suppress output of the high voltage to the load 103 side.
  • the capacitances of the capacitors 61 and 62 and the types of the capacitors are all the same, but are not limited to this configuration.
  • common mode noise can be reduced by appropriately combining capacitors having different capacitances or different types of capacitors.
  • Each of the first switch 21 to the fourth switch 24 may not include a switching element having a unidirectional conduction direction and a diode connected in reverse parallel to the switching element.
  • a switching element having a parasitic diode such as a MOSFET may be used.
  • the control unit 3 controls the on / off states of the first switch 21 to the fourth switch 24 so that a desired electric circuit is formed between the input terminals 201 and 202 and the output terminals 203 and 204.
  • the clamp switch may not include a series circuit of the first clamp switch (fifth switch 45) and the second clamp switch (sixth switch 46). In that case, the clamp switch only needs to have a function of turning on and off a bidirectional current by short-circuiting or opening both ends.
  • switching elements having parasitic diodes such as MOSFETs may be connected in parallel so that the conduction directions of the parasitic diodes are opposite to each other.
  • Each of the first clamping switch (fifth switch 45) and the second clamping switch (sixth switch 46) is connected in reverse parallel to the clamping switching element and the clamping switching element whose conduction direction is unidirectional. It does not have to have a diode for use. In that case, each of the first clamp switch and the second clamp switch may have a function of turning on and off a bidirectional current by short-circuiting or opening both ends of the clamp switch.
  • Embodiment 2 A power conversion circuit 1B according to the present embodiment will be described with reference to FIG. In addition, about the structure similar to Embodiment 1, the same code
  • the power conversion circuit 1B of the present embodiment further includes current limiting units 81 to 84 having a desired impedance.
  • the current limiters 81 to 84 have two terminals.
  • Each of the current limiters 81 to 84 has at least one of a resistance component and a reactance component between two terminals, and is configured to have a desired impedance at a desired frequency.
  • the current limiting units 81 and 82 are configured to have the same impedance.
  • the current limiting units 83 and 84 are configured to have the same impedance.
  • Each of the current limiters 81 and 82 is configured such that a predetermined primary side impedance is provided between the two terminals.
  • the current limiting unit 81 (first input side current limiting unit) is electrically connected between the input terminal 201 and the capacitor 61.
  • the current limiting unit 82 (second input side current limiting unit) is electrically connected between the input terminal 202 and the capacitor 62.
  • Each of the current limiting units 83 and 84 is configured such that a predetermined secondary side impedance is provided between the two terminals.
  • the current limiting unit 83 (first output side current limiting unit) is electrically connected between the connection point 511 and the capacitor 61.
  • the current limiting unit 84 (second output side current limiting unit) is electrically connected between the connection point 521 and the capacitor 62.
  • the current limiters 81 to 84 have at least one of a resistance component and a reactance component, and are configured to have a desired impedance at a desired frequency.
  • the current limiting units 81 and 82 are configured to have the same impedance.
  • the current limiting units 83 and 84 are configured to have the same impedance. Radiation noise output to the load 103 side can be suppressed by reducing the current value of the current flowing through the capacitors 61 and 62 by the current limiters 81 to 84, respectively. Further, by adjusting the impedance of each of the current limiting portions 81 to 84, the effect of the capacitors 61 and 62 suppressing common mode noise can be changed.
  • each of the current limiters 81 to 84 by adjusting the impedance of each of the current limiters 81 to 84 so that the impedance is reduced at a desired frequency, it is possible to suppress the noise component of the desired frequency among the common mode noise.
  • the impedance of each of the current limiting units 81 to 84 by adjusting the impedance of each of the current limiting units 81 to 84, the frequency band of radiation noise when current flows from the output terminals 203 and 204 to the input terminals 201 and 202 via the capacitors 61 and 62 is adjusted. Can be changed. Therefore, it is possible to suppress radiation noise of a desired frequency among radiation noises from currents flowing through the capacitors 61 and 62 while suppressing noise components of a desired frequency of common mode noise using the current limiting units 81 to 84.
  • the power conversion circuit 1B of the present embodiment includes the current limiter 81 (first input side current limiter) and the current limiter 82 (second input side current limit) each having a predetermined primary impedance. It is also preferable that the apparatus is further configured as follows.
  • the current limiting unit 81 (first input side current limiting unit) is electrically connected between the first input terminal 201 and the first capacitor 61.
  • the current limiting unit 82 (second input side current limiting unit) is electrically connected between the second input terminal 202 and the second capacitor 62. According to the above configuration, the current limiting units 81 and 82 can suppress the radiation noise output to the load 103 side by reducing the current value of the current flowing through the capacitors 61 and 62, respectively.
  • the power conversion circuit 1B of the present embodiment further includes a current limiting unit 83 (first output side current limiting unit) and a current limiting unit 84 (second output side current limiting unit) each having a predetermined secondary impedance, It is also preferable to be configured as follows.
  • Current limiting unit 83 first output-side current limiting unit
  • Current limiting unit 84 second output side current limiting unit
  • the current limiting unit 84 (second output side current limiting unit) is electrically connected between the second reactor 52 and the connection point 521 of the load 103 and the second capacitor 62. According to the above configuration, the current limiting units 83 and 84 can suppress the radiation noise output to the load 103 side by reducing the current value of the current flowing through the capacitors 61 and 62, respectively. Further, by adjusting the impedances of the current limiting units 83 and 84 so that the impedance is reduced at a desired frequency, it is possible to suppress a noise component having a desired frequency in the common mode noise.
  • a power conversion circuit 1C in which capacitors 61 and 62 are electrically connected between the input and output terminals of the inverter circuit 2 and further includes current limiting units 81 to 84 is provided. This will be described as a modification. Note that the configuration of the current limiting units 81 and 82 is the same as that of the present embodiment, and a description thereof will be omitted.
  • the capacitor 61 is electrically connected between the output end 203 and the input end 201 as shown in FIG.
  • the capacitor 62 is electrically connected between the output end 204 and the input end 202.
  • the current limiting unit 83 is electrically connected between the output end 203 and the capacitor 61.
  • the current limiting unit 84 is electrically connected between the output end 204 and the capacitor 62.
  • the power conversion circuit 1C includes the current limiting unit 83 (first output side current limiting unit) and the current limiting unit 84 (second output side current limiting unit) each having a predetermined secondary side impedance. It is also preferable to be configured as follows.
  • the current limiting unit 83 (first output side current limiting unit) is electrically connected between the first output terminal 203 and the first capacitor 61.
  • the current limiting unit 84 (second output side current limiting unit) is electrically connected between the second output end 204 and the second capacitor 62.
  • the current limiting units 83 and 84 can suppress the radiation noise output to the load 103 side by reducing the current value of the current flowing through the capacitors 61 and 62, respectively. Further, by adjusting the impedance of each of the current limiting units 83 and 84, radiation noise from the current flowing through the capacitors 61 and 62 can be suppressed.
  • the current limiting units 81 and 82 are determined to have the same impedance, and the current limiting units 83 and 84 are determined to have the same impedance. It is not limited.
  • the impedances of the current limiters 81 to 84 may be set to appropriate values individually. Further, each of the current limiting units 81 to 84 may be omitted as appropriate.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Abstract

L'invention concerne un circuit de conversion de puissance 1 qui est pourvu d'un circuit inverseur 2, d'une unité de commande 3, d'un circuit de fixation de niveau 4 et de condensateurs 61, 62. Le circuit inverseur 2 comprend des bornes d'entrée 201, 202 et des bornes de sortie 203, 204. L'unité de commande 3 commande le fonctionnement du circuit inverseur 2 et du circuit de fixation de niveau 4. Le circuit de fixation de niveau 4 forme un court-circuit ou un circuit ouvert entre les bornes de sortie 203, 204. Le condensateur 61 est connecté électriquement entre la borne de sortie 203 et la borne d'entrée 201. Le condensateur 62 est connecté électriquement entre la borne de sortie 204 et la borne d'entrée 202.
PCT/IB2016/000220 2015-03-11 2016-03-02 Circuit de conversion de puissance et dispositif de conversion de puissance l'utilisant WO2016142763A1 (fr)

Applications Claiming Priority (2)

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JP2015-048565 2015-03-11
JP2015048565A JP6516182B2 (ja) 2015-03-11 2015-03-11 電力変換回路およびそれを用いた電力変換装置

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CN109831930A (zh) * 2016-09-30 2019-05-31 日本电产艾莱希斯株式会社 马达驱动装置以及电动助力转向***
JP6394760B1 (ja) * 2017-07-27 2018-09-26 オムロン株式会社 電力変換装置及び電力変換装置の制御方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012065515A (ja) * 2010-09-17 2012-03-29 Toshiba Corp 電力変換装置のスイッチング方法
JP2014209841A (ja) * 2013-03-28 2014-11-06 パナソニック株式会社 インバータ装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012065515A (ja) * 2010-09-17 2012-03-29 Toshiba Corp 電力変換装置のスイッチング方法
JP2014209841A (ja) * 2013-03-28 2014-11-06 パナソニック株式会社 インバータ装置

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