WO2014097714A1 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
WO2014097714A1
WO2014097714A1 PCT/JP2013/077551 JP2013077551W WO2014097714A1 WO 2014097714 A1 WO2014097714 A1 WO 2014097714A1 JP 2013077551 W JP2013077551 W JP 2013077551W WO 2014097714 A1 WO2014097714 A1 WO 2014097714A1
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film
metal film
substrate
interface
laser beam
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PCT/JP2013/077551
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English (en)
French (fr)
Japanese (ja)
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輝尚 川▲崎▼
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住友重機械工業株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/048—Making electrodes
    • H01L21/0485—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
    • H01L29/66204—Diodes
    • H01L29/66212—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device in which a metal silicide film is formed on the surface of a substrate made of silicon carbide (SiC).
  • SiC having a wider band gap than silicon has been attracting attention.
  • a vertical semiconductor device typified by a Schottky barrier diode
  • an element structure is formed on one surface, and an ohmic electrode is formed on the other surface (back surface).
  • a metal silicide such as nickel silicide is used as the ohmic electrode.
  • the metal silicide is formed by performing rapid thermal annealing (RTA) or the like after forming a metal film on the back surface.
  • an element structure is formed on one surface of an SiC substrate and then the other surface (back surface) is ground to thin the substrate.
  • the element resistance can be reduced.
  • the metal silicide film must be formed on the back surface of the substrate after the element structure is formed and the substrate is thinned. For this reason, the element structure formed on one surface of the substrate is affected by heat when the metal silicide film is formed on the other surface (back surface).
  • the electrical characteristics of the semiconductor power device may deteriorate.
  • An object of the present invention is to provide a manufacturing method in which an element structure formed on one surface of a substrate is hardly affected by heat generated during heat treatment for forming a metal silicide film.
  • a metal film made of nickel or titanium on a first surface of a substrate made of silicon carbide Irradiating the metal film with a pulsed laser beam having a wavelength in the ultraviolet region to cause a silicide reaction at the interface between the substrate and the metal film, thereby forming a metal silicide film,
  • a method of manufacturing a semiconductor device is provided in which the pulse laser beam is irradiated under a condition that the surface of the metal film does not melt.
  • FIGS. EA to 1F are cross-sectional views of a substrate in the course of manufacturing a semiconductor device manufacturing method according to an embodiment.
  • FIGS. EA to 1F are cross-sectional views of the substrate in the middle of the manufacturing process of the semiconductor device manufacturing method according to the embodiment.
  • FIG. 2A is a graph showing a simulation result of the relationship between the maximum temperature at the interface between the substrate and the nickel film and the thickness of the nickel film when annealing is performed under the condition of a pulse width of 10 ns
  • FIG. It is a graph which shows the simulation result of the relationship between the maximum ultimate temperature of the surface of a nickel film, and the thickness of a nickel film.
  • FIG. 3A is a graph showing a simulation result of the relationship between the maximum temperature at the interface between the substrate and the nickel film and the thickness of the nickel film when annealing is performed under the condition of a pulse width of 20 ns
  • FIG. It is a graph which shows the simulation result of the relationship between the maximum ultimate temperature of the surface of a nickel film, and the thickness of a nickel film.
  • FIG. 4A is a graph showing a simulation result of the relationship between the maximum temperature at the interface between the substrate and the nickel film and the thickness of the nickel film when annealing is performed under the condition of a pulse width of 30 ns. It is a graph which shows the simulation result of the relationship between the maximum ultimate temperature of the surface of a nickel film, and the thickness of a nickel film.
  • FIG. 5A is a graph showing a simulation result of the relationship between the maximum temperature at the interface between the substrate and the nickel film and the thickness of the nickel film when annealing is performed under the condition of a pulse width of 50 ns
  • FIG. It is a graph which shows the simulation result of the relationship between the maximum ultimate temperature of the surface of a nickel film, and the thickness of a nickel film.
  • FIG. 6A is a graph showing a simulation result of the relationship between the maximum temperature at the interface between the substrate and the titanium film and the thickness of the titanium film when annealing is performed under the condition of a pulse width of 10 ns
  • FIG. It is a graph which shows the simulation result of the relationship between the maximum ultimate temperature of the surface of a titanium film, and the thickness of a titanium film.
  • FIGS. 1A to 1F a method of manufacturing a semiconductor device according to an embodiment will be described.
  • a p-type guard ring 11 is formed in one surface layer portion of a substrate 10 made of n-type SiC by ion implantation.
  • the surface opposite to the surface on which the guard ring 11 is formed is referred to as a “first surface” 10A, and the surface on which the guard ring 11 is formed is referred to as a “second surface” 10B.
  • an insulating film 12 made of silicon oxide is formed on the second surface 10B.
  • the insulating film 12 has an opening that exposes a region surrounded by the guard ring 11.
  • a Schottky electrode 13 is formed on the surface of the substrate 10 exposed at the bottom surface of the opening formed in the insulating film 12.
  • Schottky contact is realized by performing a heat treatment after forming a titanium film.
  • a surface electrode 14 is formed on the Schottky electrode 13.
  • aluminum is used for the surface electrode 14.
  • the guard ring 11, the Schottky electrode 13, and the surface electrode 14 are referred to as “element structure” 15.
  • the substrate 10 is thinned by grinding the substrate 10 from the first surface 10A.
  • a metal film 16 is formed on the first surface 10A of the substrate 10.
  • the metal film 16 for example, nickel (Ni) or titanium (Ti) is used.
  • laser annealing is performed by irradiating the metal film 16 with a pulse laser beam 20. This laser annealing is performed while moving the incident region of the pulse laser beam 20 within the surface of the metal film 16.
  • the overlap ratio of the incident region is, for example, 50% to 90%.
  • a metal silicide film 17 is formed at the interface between the substrate 10 and the metal film 16.
  • This laser annealing is performed under the condition that the surface of the metal film 16 does not melt. When the surface of the metal film 16 is melted, the surface of the metal film 16 becomes rough after solidification. In the method according to the embodiment, since the annealing is performed under the condition that the surface of the metal film 16 is not melted, the surface roughness of the metal film 16 can be suppressed. Performing silicidation at the interface without melting the surface of the metal film is referred to as “non-molten silicidation”.
  • the pulse width of the pulse laser beam 20 is shorter than the heating time by rapid thermal annealing (RTA).
  • RTA rapid thermal annealing
  • the pulsed laser beam 20 having a wavelength range that does not transmit through the substrate 10 is used, the pulsed laser beam does not reach the element structure 15 formed on the second surface 10B. For this reason, the temperature rise of the 2nd surface 10B of the board
  • the annealing method according to the embodiment is employed, the temperature rise of the element structure 15 can be suppressed as compared with the case where RTA is employed.
  • FIG. 3A, FIG. 4A, and FIG. 5A show the relationship between the maximum temperature reached at the interface between the substrate and the nickel film (hereinafter simply referred to as “interface”) and the thickness of the nickel film.
  • the horizontal axis represents the thickness of the nickel film in the unit “nm”, and the vertical axis represents the maximum temperature reached at the interface in the unit “° C.”.
  • 2B, FIG. 3B, FIG. 4B, and FIG. 5B show the relationship between the maximum temperature reached on the surface of the nickel film (hereinafter simply referred to as “surface”) and the thickness of the nickel film.
  • the horizontal axis represents the thickness of the nickel film in the unit “nm”, and the vertical axis represents the maximum surface temperature of the surface in the unit “° C.”.
  • 2A and 2B show simulation results when the pulse width Pw of the pulse laser beam is 10 ns.
  • 3A and 3B show simulation results when the pulse width Pw of the pulse laser beam is 20 ns.
  • 4A and 4B show simulation results when the pulse width Pw of the pulse laser beam is 30 ns.
  • 5A and 5B show simulation results when the pulse width Pw of the pulse laser beam is 50 ns.
  • the rhombus symbol, square symbol, triangle symbol, and circle symbol in FIGS. 2A and 2B each have a pulse energy density (hereinafter simply referred to as “pulse energy density”) of 1.2 J / cm 2 on the surface of the nickel film. This corresponds to the case where laser annealing is performed under the conditions of 3 J / cm 2 , 1.4 J / cm 2 , and 1.5 J / cm 2 .
  • the rhombus, square, triangle, and circle symbols in FIGS. 3A and 3B have pulse energy densities of 1.6 J / cm 2 , 1.7 J / cm 2 , 1.8 J / cm 2 , and 1.9 J, respectively.
  • the rhombus, square, triangle, and circle symbols in FIGS. 4A and 4B have pulse energy densities of 1.8 J / cm 2 , 2.0 J / cm 2 , 2.2 J / cm 2 , and 2.4 J, respectively. This corresponds to the case where laser annealing is performed under the condition of / cm 2 .
  • the rhombus, square, triangle, and circle symbols in FIGS. 5A and 5B have pulse energy densities of 2.4 J / cm 2 , 2.6 J / cm 2 , 2.8 J / cm 2 , and 3.0 J, respectively. This corresponds to the case where laser annealing is performed under the condition of / cm 2 .
  • the “pulse energy density” is obtained by dividing the energy per pulse of the pulse laser beam by the area of the beam cross section.
  • the area of a region surrounded by a closed curve connecting positions where the light intensity is 1 ⁇ 2 of the maximum value in the beam cross section is adopted as the “area of the beam cross section”.
  • the maximum temperature at the interface does not reach 950 ° C. when the thickness of the nickel film is about 20 nm or less. This is because the substrate made of SiC acts as a heat sink and heat is not accumulated at the interface.
  • the thickness of the nickel film is 30 nm or more, the maximum temperature reached at the interface becomes 950 ° C. or more within a pulse energy density of at least 1.3 to 1.5 J / cm 2 .
  • the pulse energy density is made higher, there will be an annealing condition that makes the maximum temperature at the interface more than 950 ° C. even if the thickness of the nickel film is less than 20 nm.
  • the thickness of the nickel film is preferably 30 nm or more.
  • the maximum temperature at the interface decreases as the film thickness increases.
  • the maximum temperature at the interface can be 950 ° C. or more.
  • the maximum temperature at the interface can be made 950 ° C. or more by adjusting the pulse energy density.
  • the maximum surface temperature increases as the nickel film becomes thicker. This is because when the nickel film is thin, the temperature rise of the surface of the nickel film is suppressed by the heat sink effect of the substrate, and when the nickel film is thick, the heat sink effect of the substrate is weakened.
  • the surface temperature of the nickel film exceeds 1455 ° C., which is the melting point of nickel, the surface is melted. In order to avoid melting of the surface, it is preferable to perform annealing under the condition that the maximum surface temperature is 1455 ° C. or less.
  • the maximum temperature reached at the interface can be made 950 ° C. or more.
  • the pulse energy density of the pulse laser beam to be irradiated is set in a range lower than the magnitude at which the maximum temperature reached on the surface of the nickel film is equal to the melting point of nickel.
  • the maximum temperature at the interface can be set to 950 ° C. or more within the thickness range of 30 nm to 250 nm.
  • the maximum temperature at the interface can be set to 950 ° C. or more within the thickness range of 30 nm to 250 nm of the nickel film.
  • the maximum temperature at the interface is set to 950 ° C. or more, and The maximum temperature reached on the surface can be made 1455 ° C. or lower.
  • the maximum temperature at the interface can be set to 950 ° C. or more within the thickness range of 30 nm to 200 nm.
  • the maximum temperature at the interface can be made 950 ° C. or higher.
  • the maximum temperature reached at the interface can be set to 950 ° C. or more within the thickness range of the nickel film of 30 nm to 200 nm.
  • the maximum temperature at the interface can be made 950 ° C. or more by adjusting the pulse energy density.
  • the maximum temperature at the interface is set to 950 ° C. or more, and The maximum temperature reached on the surface can be made 1455 ° C. or lower.
  • the maximum temperature at the interface can be set to 950 ° C. or more within the thickness range of 30 nm to 250 nm.
  • the maximum temperature at the interface can be increased to 950 ° C. or more within the thickness range of 30 nm to 250 nm.
  • the maximum temperature at the interface is set to 950 ° C. or more, and The maximum temperature reached on the surface can be made 1455 ° C. or lower.
  • Annealing can be performed under conditions where the maximum temperature reached 950 ° C. or higher and the surface maximum temperature reached 1455 ° C. or lower. That is, non-molten silicidation can be performed.
  • the pulse energy density required to increase the maximum temperature at the interface to 950 ° C. or higher increases as the pulse width increases. .
  • the pulse width is less than 10 ns, the surface is locally heated, making it difficult to transfer heat to the interface.
  • the pulse width is preferably 10 ns or more. If the pulse width is longer than 50 ns, the pulse energy density required for setting the maximum temperature at the interface to 950 ° C. or higher increases, and the annealing efficiency decreases. In order to perform efficient annealing, the pulse width is preferably 50 ns or less.
  • FIG. 6A to FIG. 6B preferable conditions for laser annealing when titanium is used for the metal film 16 (FIG. 1E) will be described.
  • a titanium film is formed on the surface of a substrate made of 4H—SiC and the titanium film is irradiated with a pulsed laser beam having a wavelength of 355 nm, the highest temperature at the interface between the substrate and the titanium film, and the highest surface of the titanium film The ultimate temperature was determined by simulation. 6A to 6B show the simulation results.
  • FIG. 6A shows the relationship between the maximum temperature reached at the interface between the substrate and the titanium film (hereinafter simply referred to as “interface”) and the thickness of the titanium film.
  • the horizontal axis represents the thickness of the titanium film in the unit “nm”, and the vertical axis represents the maximum temperature reached at the interface in the unit “° C.”.
  • FIG. 6B shows the relationship between the maximum temperature reached on the surface of the titanium film (hereinafter simply referred to as “surface”) and the thickness of the titanium film.
  • the abscissa represents the thickness of the titanium film in the unit “nm”, and the ordinate represents the highest surface temperature in the unit “° C.”.
  • the pulse width Pw of the pulse laser beam was 10 ns.
  • the rhombus symbols, square symbols, triangle symbols, and circle symbols in FIGS. 6A and 6B each have a pulse energy density (hereinafter simply referred to as “pulse energy density”) of 0.8 J / cm 2 on the surface of the titanium film.
  • pulse energy density 0.8 J / cm 2 on the surface of the titanium film.
  • the maximum temperature at the interface can be set to 950 ° C. or more within the range of the thickness of the titanium film of 30 nm to 150 nm.
  • the maximum temperature at the interface is set to 950 ° C. or more, and The highest surface temperature can be made 1668 ° C. or lower, which is the melting point of titanium.
  • the wavelength of the pulse laser beam is set to 355 nm, but it is possible to perform non-molten silicidation under substantially the same conditions using a pulse laser beam in the ultraviolet region with a wavelength of 300 nm to 400 nm.
  • a pulse laser beam a third harmonic of a solid-state laser such as an Nd: YAG laser, an Nd: YVO 4 laser, or an Nd: YLF laser, an excimer laser, or the like can be used.
  • the pulse laser beam 20 incident on the metal film 16 does not reach the second surface 10B of the substrate 10. For this reason, the temperature rise of the element structure 15 can be suppressed.
  • the pulse width Pw is set in the range of 10 ns to 50 ns, but there are annealing conditions that enable non-molten silicidation even in the range of the pulse width Pw of 50 ns or more.
  • the pulse width Pw is 50 ns or more, it is preferable to increase the pulse energy density in order to maintain a sufficient peak power density.

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  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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PCT/JP2013/077551 2012-12-20 2013-10-10 半導体装置の製造方法 WO2014097714A1 (ja)

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CN113345806A (zh) * 2021-04-23 2021-09-03 北京华卓精科科技股份有限公司 一种SiC基半导体的激光退火方法
CN113851374A (zh) * 2021-11-05 2021-12-28 南京航空航天大学 提高半导体材料放电加工效率的进电端表面预处理方法
CN114414747A (zh) * 2022-03-14 2022-04-29 绍兴中芯集成电路制造股份有限公司 激光退火均匀性的验证方法
CN117438297A (zh) * 2023-12-18 2024-01-23 合肥晶合集成电路股份有限公司 一种半导体器件及其制备方法

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JP6323252B2 (ja) * 2014-08-20 2018-05-16 住友電気工業株式会社 炭化珪素半導体装置の製造方法
JP2016046449A (ja) * 2014-08-26 2016-04-04 住友重機械工業株式会社 半導体素子の製造方法
JP6425457B2 (ja) * 2014-08-26 2018-11-21 住友重機械工業株式会社 半導体素子の製造方法
WO2016091488A1 (en) * 2014-12-08 2016-06-16 Abb Technology Ag Method for manufacturing a wide bandgap junction barrier schottky diode
JP2016127157A (ja) * 2015-01-05 2016-07-11 住友重機械工業株式会社 レーザアニール装置及び半導体素子の製造方法
JP6639922B2 (ja) * 2016-01-20 2020-02-05 国立大学法人広島大学 炭化珪素半導体装置及びその製造方法
JP2017224694A (ja) * 2016-06-15 2017-12-21 三菱電機株式会社 炭化珪素半導体装置およびその製造方法
JP7428481B2 (ja) * 2019-06-07 2024-02-06 住友重機械工業株式会社 レーザアニール方法及びレーザ制御装置

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