WO2012042667A1 - 部品内蔵基板の製造方法及びこれを用いた部品内蔵基板 - Google Patents

部品内蔵基板の製造方法及びこれを用いた部品内蔵基板 Download PDF

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Publication number
WO2012042667A1
WO2012042667A1 PCT/JP2010/067259 JP2010067259W WO2012042667A1 WO 2012042667 A1 WO2012042667 A1 WO 2012042667A1 JP 2010067259 W JP2010067259 W JP 2010067259W WO 2012042667 A1 WO2012042667 A1 WO 2012042667A1
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Prior art keywords
component
solder pad
dummy
conductive layer
actual
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PCT/JP2010/067259
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English (en)
French (fr)
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WO2012042667A9 (ja
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今村圭男
松本徹
清水良一
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株式会社メイコー
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Priority to JP2012536127A priority Critical patent/JP5525618B2/ja
Priority to KR1020137007858A priority patent/KR20130115230A/ko
Priority to PCT/JP2010/067259 priority patent/WO2012042667A1/ja
Priority to CN201080069364.5A priority patent/CN103125151B/zh
Priority to US13/824,437 priority patent/US9320185B2/en
Priority to EP10857880.8A priority patent/EP2624672A4/en
Priority to TW100129325A priority patent/TWI474768B/zh
Publication of WO2012042667A1 publication Critical patent/WO2012042667A1/ja
Publication of WO2012042667A9 publication Critical patent/WO2012042667A9/ja

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H05K1/0269—Marks, test patterns or identification means for visual or optical inspection
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R43/00—Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current collectors or for joining electric conductors
    • H01R43/02—Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current collectors or for joining electric conductors for soldered or welded connections
    • H01R43/0235—Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current collectors or for joining electric conductors for soldered or welded connections for applying solder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/188—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/83132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09918—Optically detected marks used for aligning tool relative to the PCB, e.g. for mounting of components

Definitions

  • the present invention relates to a method for manufacturing a component-embedded substrate capable of forming a pattern with high accuracy and a component-embedded substrate using the same.
  • a component-embedded substrate that incorporates electrical or electronic components (see, for example, Patent Document 1).
  • a component-embedded substrate represented by Patent Document 1 components are laminated with an insulating base material such as a prepreg, and then an outer conductive layer is patterned by etching or the like. When this pattern is formed, it is difficult to align the terminal of the component with the pattern. For this reason, a mark is formed of a conductive material such as copper on a core substrate made of an insulating base material having a hole through which a component can be inserted, and this core substrate is also laminated when the components are laminated.
  • the built-in mark is detected by X-rays, a through hole is provided in the mark portion, and pattern formation is performed using the through hole as a reference, thereby improving the position accuracy of the pattern.
  • forming the mark on the core substrate takes the same effort as the normal pattern formation, and this step is necessary.
  • a hole is formed in a conductive layer such as a copper foil in advance, a solder resist is formed on the basis of this hole, an X-ray drilling process is performed on the basis of the hole after lamination, and a guide hole on the basis of this X-ray hole.
  • a method in which processing is performed and a pattern is formed on the basis of this guide hole to improve the positional accuracy is performed and a pattern is formed on the basis of this guide hole to improve the positional accuracy.
  • there are many processes based on various holes and the accuracy is actually inferior. In reality, it is difficult to form a substrate because the resin of the prepreg flows into the holes of the conductive layer.
  • the present invention takes the above-described conventional technology into consideration, and does not require a troublesome process, and a method for manufacturing a component-embedded substrate that can form a pattern accurately on a built-in component, and a component-embedded substrate using the same The purpose is to provide.
  • a thin film conductive layer to be a conductor pattern is prepared, and a plurality of actual connection positions and at least one dummy connection position are formed on the conductive layer, except for a plurality of actual connection positions and at least one dummy connection position.
  • a mask layer is formed, and an actual solder pad and a dummy solder pad are respectively formed using solder at the actual connection position and the dummy connection position exposed from the conductive layer, and an electrical or electronic component is formed on the actual solder pad.
  • a connection terminal is connected, a resin insulating base material is formed which is laminated directly or through the mask layer and embedded with the component, and is formed on the conductive layer with reference to the dummy solder pad.
  • a method for manufacturing a component-embedded substrate is provided, wherein a part of the conductive pattern is formed by removing a part.
  • a reference hole penetrating the dummy solder pad and the conductive layer in contact with the dummy solder pad is formed, and a part of the conductive layer is removed using the reference hole as a reference.
  • an X-ray irradiation apparatus is used when the dummy solder pad is used as a reference.
  • the connection terminal is connected to the actual solder pad, the component is aligned based on the position of the dummy solder pad.
  • the insulating base material is further penetrated.
  • a component-embedded substrate using the component-embedded substrate manufacturing method according to claim 1, wherein the component includes the conductor pattern, the insulating base, and the component. Provide a built-in substrate.
  • the semiconductor device further includes a mask layer embedded in the insulating base material and forming the dummy connection position.
  • the semiconductor device further includes the dummy solder pad embedded in the insulating base material.
  • the actual connection position and the dummy connection position are formed on the conductive layer, they are formed on the same surface. Therefore, even when the conductive layer is displaced in the lateral direction, the distance between the actual connection position and the dummy connection position is maintained.
  • An actual solder pad is formed using solder at the actual connection position, and a component is connected to the actual solder pad.
  • a dummy solder pad is formed using solder at the dummy connection position, and a conductor pattern is formed using this dummy solder pad as a reference. Therefore, coupled with the fact that the relative positional relationship between the actual connection position and the dummy connection position is maintained, the relative positional accuracy between the component and the conductor pattern can be improved.
  • the dummy solder pad used for improving the positional accuracy can be formed in the same process as the formation of the actual solder pad for component mounting. That is, a troublesome process is not required for improving the positional accuracy of the conductor pattern. Further, since the actual solder pad and the dummy solder pad are formed in the same process, both are formed with the same accuracy. For this reason, the relative positional accuracy between the actual solder pad and the dummy solder pad is further improved.
  • a reference position can be clarified. Further, the dummy solder pad can be accurately detected by detecting the dummy solder pad with the X-ray irradiation apparatus.
  • the positional accuracy reference becomes the same as that of the conductor pattern, so that the relative positional accuracy between the two is improved.
  • a support plate 1 is prepared.
  • the support plate 1 is, for example, a SUS plate.
  • a thin conductive layer 2 is formed on the support plate 1.
  • the conductive layer 2 is, for example, copper plating.
  • a mask layer 3 is formed on the conductive layer 2.
  • the mask layer 3 is, for example, a solder resist, and is formed so as to expose a predetermined portion of the conductive layer 2. This exposed area becomes the actual connection position 4 and the dummy connection position 5.
  • the positions of the actual connection position 4 and the dummy connection position 5 are determined in advance. That is, the actual connection position 4 is to form an actual solder pad 6 (see FIG. 4) for mounting the component 8 (see FIG.
  • the position is determined in consideration.
  • the dummy connection position 5 is determined in consideration of forming dummy solder pads 7 (see FIG. 4) used for improving the positional accuracy of the conductor pattern 18.
  • an actual solder pad 6 is formed at the actual connection position 4 and a dummy solder pad 7 is formed at the dummy connection position using solder.
  • an electrical or electronic component 8 is prepared.
  • the connection terminal 9 of the component 8 and the actual solder pad 6 are connected. Thereby, the conductive layer 2 and the component 8 are electrically connected.
  • the insulating base materials 10 and 11 and the core substrate 12 are prepared.
  • the insulating base materials 10 and 11 and the core substrate 12 are made of resin.
  • the insulating base materials 10 and 11 are so-called prepregs.
  • the insulating base material 10 and the core substrate 12 have through holes 13 and 14, respectively.
  • the through holes 13 and 14 are formed in a size that allows the component 8 to be inserted.
  • the through holes 13 and 14 are formed at positions that are continuous when the insulating base material 10 and the core substrate 12 are laminated.
  • the parts 8 are passed through the through-holes 13 and 14, the insulating base material 11 is further stacked on the upper side, and the conductive layer 21 is further stacked on the upper side and pressed.
  • the support plate 1, the insulating base materials 10 and 11, and the core substrate 12 are laminated to form a laminated body 15.
  • the insulating base materials 10 and 11 are laminated and integrated, and the gaps between the through holes 13 and 14 are filled.
  • the insulating layer 16 composed of the insulating base materials 10 and 11 and the core substrate 12 is formed. Therefore, the component 8 is embedded in the insulating layer 16.
  • the through holes 10 and 11 are provided in advance, the pressure applied to the component 5 at the time of stacking can be suppressed. For this reason, even the large component 5 can be embedded in the insulating layer 16.
  • substrate 12 was used in the above, when lamination
  • the support plate 1 is removed.
  • the position of the dummy solder pad 7 is detected, and a reference hole 17 that penetrates the dummy solder pad 7 together with the conductive layer 2 is formed.
  • the position of the dummy solder pad 7 is detected using an X-ray irradiation apparatus (not shown) that can easily detect solder. As described above, by using the X-ray irradiation apparatus, the dummy solder pad 7 can be accurately detected.
  • the detection of the dummy solder pad 7 may be performed by removing the conductive layer 2 to expose the dummy solder pad 7 and directly recognizing it with a camera, or without embedding the dummy solder pad 7 in the insulating layer 16. It may be recognized by visually recognizing this.
  • the through-hole 22 which penetrates the insulating layer 16 and penetrates the conductive layer 2 formed in both surfaces of the insulating layer 16.
  • the plating process can be performed in the through-hole 22 to form the conductive plating 20, and conduction between both surfaces of the substrate can be achieved.
  • a part of the conductive layer 2 is removed by etching or the like to form a conductor pattern 18.
  • the component built-in substrate 19 is formed through the above steps.
  • the positional accuracy between the conductor pattern 18 and the component 8 can be increased. That is, since the actual connection position 4 and the dummy connection position 5 are formed in the conductive layer 2, the actual connection position 4 and the dummy connection position 5 are formed on the same surface. Therefore, even when the conductive layer 2 is displaced in the lateral direction, the distance between the actual connection position 4 and the dummy connection position 5 is maintained.
  • the component 8 is connected to the actual solder pad 6 formed at the actual connection position 4, and the conductor pattern 18 is formed with reference to the dummy solder pad 7 (reference hole 17) formed at the dummy connection position 5. Therefore, the relative positional accuracy between the component 8 and the conductor pattern 18 described above can be improved.
  • the dummy solder pad 7 used for improving the positional accuracy can be performed using the same apparatus in the same process as the formation of the actual solder pad 6 for mounting the component 5. For this reason, a troublesome process is not required for improving the positional accuracy of the conductor pattern 18. Since the actual solder pad 6 and the dummy solder pad 7 are formed in the same process, both are formed with the same accuracy. For this reason, the relative positional accuracy between the actual solder pad 6 and the dummy solder pad 7 is further improved. At the same time, a material for forming a mark, which has been used as a standard, is unnecessary, and there is no burden in terms of cost and labor.
  • the position of the component 8 may be aligned based on the position of the dummy solder pad 7.
  • the reference of the positional accuracy of the component 8 is the dummy solder pad 7 that is the same as that of the conductor pattern 18, the relative positional accuracy of the two 8 and 18 is improved.
  • the dummy solder pad 7 may be provided at any position as long as it is on the mounting surface of the component 8, that is, on the same surface as the actual solder pad 6.
  • the dummy solder pad 7 can adopt various shapes in combination with a solder resist.
  • it may be circular in plan view, or it may be cross-shaped in plan view as shown in FIG.
  • yen and the cross by planar view may be sufficient as shown in FIG. 13, and an annular
  • other shapes can be used.

Abstract

導体パターン（１８）となるべき薄膜の導電層を準備し、前記導電層上に複数の実接続位置及び少なくとも１個のダミー接続位置を除き、前記導電層上にマスク層（３）を形成し、前記導電層から露出した前記実接続位置及び前記ダミー接続位置に半田を用いて実半田パッド（６）及びダミー半田パッド（７）をそれぞれ形成し、前記実半田パッド（６）に電気又は電子的な部品（８）の接続端子（９）を接続し、前記導電層に直接又は前記マスク層（３）を介して積層され、且つ、前記部品（８）を埋設させた樹脂製の絶縁基材（１６）を形成し、前記ダミー半田バッド（７）を基準として前記導電層の一部を除去し、前記導体パターン（１８）を形成する。

Description

部品内蔵基板の製造方法及びこれを用いた部品内蔵基板
　本発明は、精度よくパターン形成できる部品内蔵基板の製造方法及びこれを用いた部品内蔵基板に関するものである。
　電気又は電子的な部品を内蔵した部品内蔵基板が知られている(例えば特許文献１参照)。特許文献１に代表されるような部品内蔵基板は、部品をプリプレグ等の絶縁基材で積層した後、外側の導電層をエッチング等によりパターン形成する。このパターン形成時、部品の端子とパターンとの位置合わせが困難である。このため、部品を挿通可能な孔を有する絶縁基材からなるコア基板に銅等の導電性物質でマークを形成し、部品積層時にこのコア基板も積層する。これにより、内蔵されたマークをＸ線で検出してマーク部分に貫通孔を設け、この貫通孔を基準にしてパターン成形し、パターンの位置精度の向上を図っている。しかしながら、コア基板にマークを形成するのは通常のパターン形成と同様の手間がかかり、その工程が必要となってくる。
　一方で、予め銅箔等の導電層に孔を設け、この孔を基準にソルダレジストを形成し、積層後に孔を基準にしてＸ線孔開け加工し、さらにこのＸ線孔を基準にガイド孔加工をし、さらにこのガイド孔を基準にパターン形成して位置精度を向上させようとする方法がある。しかしながら、種々の孔を基準にする工程が多く、実際にはその精度が劣っている。また、現実的には、導電層の孔にプリプレグの樹脂が流れ込み、基板として形成することは困難である。
特開２０１０－２７９１７号公報
　本発明は、上記従来技術を考慮したものであって、面倒な工程を必要とせず、内蔵された部品に対して精度よくパターン形成できる部品内蔵基板の製造方法及びこれを用いた部品内蔵基板を提供することを目的とする。
　前記目的を達成するため、本発明では、導体パターンとなるべき薄膜の導電層を準備し、前記導電層上に複数の実接続位置及び少なくとも１個のダミー接続位置を除き、前記導電層上にマスク層を形成し、前記導電層から露出した前記実接続位置及び前記ダミー接続位置に半田を用いて実半田パッド及びダミー半田パッドをそれぞれ形成し、前記実半田パッドに電気又は電子的な部品の接続端子を接続し、前記導電層に直接又は前記マスク層を介して積層され、且つ、前記部品を埋設させた樹脂製の絶縁基材を形成し、前記ダミー半田バッドを基準として前記導電層の一部を除去し、前記導体パターンを形成することを特徴とする部品内蔵基板の製造方法を提供する。
　好ましくは、前記導体パターンを形成するに際し、前記ダミー半田パッド及びこれに接する前記導電層を貫通する基準孔を形成し、前記基準孔を基準として前記導電層の一部を除去する。
　また、好ましくは、前記ダミー半田パッドを基準とする際、Ｘ線照射装置を用いる。
　また、好ましくは、前記実半田パッドに前記接続端子を接続する際、前記ダミー半田パッドの位置を基準として前記部品の位置合わせを行う。
　また、好ましくは、前記基準孔を形成する際、さらに前記絶縁基材を貫通させる。
　さらに本発明では、請求項１に記載の部品内蔵基板の製造方法を用いた部品内蔵基板であって、前記導体パターンと、前記絶縁基材と、前記部品とを備えたことを特徴とする部品内蔵基板を提供する。
　好ましくは、前記絶縁基材に埋設され、前記ダミー接続位置を形成するためのマスク層とをさらに備えた。
　また、好ましくは、前記絶縁基材に埋設され、前記ダミー半田パッドとをさらに備えた。
　本発明によれば、実接続位置及びダミー接続位置が導電層に形成されるため、これらは同一面上に形成される。したがって、導電層が横方向にずれた場合でも、実接続位置及びダミー接続位置の間隔は保たれたままである。この実接続位置に半田を用いて実半田パッドを形成し、この実半田パッドに対して部品を接続する。一方、ダミー接続位置に半田を用いてダミー半田パッドを形成し、このダミー半田パッドを基準として導体パターンを形成する。したがって、上記実接続位置とダミー接続位置との相対的な位置関係が保持されていることと相俟って、部品と導体パターンとの相対的な位置精度を向上させることができる。また、このような位置精度向上のために用いるダミー半田パッドは、部品搭載のための実半田パッドの形成と同様の工程で形成することができる。すなわち、導体パターンの位置精度向上のために面倒な工程が必要となることはない。また、実半田パッドとダミー半田パッドは同一の工程で形成されるので、両者は同一の精度で形成される。このため、実半田パッドとダミー半田パッドとの相対的な位置精度はさらに向上する。
　また、ダミー半田パッドを貫通する基準孔を設けることにより、基準となる位置を明確にすることができる。
　また、ダミー半田パッドをＸ線照射装置で検出することにより、ダミー半田パッドを正確に検出することができる。
　また、ダミー半田パッドの位置を基準として部品の位置合わせを行うことにより、位置精度の基準が導体パターンと同じになるので、両者の相対的な位置精度が向上する。
本発明に係る部品内蔵基板の製造方法を順番に示す概略図である。 本発明に係る部品内蔵基板の製造方法を順番に示す概略図である。 本発明に係る部品内蔵基板の製造方法を順番に示す概略図である。 本発明に係る部品内蔵基板の製造方法を順番に示す概略図である。 本発明に係る部品内蔵基板の製造方法を順番に示す概略図である。 本発明に係る部品内蔵基板の製造方法を順番に示す概略図である。 本発明に係る部品内蔵基板の製造方法を順番に示す概略図である。 本発明に係る部品内蔵基板の製造方法を順番に示す概略図である。 本発明に係る部品内蔵基板の製造方法を順番に示す概略図である。 本発明に係る部品内蔵基板の製造方法を用いた部品内蔵基板の一例を示す概略図である。 ダミー半田パッドの例を示す概略平面図である。 ダミー半田パッドの別の例を示す概略平面図である。 ダミー半田パッドのさらに別の例を示す概略平面図である。 ダミー半田パッドのさらに別の例を示す概略平面図である。
　図１に示すように、支持板１を用意する。支持板１は、例えばＳＵＳ板である。そして、図２に示すように、支持板１上に薄膜の導電層２を形成する。導電層２は、例えば銅めっきである。次に、図３に示すように、導電層２上にマスク層３を形成する。このマスク層３は、例えばソルダレジストであり、所定部分の導電層２を露出するようにして形成される。この露出した領域が実接続位置４及びダミー接続位置５となる。この実接続位置４及びダミー接続位置５の位置は、予め決められている。すなわち、実接続位置４は、導体パターン１８（図９参照）となるべき導電層２上に部品８（図５参照）を実装するための実半田パッド６（図４参照）を形成することを考慮してその位置が決定される。また、ダミー接続位置５は、導体パターン１８の位置精度向上のためとして用いるダミー半田パッド７（図４参照）を形成することを考慮してその位置が決定される。
　次に、図４に示すように、実接続位置４に実半田パッド６を、ダミー接続位置にダミー半田パッド７を半田を用いて形成する。そして、図５に示すように、電気又は電子的な部品８を用意する。この部品８の接続端子９と、実半田パッド６とを接続する。これにより、導電層２と部品８とが電気的に接続される。
　次に、図６に示すように、絶縁基材１０，１１及びコア基板１２を用意する。これら絶縁基材１０，１１及びコア基板１２は、互いに樹脂製である。絶縁基材１０，１１はいわゆるプリプレグである。絶縁基材１０及びコア基板１２は、それぞれ貫通孔１３，１４とを有している。この貫通孔１３，１４は、部品８が挿通可能な大きさに形成されている。貫通孔１３，１４は、絶縁基材１０及びコア基板１２を積層したときに連続するような位置に形成されている。この貫通孔１３，１４に部品８を通し、さらに上側に絶縁基材１１を重ね、さらにその上側に導電層２１を重ねて圧接する。
　これにより、図７に示すように、支持板１と絶縁基材１０，１１、さらにコア基板１２が積層され、積層体１５が形成される。このとき、絶縁基材１０，１１は積層されて一体化し、貫通孔１３，１４の隙間に充填される。これにより、絶縁基材１０，１１及びコア基板１２からなる絶縁層１６が形成される。したがって、部品８は絶縁層１６に埋設される。また、予め貫通孔１０，１１が設けられているため、積層時に部品５にかかる圧力を抑制できる。このため、大型の部品５であっても絶縁層１６内に埋設することができる。なお、上記ではコア基板１２を用いたが、貫通孔を設けなくても積層が可能な場合は、プリプレグのみで積層してもよい。この場合は、絶縁層１６が絶縁基材そのものとなる。
　そして、図８に示すように、支持板１を除去する。次に、ダミー半田パッド７の位置を検出し、導電層２とともにこのダミー半田パッド７を貫通する基準孔１７を形成する。ダミー半田パッド７の位置検出は、半田を容易に検出できるＸ線照射装置(不図示)を用いて行われる。このようにＸ線照射装置を用いることで、ダミー半田パッド７を正確に検出することができる。なお、ダミー半田パッド７の検出は、導電層２を削ってダミー半田パッド７を露出させ、これを直接カメラにて認識してもよいし、ダミー半田パッド７を絶縁層１６に埋設させずに、これを視認することで認識してもよい。
　そして、図９で示したように、絶縁層１６を貫通し、絶縁層１６の両面に形成された導電層２を貫通する貫通孔２２を形成してもよい。これにより、貫通孔２２内にめっき処理を施して導電めっき２０を形成し、基板両面の導通を図ることができる。
　そして、図１０に示すように、基準孔１７を基準として、導電層２の一部をエッチング等で除去し、導体パターン１８を形成する。以上の工程を経て、部品内蔵基板１９が形成される。
　このようにして部品内蔵基板１９を製造することにより、導体パターン１８と部品８との互いの位置精度を高めることができる。すなわち、実接続位置４及びダミー接続位置５が導電層２に形成されるため、実接続位置４及びダミー接続位置５は同一面上に形成される。したがって、導電層２が横方向にずれた場合でも、実接続位置４及びダミー接続位置５の間隔は保たれたままである。この実接続位置４に形成された実半田パッド６に対して部品８を接続し、ダミー接続位置５に形成されたダミー半田パッド７（基準孔１７）を基準として導体パターン１８を形成する。したがって、上述した部品８と導体パターン１８との相対的な位置精度を向上させることができる。
　また、このような位置精度向上のために用いるダミー半田パッド７は、部品５を搭載するための実半田パッド６の形成と同様の工程で同様の装置を用いて行うことができる。このため、導体パターン１８の位置精度向上のために面倒な工程が必要となることはない。また、実半田パッド６とダミー半田パッド７は同一の工程で形成されるので、両者は同一の精度で形成される。このため、実半田パッド６とダミー半田パッド７との相対的な位置精度はさらに向上する。これとともに、従来基準として用いていたマークのようなものを形成するための材料も不要であり、コスト的にも労力的にも負担がない。
　また、上述した実半田パッド６に接続端子９を接続する際、ダミー半田パッド７の位置を基準として部品８の位置合わせを行ってもよい。このようにすれば、部品８の位置精度の基準が導体パターン１８と同一のダミー半田パッド７となるので、両者８，１８の相対的な位置精度が向上する。なお、ダミー半田パッド７は部品８の実装面、すなわち実半田パッド６と同一面上であればどのような位置に設けてもよい。
　ダミー半田パッド７は、ソルダレジストと組み合わせて種々の形状を採用できる。例えば、図１１に示すように、平面視で円形でもよいし、図１２に示すように、平面視で十字形でもよい。また、図１３に示すように平面視で円と十字を重ねた形状でもよいし、図１４に示すように環状でもよい。もちろん、これ以外の形状も採用可能である。
１　支持板
２　導電層
３　マスク層
４　実接続位置
５　ダミー接続位置
６　実半田パッド
７　ダミー半田パッド
８　電気又は電子的な部品
９　接続端子
１０　絶縁基材
１１　絶縁基材
１２　コア基板
１３　貫通孔
１４　貫通孔
１５　積層体
１６　絶縁層
１７　基準孔
１８　導体パターン
１９　部品内蔵基板
２０　導電めっき
２１　導電層
２２　貫通孔

Claims (7)

  1. 　導体パターンとなるべき薄膜の導電層を準備し、
    　前記導電層上に複数の実接続位置及び少なくとも１個のダミー接続位置を除き、前記導電層上にマスク層を形成し、
    　前記導電層から露出した前記実接続位置及び前記ダミー接続位置に半田を用いて実半田パッド及びダミー半田パッドをそれぞれ形成し、
    　前記実半田パッドに電気又は電子的な部品の接続端子を接続し、
    　前記導電層に直接又は前記マスク層を介して積層され、且つ、前記部品を埋設させた樹脂製の絶縁基材を形成し、
    　前記ダミー半田バッドを基準として前記導電層の一部を除去し、前記導体パターンを形成することを特徴とする部品内蔵基板の製造方法。
  2. 　前記導体パターンを形成するに際し、前記ダミー半田パッド及びこれに接する前記導電層を貫通する基準孔を形成し、前記基準孔を基準として前記導電層の一部を除去することを特徴とする請求項１に記載の部品内蔵基板の製造方法。
  3. 　前記ダミー半田パッドを基準とする際、Ｘ線照射装置を用いることを特徴とする請求項１に記載の部品内蔵基板の製造方法。
  4. 　前記実半田パッドに前記接続端子を接続する際、前記ダミー半田パッドの位置を基準として前記部品の位置合わせを行うことを特徴とする請求項１に記載の部品内蔵基板の製造方法。
  5. 　請求項１に記載の部品内蔵基板の製造方法を用いた部品内蔵基板であって、
    　前記導体パターンと、前記絶縁基材と、前記部品とを備えたことを特徴とする部品内蔵基板。
  6. 　前記絶縁基材に埋設され、前記ダミー接続位置を形成するためのマスク層とをさらに備えたことを特徴とする請求項５に記載の部品内蔵基板。
  7. 　前記絶縁基材に埋設され、前記ダミー半田パッドとをさらに備えたことを特徴とする請求項５に記載の部品内蔵基板。
PCT/JP2010/067259 2010-10-01 2010-10-01 部品内蔵基板の製造方法及びこれを用いた部品内蔵基板 WO2012042667A1 (ja)

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WO2014125567A1 (ja) * 2013-02-12 2014-08-21 株式会社メイコー 部品内蔵基板及びその製造方法
KR20150110522A (ko) * 2013-01-18 2015-10-02 메이코 일렉트로닉스 컴파니 리미티드 부품내장기판 및 그 제조방법
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EP2624672A1 (en) 2013-08-07
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US20130242516A1 (en) 2013-09-19
CN103125151A (zh) 2013-05-29
TWI474768B (zh) 2015-02-21
EP2624672A4 (en) 2014-11-26
WO2012042667A9 (ja) 2013-08-22
CN103125151B (zh) 2016-09-07
TW201218897A (en) 2012-05-01
US9320185B2 (en) 2016-04-19

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