TWI474768B - A method of manufacturing a substrate having a built-in member, and a substrate for a built-in member manufactured by the method - Google Patents

A method of manufacturing a substrate having a built-in member, and a substrate for a built-in member manufactured by the method Download PDF

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TWI474768B
TWI474768B TW100129325A TW100129325A TWI474768B TW I474768 B TWI474768 B TW I474768B TW 100129325 A TW100129325 A TW 100129325A TW 100129325 A TW100129325 A TW 100129325A TW I474768 B TWI474768 B TW I474768B
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substrate
built
pad
manufacturing
conductive layer
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TW100129325A
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TW201218897A (en
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Yoshio Imamura
Tohru Matsumoto
Ryoichi Shimizu
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Meiko Electronics Co Ltd
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
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    • H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
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    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
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    • H01R43/02—Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current collectors or for joining electric conductors for soldered or welded connections
    • H01R43/0235—Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current collectors or for joining electric conductors for soldered or welded connections for applying solder
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    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/188—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
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    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
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    • H01L2224/8312—Aligning
    • H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
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    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
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Description

內藏元件之基板的製造方法及使用該方法製造之內藏元件的基板
本發明是關於一種可以良好之精度形成的內藏元件之基板的製造方法及使用該方法製造的內藏元件之基板。
內藏電子元件的內藏元件之基板已為一般所習知(範例請參照專利文獻1)。專利文獻1所代表的內藏元件之基板的形成方式為，藉由預浸材料等絕緣基材積層元件之後，再藉由蝕刻等技術對外側之導電層形成圖樣。當形成此圖樣時，元件之端子和圖樣的對位有困難。因此，在由有孔可以插通元件之絕緣基材構成的核心基板上，以銅等導電性物質形成遮罩，當積層元件時，也對此核心基板進行積層。藉此，以X光檢測出內藏之遮罩，在遮罩部份設置貫通孔，以此貫通孔為基準，形成圖樣，力求圖樣之位置精度之提昇。然而，在核心基板上形成遮罩和一般形成圖樣的情況都一樣麻煩，需要其中的製程。
另一方面，有一種方法為，預先在銅箔等導電層設置通孔，以此通孔為基準，形成阻焊膜，積層後，以通孔為基準，進行X光孔之開孔加工，然後，以此X光孔為基準，進行導孔加工，然後，以此導孔為基準，形成圖樣，以提高位置精度。然而，以各種通孔為基準的製程過多，實際上導致其精度劣化。又，在現實中，導電層之通孔會有預浸材料之樹脂流入，難以形成基板。
專利文獻1：特開2010-27917號公報
本發明為考慮上述習知技術之發明，目的在提供一種內藏元件之基板的製造方法及使用該方法製造的內藏元件之基板，其不需要麻煩的製程，可在內藏之元件上以良好之精度形成圖樣。
為達成上述目的，在本發明中，提供一種內藏元件之基板的製造方法，其特徵在於：準備將用來構成導體圖樣之薄膜導電層，在上述導電層上去除複數個實際連接位置及至少一個以上之虛擬連接位置，以在上述導電層上形成遮罩層，在從上述導電層露出之上述實際連接位置及上述虛擬連接位置上使用焊接技術分別形成實際焊墊及虛擬焊墊，在上述實際焊墊上連接電子元件之連接端子，在上述導電層上直接或透過上述遮罩層進行積層，並且，形成用來埋設上述元件之樹脂製絕緣基材，以上述虛擬焊墊為基準，去除上述導電層之一部分，形成上述導體圖樣。
更理想的發明為，當形成上述導體圖樣時，形成用來貫通上述虛擬焊墊及與其連接之上述導電層的基準孔，以上述基準孔為基準，去除上述導電層之一部分。
又，更理想的發明為，當以上述虛擬焊墊為基準時，使用X光照射裝置。
又，更理想的發明為，當在上述實際焊墊上連接上述連接端子時，以上述虛擬焊墊為基準，進行上述元件之對位。
又，更理想的發明為，當形成上述基準孔蝕，進一步貫通上述絕緣基材。
再者，在本發明中，提供一種內藏元件之基板，其為使用如申請專利範圍第1項之內藏元件之基板的製造方法製造的內藏元件之基板，其特徵在於：包括上述導體圖樣、上述絕緣基材及上述元件。
更理想的發明為，被上述絕緣基材埋設，並且進一步包括用來形成上述虛擬連接位置的遮罩層。
又，更理想的發明為，被上述絕緣基材埋設，並且進一步包括上述虛擬焊墊。
根據本發明，實際連接位置及虛擬連接位置形成於導電層，所以，它們形成於同一面上。於是，即使在導電層偏移到水平方向的情況下，實際連接位置及虛擬連接位置之間的間隔仍然可以保持。在此實際連接位置上使用焊接技術形成實際焊墊，在此實際焊墊上連接元件。另一方面，在虛擬連接位置上使用焊接技術形成虛擬焊墊，以此虛擬焊墊為基準，形成導體圖樣。於是，上述實際連接位置和虛擬連接位置的相對位置關係得以保持，同時，可提高元件和導體圖樣之間的相對位置精度。又，此種用來提高位置精度的虛擬焊墊之形成時所使用的製程可和用來搭載元件之實際焊墊之形成方式相同。亦即，若要提高導體圖樣之位置精度，不需要麻煩的製程。又，實際焊墊和虛擬焊墊以同一製程形成，所以，兩者以同一精度形成。因此，實際焊墊和虛擬焊墊的相對位置精度進一步提高。
又，藉由設置用來貫通虛擬焊墊的基準孔，可使作為基準之位置明確。
又，藉由使用X光照射裝置檢測出虛擬焊墊，可正確檢測出虛擬焊墊。
又，以虛擬焊墊之位置為基準，進行元件之對位，藉此，位置精度之基準與導體圖樣相同，所以，兩者的相對位置精度提高。
如第1圖所示，準備支持板1。支持板1可為SUS板。然後，如第2圖所示，在支持板1上形成薄膜之導電層2。導電層2可為銅鍍層。接著，如第3圖所示，在導電層2上形成遮罩層3。此遮罩層3可為阻焊膜，其露出既定部分之導電層2而形成。此露出之區域作為實際連接位置4及虛擬連接位置5。此實際連接位置4及虛擬連接位置5的位置可預先決定。亦即，實際連接位置4考慮實際焊墊6(參照第4圖)之形成，該實際焊墊6用來在即將形成導體圖樣18(參照第9圖)之導電層2上封裝元件8(參照第5圖)，然後再決定其位置。又，虛擬連接位置5考慮用來提高導體圖樣18之位置精度的虛擬焊墊7(參照第4圖)之形成，再決定其位置。
接著，如第4圖所示，在實際連接位置4上使用焊接技術形成實際焊墊6，在虛擬連接位置上形成虛擬焊墊7。然後，如第5圖所示，準備電子元件8。連接此元件8之連接端子9和實際焊墊6。藉此，導電層2和元件8作電子連接。
接著，如第6圖所示，準備絕緣基材10,11及核心基板12。絕緣基材10,11及核心基板12彼此為樹脂製。絕緣基材10,11為所謂的預浸材料。絕緣基材10及核心基板12分別具有貫通孔13,14。這些貫通孔13,14形成可插通元件8的大小。貫通孔13,14在積層絕緣基材10及核心基板12之後形成連續的位置。在這些貫通孔13,14上有元件8通過，而且在上側有絕緣基材11重疊，然後在其上側有導電層21重疊壓接。
藉此，如第7圖所示，形成積層體15。此時，絕緣基材10,11積層為一體化，填充於貫通孔13,14的間隙之中。藉此，形成由絕緣基材10,11及核心基板12所構成的絕緣層16。於是，元件8埋設於絕緣層16中。又，由於預先設置貫通孔10,11，所以可在積層時抑制對元件5產生的壓力。因此，即使是大型的元件5，也可埋設於絕緣層16內。此外，在上面的敘述中使用基板12，但在可不設置貫通孔而積層的情況下，也可僅以預浸材料來積層。在此情況下，絕緣層16為絕緣基材本身。
另外，如第8圖所示，去除支持板1。接著，檢測出虛擬焊墊7的位置，和導電層2一起形成貫通此虛擬焊墊7的基準孔17。關於虛擬焊墊7的位置檢測，採用容易檢測出焊接部位的X光照射裝置(未圖示)來進行。如此，藉由使用X光照射裝置，可正確檢測出虛擬焊墊7。此外，關於虛擬焊墊7的檢測，可切削導電層2使虛擬焊墊7露出，直接以相機來辨識，亦可不將虛擬焊墊7埋設於絕緣層16，以目測方式來辨認之。
另外，如第9圖所示，亦可貫通絕緣層16，形成貫通孔22以貫通形成於絕緣層16之兩面的導電層2。藉此，可在貫通孔22內施以鍍層處理以形成導電鍍層20，使基板兩面得以導通。
另外，如第10圖所示，以基準孔17為基準，使用蝕刻等技術去除導電層2之一部份，形成導體圖樣18。經過以上的製程，形成內藏元件之基板19。
如此，製造出內藏元件之基板19，藉此，可提高導體圖樣18和元件8彼此之間的位置精度。亦即，實際連接位置4及虛擬連接位置5形成於導電層2，所以，實際連接位置4及虛擬連接位置5形成於同一面上。於是，即使在導電層2偏移至水平方向的情況下，實際連接位置4及虛擬連接位置5之間的間隔仍然可以保持。在此實際連接位置4上所形成之實際焊墊6上，連接有元件8，以在虛擬連接位置5上所形成之虛擬焊墊7(基準孔17)為基準，形成導體圖樣18。於是，可提高上述元件8和導體圖樣18之間的相對位置精度。
又，若要形成此種用來提高位置精度的虛擬焊墊7，可採用製程與用來搭載元件5之實際焊墊6相同的裝置來進行。因此，若要提高導體圖樣18之位置精度，不需要麻煩的製程。又，實際焊墊6和虛擬焊墊7以同一製程形成，所以，兩者以同一精度形成。因此，實際焊墊6和虛擬焊墊7的相對位置精度進一步提高。同時，用來形成過去用來作基準之遮罩等元件的材料也不需要，沒有成本和勞力上的負擔。
又，當在上述實際焊墊6上連接連接端子9時，可以虛擬焊墊7的位置為基準，進行元件8的對位。如此，元件8之位置精度之基準變成與導體圖樣18相同的虛擬焊墊7，所以，兩者8,18的相對位置精度提高。此外，只要虛擬焊墊7和元件8的封裝面或者說實際焊墊6在同一面上，可設在任意位置。
虛擬焊墊7可和阻焊膜組合，採用各種形狀。例如，如第11圖所示，可為從平面看為圓形的形狀，如第12圖所示，可為從平面看為十字形的形狀。又，如第13圖所示，可為從平面看為圓形和十字形重疊的形狀，如第14圖所示，可為環狀。當然，亦可採用上述以外的形狀。
1．．．支持板
2．．．導電層
3．．．遮罩層
4．．．實際連接位置
5．．．虛擬連接位置
6．．．實際焊墊
7．．．虛擬焊墊
8．．．電子元件
9．．．連接端子
10．．．絕緣基材
11．．．絕緣基材
12．．．核心基板
13．．．貫通孔
14．．．貫通孔
15．．．積層體
16．．．絕緣層
17．．．基準孔
18．．．導體圖樣
19．．．內藏元件之基板
20．．．導電鍍層
21．．．導電層
22．．．貫通孔
第1圖為概略圖，依序表示本發明之內藏元件之基板的製造方法。
第2圖為概略圖，依序表示本發明之內藏元件之基板的製造方法。
第3圖為概略圖，依序表示本發明之內藏元件之基板的製造方法。
第4圖為概略圖，依序表示本發明之內藏元件之基板的製造方法。
第5圖為概略圖，依序表示本發明之內藏元件之基板的製造方法。
第6圖為概略圖，依序表示本發明之內藏元件之基板的製造方法。
第7圖為概略圖，依序表示本發明之內藏元件之基板的製造方法。
第8圖為概略圖，依序表示本發明之內藏元件之基板的製造方法。
第9圖為概略圖，依序表示本發明之內藏元件之基板的製造方法。
第10圖為概略圖，表示使用本發明之內藏元件之基板的製造方法來製造的內藏元件之基板之一例。
第11圖為概略平面圖，表示虛擬焊墊的範例。
第12圖為概略平面圖，表示虛擬焊墊的另一範例。
第13圖為概略平面圖，表示虛擬焊墊的又一範例。
第14圖為概略平面圖，表示虛擬焊墊的又一範例。
3．．．遮罩層
6．．．實際焊墊
7．．．虛擬焊墊
8．．．電子元件
9．．．連接端子
16．．．絕緣層
17．．．基準孔
18．．．導體圖樣
20．．．導電鍍層
22．．．貫通孔

Claims (7)

  1. 一種內藏元件之基板的製造方法，其特徵在於：準備將用來構成導體圖樣之薄膜導電層，在上述導電層上去除複數個實際連接位置及至少一個以上之虛擬連接位置，以在上述導電層上形成遮罩層，在從上述導電層露出之上述實際連接位置及上述虛擬連接位置上使用焊接技術分別形成實際焊墊及虛擬焊墊，在上述實際焊墊上連接電子元件之連接端子，在上述導電層上直接或透過上述遮罩層進行積層，並且，形成用來埋設上述元件之樹脂製絕緣基材，以上述虛擬焊墊為基準，去除上述導電層之一部分，形成上述導體圖樣。
  2. 如申請專利範圍第1項之內藏元件之基板的製造方法，其中，當形成上述導體圖樣時，形成用來貫通上述虛擬焊墊及與其連接之上述導電層的基準孔，以上述基準孔為基準，去除上述導電層之一部分。
  3. 如申請專利範圍第1項之內藏元件之基板的製造方法，其中，當以上述虛擬焊墊為基準時，使用X光照射裝置。
  4. 如申請專利範圍第1項之內藏元件之基板的製造方法，其中，當在上述實際焊墊上連接上述連接端子時，以上述虛擬焊墊為基準，進行上述元件之對位。
  5. 一種內藏元件之基板，使用如申請專利範圍第1項之內藏元件之基板的製造方法製造的內藏元件之基板，其特徵在於：包括上述導體圖樣、上述絕緣基材及上述元件。
  6. 如申請專利範圍第5項之內藏元件之基板的製造方法，其中，被上述絕緣基材埋設，並且進一步包括用來形成上述虛擬連接位置的遮罩層。
  7. 如申請專利範圍第5項之內藏元件之基板的製造方法，其中，被上述絕緣基材埋設，並且進一步包括上述虛擬焊墊。
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