JP5525618B2 - 部品内蔵基板の製造方法及びこれを用いた部品内蔵基板 - Google Patents
部品内蔵基板の製造方法及びこれを用いた部品内蔵基板 Download PDFInfo
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- JP5525618B2 JP5525618B2 JP2012536127A JP2012536127A JP5525618B2 JP 5525618 B2 JP5525618 B2 JP 5525618B2 JP 2012536127 A JP2012536127 A JP 2012536127A JP 2012536127 A JP2012536127 A JP 2012536127A JP 5525618 B2 JP5525618 B2 JP 5525618B2
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- 239000000758 substrate Substances 0.000 title claims description 33
- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 229910000679 solder Inorganic materials 0.000 claims description 75
- 239000000463 material Substances 0.000 claims description 22
- 239000004020 conductor Substances 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 16
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 238000007747 plating Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
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- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R43/00—Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current collectors or for joining electric conductors
- H01R43/02—Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current collectors or for joining electric conductors for soldered or welded connections
- H01R43/0235—Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current collectors or for joining electric conductors for soldered or welded connections for applying solder
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- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
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- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/188—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
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- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
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- H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
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- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
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- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8312—Aligning
- H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
- H01L2224/83132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09918—Optically detected marks used for aligning tool relative to the PCB, e.g. for mounting of components
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
また、好ましくは、前記実半田パッドに前記接続端子を接続する際、前記ダミー半田パッドの位置を基準として前記部品の位置合わせを行う。
さらに本発明では、請求項1に記載の部品内蔵基板の製造方法を用いた部品内蔵基板であって、前記導体パターンと、前記絶縁基材と、前記部品とを備えたことを特徴とする部品内蔵基板を提供する。
また、好ましくは、前記絶縁基材に埋設された前記ダミー半田パッドを備えている。
また、ダミー半田パッドをX線照射装置で検出することにより、ダミー半田パッドを正確に検出することができる。
そして、図10に示すように、基準孔17を基準として、導電層2の一部をエッチング等で除去し、導体パターン18を形成する。以上の工程を経て、部品内蔵基板19が形成される。
2 導電層
3 マスク層
4 実接続位置
5 ダミー接続位置
6 実半田パッド
7 ダミー半田パッド
8 電気又は電子的な部品
9 接続端子
10 絶縁基材
11 絶縁基材
12 コア基板
13 貫通孔
14 貫通孔
15 積層体
16 絶縁層
17 基準孔
18 導体パターン
19 部品内蔵基板
20 導電めっき
21 導電層
22 貫通孔
Claims (7)
- 導体パターンとなるべき薄膜の導電層を準備し、
前記導電層上に複数の実接続位置及び少なくとも1個のダミー接続位置を除き、前記導電層上にマスク層を形成し、
前記導電層から露出した前記実接続位置及び前記ダミー接続位置に半田を用いて実半田パッド及びダミー半田パッドをそれぞれ形成し、
前記実半田パッドに電気又は電子的な部品の接続端子を接続し、
前記導電層に直接又は前記マスク層を介して積層され、且つ、前記部品を埋設させた樹脂製の絶縁基材を形成し、
前記ダミー半田バッドを基準として前記導電層の一部を除去し、前記導体パターンを形成することを特徴とする部品内蔵基板の製造方法。 - 前記導体パターンを形成するに際し、前記ダミー半田パッド及びこれに接する前記導電層を貫通する基準孔を形成し、前記基準孔を基準として前記導電層の一部を除去することを特徴とする請求項1に記載の部品内蔵基板の製造方法。
- 前記ダミー半田パッドを基準とする際、X線照射装置を用いることを特徴とする請求項1に記載の部品内蔵基板の製造方法。
- 前記実半田パッドに前記接続端子を接続する際、前記ダミー半田パッドの位置を基準として前記部品の位置合わせを行うことを特徴とする請求項1に記載の部品内蔵基板の製造方法。
- 請求項1に記載の部品内蔵基板の製造方法を用いた部品内蔵基板であって、
前記導体パターンと、前記絶縁基材と、前記部品とを備えたことを特徴とする部品内蔵基板。 - 前記絶縁基材に埋設され、前記ダミー接続位置を形成するための前記マスク層を備えたことを特徴とする請求項5に記載の部品内蔵基板。
- 前記絶縁基材に埋設された前記ダミー半田パッドを備えたことを特徴とする請求項5に記載の部品内蔵基板。
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PCT/JP2010/067259 WO2012042667A1 (ja) | 2010-10-01 | 2010-10-01 | 部品内蔵基板の製造方法及びこれを用いた部品内蔵基板 |
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JPWO2012042667A1 JPWO2012042667A1 (ja) | 2014-02-03 |
JP5525618B2 true JP5525618B2 (ja) | 2014-06-18 |
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US (1) | US9320185B2 (ja) |
EP (1) | EP2624672A4 (ja) |
JP (1) | JP5525618B2 (ja) |
KR (1) | KR20130115230A (ja) |
CN (1) | CN103125151B (ja) |
TW (1) | TWI474768B (ja) |
WO (1) | WO2012042667A1 (ja) |
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EP2897447A4 (en) * | 2012-09-11 | 2016-05-25 | Meiko Electronics Co Ltd | METHOD FOR PRODUCING A SUBSTRATE WITH AN EMBEDDED COMPONENT AND SUBSTRATE PRODUCED IN THIS METHOD WITH AN EMBEDDED COMPONENT |
US9622352B2 (en) | 2012-09-26 | 2017-04-11 | Meiko Electronics Co., Ltd. | Manufacturing method for component incorporated substrate and component incorporated substrate |
JP6262153B2 (ja) * | 2013-01-18 | 2018-01-17 | 株式会社メイコー | 部品内蔵基板の製造方法 |
EP2958408A4 (en) * | 2013-02-12 | 2016-11-30 | Meiko Electronics Co Ltd | SUBSTRATE WITH A BUILT-IN COMPONENT AND MANUFACTURING METHOD THEREFOR |
JP6308007B2 (ja) * | 2013-07-16 | 2018-04-11 | ソニー株式会社 | 配線基板および配線基板の製造方法 |
KR102194718B1 (ko) * | 2014-10-13 | 2020-12-23 | 삼성전기주식회사 | 임베디드 기판 및 임베디드 기판의 제조 방법 |
CN106304611A (zh) * | 2015-06-10 | 2017-01-04 | 宏启胜精密电子(秦皇岛)有限公司 | 电路板及其制造方法、应用该电路板的电子装置 |
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2010
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- 2010-10-01 CN CN201080069364.5A patent/CN103125151B/zh not_active Expired - Fee Related
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JP2005159345A (ja) * | 2003-11-20 | 2005-06-16 | E I Du Pont De Nemours & Co | 基準のx線識別を用いて内層パネルおよび印刷回路板を製造する方法 |
JP2007027510A (ja) * | 2005-07-19 | 2007-02-01 | Fujikura Ltd | 実装基板及び電子部品の実装方法 |
JP2008300690A (ja) * | 2007-05-31 | 2008-12-11 | Icom Inc | 表面部品実装方法および表面部品実装用基板 |
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WO2012042667A1 (ja) | 2012-04-05 |
CN103125151A (zh) | 2013-05-29 |
KR20130115230A (ko) | 2013-10-21 |
TWI474768B (zh) | 2015-02-21 |
EP2624672A4 (en) | 2014-11-26 |
EP2624672A1 (en) | 2013-08-07 |
US9320185B2 (en) | 2016-04-19 |
JPWO2012042667A1 (ja) | 2014-02-03 |
CN103125151B (zh) | 2016-09-07 |
TW201218897A (en) | 2012-05-01 |
US20130242516A1 (en) | 2013-09-19 |
WO2012042667A9 (ja) | 2013-08-22 |
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