WO2005086233A3 - Bauelement mit wlp-fähiger verkapselung und herstellverfahren - Google Patents

Bauelement mit wlp-fähiger verkapselung und herstellverfahren Download PDF

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Publication number
WO2005086233A3
WO2005086233A3 PCT/EP2005/000327 EP2005000327W WO2005086233A3 WO 2005086233 A3 WO2005086233 A3 WO 2005086233A3 EP 2005000327 W EP2005000327 W EP 2005000327W WO 2005086233 A3 WO2005086233 A3 WO 2005086233A3
Authority
WO
WIPO (PCT)
Prior art keywords
component
wlp
production method
encapsulation
electrical
Prior art date
Application number
PCT/EP2005/000327
Other languages
English (en)
French (fr)
Other versions
WO2005086233A2 (de
Inventor
Wolfgang Pahl
Original Assignee
Epcos Ag
Wolfgang Pahl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Epcos Ag, Wolfgang Pahl filed Critical Epcos Ag
Priority to US10/591,027 priority Critical patent/US20070290374A1/en
Priority to JP2007501135A priority patent/JP2007526641A/ja
Publication of WO2005086233A2 publication Critical patent/WO2005086233A2/de
Publication of WO2005086233A3 publication Critical patent/WO2005086233A3/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09145—Edge details
    • H05K2201/0919—Exposing inner circuit layers or metal planes at the side edge of the PCB or at the walls of large holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Micromachines (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

Es wird vorgeschlagen, ein elektrisches Bauelement mit einer Abdeckung und insbesondere mit einer Leiterplatte zu verkapseln und die elektrischen Verbindungen mithilfe eines Leitklebers herzustellen. Dieser kann durch ein Kanalsystem in den Aufbau eingespritzt werden, wobei der elektrische Kurzschluss aller Verbindungen durch einen geeignet geführten Sägeschnitt beim Vereinzeln der Bauelemente wieder aufgetrennt werden kann.
PCT/EP2005/000327 2004-03-04 2005-01-14 Bauelement mit wlp-fähiger verkapselung und herstellverfahren WO2005086233A2 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US10/591,027 US20070290374A1 (en) 2004-03-04 2005-01-14 Component with Encapsulation Suitable for Wlp and Production Method
JP2007501135A JP2007526641A (ja) 2004-03-04 2005-01-14 Ｗｌｐ法で製造可能なパッケージング電気部品およびその製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102004010703.3 2004-03-04
DE102004010703.3A DE102004010703B4 (de) 2004-03-04 2004-03-04 Bauelement mit WLP-fähiger Verkapselung und Herstellverfahren

Publications (2)

Publication Number Publication Date
WO2005086233A2 WO2005086233A2 (de) 2005-09-15
WO2005086233A3 true WO2005086233A3 (de) 2006-01-12

Family

ID=34877388

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2005/000327 WO2005086233A2 (de) 2004-03-04 2005-01-14 Bauelement mit wlp-fähiger verkapselung und herstellverfahren

Country Status (6)

Country Link
US (1) US20070290374A1 (de)
JP (1) JP2007526641A (de)
KR (1) KR20070012659A (de)
CN (1) CN1930684A (de)
DE (1) DE102004010703B4 (de)
WO (1) WO2005086233A2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101084246B1 (ko) * 2009-12-28 2011-11-16 삼성모바일디스플레이주식회사 유기 발광 조명 장치
JP5549792B1 (ja) 2012-08-29 2014-07-16 株式会社村田製作所 弾性波装置
US10243286B2 (en) 2014-12-17 2019-03-26 Hewlett Packard Enterprise Development Lp Disabling device including adhesive to disable an electrical interface
KR20180055369A (ko) * 2016-11-17 2018-05-25 (주)와이솔 표면탄성파 소자 패키지 및 그 제작 방법

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0951062A2 (de) * 1998-04-18 1999-10-20 TDK Corporation Elektronikteil und seine Herstellung
US20020109133A1 (en) * 1999-02-23 2002-08-15 Junichi Hikita Semiconductor chip and semiconductor device using the same, and method of fabricating semiconductor chip

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6262477B1 (en) * 1993-03-19 2001-07-17 Advanced Interconnect Technologies Ball grid array electronic package

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0951062A2 (de) * 1998-04-18 1999-10-20 TDK Corporation Elektronikteil und seine Herstellung
US20020109133A1 (en) * 1999-02-23 2002-08-15 Junichi Hikita Semiconductor chip and semiconductor device using the same, and method of fabricating semiconductor chip

Also Published As

Publication number Publication date
DE102004010703B4 (de) 2015-03-12
CN1930684A (zh) 2007-03-14
US20070290374A1 (en) 2007-12-20
DE102004010703A1 (de) 2005-09-22
KR20070012659A (ko) 2007-01-26
WO2005086233A2 (de) 2005-09-15
JP2007526641A (ja) 2007-09-13

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